Maintenance scheduled 24th July -- expect downtime along that day

Commit 0b0fcfdb authored by Andrea Boccardi's avatar Andrea Boccardi

Synch problem and I am recommitting.

parent 52f1c4f3
...@@ -312,7 +312,7 @@ endtask ...@@ -312,7 +312,7 @@ endtask
always begin always begin
VmePrompt(); VmePrompt();
#1000; #100;
end end
/* /*
......
from VfcRegistersMap import * from VfcRegistersMap import *
import numpy as np import numpy as np
from time import sleep
class VFCInstance(VfcRegisters): class VFCInstance(VfcRegisters):
def __init__(self, Slot, IntLevel, IntVector): def __init__(self, Slot, IntLevel, IntVector):
...@@ -57,17 +58,25 @@ class VFCInstance(VfcRegisters): ...@@ -57,17 +58,25 @@ class VFCInstance(VfcRegisters):
elif Data<0 : elif Data<0 :
print "SPI data cannot be negative" print "SPI data cannot be negative"
else : else :
SpiStatusReg = self.SpiMasterStatus.Read() SpiStatusReg = self.SpiMasterStatus.Read()
print "SPI status reg is: ", hex(SpiStatusReg)
SpiState = (SpiStatusReg/2**16)&0x7 SpiState = (SpiStatusReg/2**16)&0x7
SpiFree = SpiState==4 or SpiState==0 SpiFree = SpiState==4 or SpiState==0
while SpiFree==False : while SpiFree==False :
SpiStatusReg = self.SpiMasterStatus.Read() SpiStatusReg = self.SpiMasterStatus.Read()
print "SPI status reg is: ", hex(SpiStatusReg)
SpiState = (SpiStatusReg/2**16)&0x7 SpiState = (SpiStatusReg/2**16)&0x7
SpiFree = SpiState==4 or SpiState==0 SpiFree = SpiState==4 or SpiState==0
Config1 = CPol*2**31 + CPha*2**30 + LSB1st*2**29 + Channel*2**16 + Lenght Config1 = CPol*2**31 + CPha*2**30 + LSB1st*2**29 + Channel*2**16 + Lenght
Config2 = HalfPeriod*2**16 + WaitTime Config2 = HalfPeriod*2**16 + WaitTime
print "SpiMasterConfig1 is: ", hex(self.SpiMasterConfig1.Read())
print "Setting it to: ", hex(Config1)
self.SpiMasterConfig1.Write(Config1) self.SpiMasterConfig1.Write(Config1)
print "SpiMasterConfig1 is: ", hex(self.SpiMasterConfig1.Read())
print "SpiMasterConfig2 is: ", hex(self.SpiMasterConfig2.Read())
print "Setting it to: ", hex(Config2)
self.SpiMasterConfig2.Write(Config2) self.SpiMasterConfig2.Write(Config2)
print "SpiMasterConfig2 is: ", hex(self.SpiMasterConfig2.Read())
Cycles=int(np.ceil(Lenght/32.0)) Cycles=int(np.ceil(Lenght/32.0))
ReadValue = 0 ReadValue = 0
if LSB1st==0 : if LSB1st==0 :
...@@ -75,20 +84,25 @@ class VFCInstance(VfcRegisters): ...@@ -75,20 +84,25 @@ class VFCInstance(VfcRegisters):
for i in range(Cycles): for i in range(Cycles):
if LSB1st : if LSB1st :
DataToSend = Data%2**32 DataToSend = Data%2**32
print "Writing in the SPI shiftout reg ", hex(DataToSend)
self.SpiMasterShiftOut.Write(DataToSend) self.SpiMasterShiftOut.Write(DataToSend)
Data = Data/2**32 Data = Data/2**32
else: else:
DataToSend = Data/2**(32*(Cycles-(i+1))) DataToSend = Data/2**(32*(Cycles-(i+1)))
print "Writing in the SPI shiftout reg ", hex(DataToSend)
self.SpiMasterShiftOut.Write(DataToSend) self.SpiMasterShiftOut.Write(DataToSend)
Data = Data%2**(32*(Cycles-(i+1))) Data = Data%2**(32*(Cycles-(i+1)))
SpiStatusReg = self.SpiMasterStatus.Read() SpiStatusReg = self.SpiMasterStatus.Read()
print "SPI status reg is: ", hex(SpiStatusReg)
SpiState = (SpiStatusReg/2**16)&0x7 SpiState = (SpiStatusReg/2**16)&0x7
SpiFree = SpiState==4 or SpiState==0 SpiFree = SpiState==4 or SpiState==0
while SpiFree==False : while SpiFree==False :
SpiStatusReg = self.SpiMasterStatus.Read() SpiStatusReg = self.SpiMasterStatus.Read()
print "SPI status reg is: ", hex(SpiStatusReg)
SpiState = (SpiStatusReg/2**16)&0x7 SpiState = (SpiStatusReg/2**16)&0x7
SpiFree = SpiState==4 or SpiState==0 SpiFree = SpiState==4 or SpiState==0
PartialShift = self.SpiMasterShiftIn.Read() PartialShift = self.SpiMasterShiftIn.Read()
print "Partial shift done with result: ", hex(PartialShift)
if LSB1st : if LSB1st :
if i==Cycles-1 : if i==Cycles-1 :
PartialShift = PartialShift/2**((32-Lenght%32)%32) PartialShift = PartialShift/2**((32-Lenght%32)%32)
......
...@@ -14,25 +14,22 @@ WaitSimulation('1000') ...@@ -14,25 +14,22 @@ WaitSimulation('1000')
VmeReset() VmeReset()
WaitSimulation('1000') WaitSimulation('1000')
print "Release: ", hex(MyBoard.ReleaseID.Read())
print""
print"Starting to check the SPI using the SPI feedback channell (31)"
print""
print "Checking the SPI master with short accesses with all the CPol CPha combinations and MSB 1st"
print""
print "Setting the Application FPGA SRAM1(0), SRAM1(1), SRAM2(0), SRAM2(1) to 3 to: 0x1a, 0x1b, 0x2a, 0x2b" print "SPI access CPol=0 CPha=0 MSB1st 8bit 0xaa halfperiod=4 wait=12"
MyBoard.ApplSram1.Write(0, 0x1a) Result = MyBoard.SpiAccess(31, 0, 0, 0, 8, 0xaa, 4, 12)
MyBoard.ApplSram1.Write(4, 0x1b) print "Obtained value: ", hex(Result)
MyBoard.ApplSram2.Write(0, 0x2a)
MyBoard.ApplSram2.Write(4, 0x2b)
print "Application FPGA SRAM1(0)is: ", hex(MyBoard.ApplSram1.Read(0))
print "Application FPGA SRAM1(1)is: ", hex(MyBoard.ApplSram1.Read(4))
print "Application FPGA SRAM2(0)is: ", hex(MyBoard.ApplSram2.Read(0))
print "Application FPGA SRAM2(1)is: ", hex(MyBoard.ApplSram2.Read(4))
WaitSimulation(10000) WaitSimulation(10000)
StopSimulation() StopSimulation()
exit() exit()
#SIMULATIN FLOW #SIMULATIN FLOW
...@@ -68,7 +65,7 @@ print "Application FPGA debug register 2 is: ", hex(MyBoard.ApplDebugReg2.Read() ...@@ -68,7 +65,7 @@ print "Application FPGA debug register 2 is: ", hex(MyBoard.ApplDebugReg2.Read()
print "Application FPGA debug register 3 is: ", hex(MyBoard.ApplDebugReg3.Read()) print "Application FPGA debug register 3 is: ", hex(MyBoard.ApplDebugReg3.Read())
WaitSimulation(10000) WaitSimulation(1000)
print"" print""
print"" print""
......
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