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Commit 265c6bd0 authored by Andrea Boccardi's avatar Andrea Boccardi
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added a doc, recompiled the system FPGA

parent cd70b752
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trunk/firmware/XilinxISE/SystemFpga/SFpga.bld
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...@@ -15,8 +15,8 @@ Checking Constraint Associations... ...@@ -15,8 +15,8 @@ Checking Constraint Associations...
Done... Done...
Checking expanded design ... Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'N450' has no driver WARNING:NgdBuild:452 - logical net 'N456' has no driver
WARNING:NgdBuild:452 - logical net 'N452' has no driver WARNING:NgdBuild:452 - logical net 'N458' has no driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver
...@@ -44,7 +44,7 @@ NGDBUILD Design Results Summary: ...@@ -44,7 +44,7 @@ NGDBUILD Design Results Summary:
Total memory usage is 155980 kilobytes Total memory usage is 155980 kilobytes
Writing NGD file "SFpga.ngd" ... Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 4 sec Total REAL time to NGDBUILD completion: 5 sec
Total CPU time to NGDBUILD completion: 3 sec Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "SFpga.bld"... Writing NGDBUILD log file "SFpga.bld"...
trunk/firmware/XilinxISE/SystemFpga/SFpga.cmd_log
View file @ 265c6bd0
...@@ -75,3 +75,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 - ...@@ -75,3 +75,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
trunk/firmware/XilinxISE/SystemFpga/SFpga.ncd
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trunk/firmware/XilinxISE/SystemFpga/SFpga.ngc
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trunk/firmware/XilinxISE/SystemFpga/SFpga.ngd
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trunk/firmware/XilinxISE/SystemFpga/SFpga.ngr
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trunk/firmware/XilinxISE/SystemFpga/SFpga.pad
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Release 12.3 - par M.70d (nt64) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 11:12:54 2010 Mon Dec 20 08:27:29 2010
# NOTE: This file is designed to be imported into a spreadsheet program # NOTE: This file is designed to be imported into a spreadsheet program
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.par
View file @ 265c6bd0
Release 12.3 par M.70d (nt64) Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
PCBE13225:: Fri Dec 17 11:12:22 2010 PCBE13225:: Mon Dec 20 08:26:58 2010
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
...@@ -21,38 +21,38 @@ Device speed data version: "PRODUCTION 1.12c 2010-09-15". ...@@ -21,38 +21,38 @@ Device speed data version: "PRODUCTION 1.12c 2010-09-15".
Device Utilization Summary: Device Utilization Summary:
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1% Number of Slice Registers: 812 out of 184,304 1%
Number used as Flip Flops: 796 Number used as Flip Flops: 812
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 934 out of 92,152 1% Number of Slice LUTs: 954 out of 92,152 1%
Number used as logic: 891 out of 92,152 1% Number used as logic: 911 out of 92,152 1%
Number using O6 output only: 571 Number using O6 output only: 573
Number using O5 output only: 154 Number using O5 output only: 172
Number using O5 and O6: 166 Number using O5 and O6: 166
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1% Number used as Memory: 13 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
Number using O6 output only: 4 Number using O6 output only: 4
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 4 Number using O5 and O6: 4
Number used as Single Port RAM: 0 Number used as Single Port RAM: 0
Number used as Shift Register: 3 Number used as Shift Register: 5
Number using O6 output only: 3 Number using O6 output only: 5
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 32 Number used exclusively as route-thrus: 30
Number with same-slice register load: 23 Number with same-slice register load: 21
Number with same-slice carry load: 9 Number with same-slice carry load: 9
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 374 out of 23,038 1% Number of occupied Slices: 365 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,101 Number of LUT Flip Flop pairs used: 1,098
Number with an unused Flip Flop: 386 out of 1,101 35% Number with an unused Flip Flop: 364 out of 1,098 33%
Number with an unused LUT: 167 out of 1,101 15% Number with an unused LUT: 144 out of 1,098 13%
Number of fully used LUT-FF pairs: 548 out of 1,101 49% Number of fully used LUT-FF pairs: 590 out of 1,098 53%
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0% to control set restrictions: 0 out of 184,304 0%
...@@ -99,8 +99,8 @@ Specific Feature Utilization: ...@@ -99,8 +99,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High Overall effort level (-ol): High
Router effort level (-rl): High Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 10 secs Starting initial Timing Analysis. REAL time: 9 secs
Finished initial Timing Analysis. REAL time: 10 secs Finished initial Timing Analysis. REAL time: 9 secs
WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal.
...@@ -152,29 +152,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O ...@@ -152,29 +152,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
Starting Router Starting Router
Phase 1 : 5227 unrouted; REAL time: 12 secs Phase 1 : 5256 unrouted; REAL time: 11 secs
Phase 2 : 4601 unrouted; REAL time: 15 secs Phase 2 : 4603 unrouted; REAL time: 15 secs
Phase 3 : 1750 unrouted; REAL time: 21 secs Phase 3 : 1808 unrouted; REAL time: 20 secs
Phase 4 : 1750 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 26 secs Phase 4 : 1808 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Updating file: SFpga.ncd with current fully routed design. Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 28 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 30 secs Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Total REAL time to Router completion: 30 secs Total REAL time to Router completion: 29 secs
Total CPU time to Router completion: 29 secs Total CPU time to Router completion: 28 secs
Partition Implementation Status Partition Implementation Status
------------------------------- -------------------------------
...@@ -192,18 +192,18 @@ Generating Clock Report ...@@ -192,18 +192,18 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 229 | 0.260 | 1.710 | | Si57x_BUFG | BUFGMUX_X2Y4| No | 220 | 0.242 | 1.696 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.009 | 1.640 | | VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.008 | 1.643 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| VcTcXo_ik_BUFGP | BUFGMUX_X3Y16| No | 6 | 0.083 | 1.644 | | VcTcXo_ik_BUFGP | BUFGMUX_X3Y16| No | 6 | 0.083 | 1.644 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.186 | 1.693 | | SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.189 | 1.693 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| i_Core/Rst_rq | Local| | 223 | 0.000 | 7.868 | | i_Core/Rst_rq | Local| | 211 | 0.000 | 3.873 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | | |i_Core/i_VmeInterfac | | | | | |
| e/stb_o | Local| | 19 | 0.000 | 4.686 | | e/stb_o | Local| | 19 | 0.000 | 4.113 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing * Net Skew is the difference between the minimum and maximum routing
...@@ -220,11 +220,11 @@ Asterisk (*) preceding a constraint indicates it was not met. ...@@ -220,11 +220,11 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score | | Slack | Achievable | Errors | Score
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.435ns| 7.898ns| 0| 0 TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.429ns| 7.904ns| 0| 0
20 MHz HIGH 50% | HOLD | 0.413ns| | 0| 0 20 MHz HIGH 50% | HOLD | 0.225ns| | 0| 0
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 4.464ns| 3.869ns| 0| 0 TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 4.826ns| 3.507ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.442ns| | 0| 0 lk_ik" 120 MHz HIGH 50% | HOLD | 0.468ns| | 0| 0
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
...@@ -237,10 +237,10 @@ All signals are completely routed. ...@@ -237,10 +237,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 47 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. WARNING:Par:283 - There are 47 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 32 secs Total REAL time to PAR completion: 31 secs
Total CPU time to PAR completion: 32 secs Total CPU time to PAR completion: 31 secs
Peak Memory Usage: 546 MB Peak Memory Usage: 545 MB
Placer: Placement generated during map. Placer: Placement generated during map.
Routing: Completed - No errors found. Routing: Completed - No errors found.
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.pcf
View file @ 265c6bd0
//! ************************************************************************** //! **************************************************************************
// Written by: Map M.70d on Fri Dec 17 11:12:18 2010 // Written by: Map M.70d on Mon Dec 20 08:26:52 2010
//! ************************************************************************** //! **************************************************************************
SCHEMATIC START; SCHEMATIC START;
...@@ -333,7 +333,8 @@ COMP "FlashAFpgaClk_ok" LOCATE = SITE "AC22" LEVEL 1; ...@@ -333,7 +333,8 @@ COMP "FlashAFpgaClk_ok" LOCATE = SITE "AC22" LEVEL 1;
COMP "VmeTms_i" LOCATE = SITE "D21" LEVEL 1; COMP "VmeTms_i" LOCATE = SITE "D21" LEVEL 1;
COMP "Fmc2PrsntM2C_in" LOCATE = SITE "U1" LEVEL 1; COMP "Fmc2PrsntM2C_in" LOCATE = SITE "U1" LEVEL 1;
COMP "PllFmc1Pd_on" LOCATE = SITE "AD4" LEVEL 1; COMP "PllFmc1Pd_on" LOCATE = SITE "AD4" LEVEL 1;
TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_23" BEL
"i_Core/Si57xDivider_c_22" BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL "i_Core/Si57xDivider_c_20" BEL "i_Core/Si57xDivider_c_19" BEL
"i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL "i_Core/Si57xDivider_c_18" BEL "i_Core/Si57xDivider_c_17" BEL
"i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL "i_Core/Si57xDivider_c_16" BEL "i_Core/Si57xDivider_c_15" BEL
...@@ -435,6 +436,12 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL ...@@ -435,6 +436,12 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_VmeInterface/DataReg_2" BEL "i_Core/i_VmeInterface/DataReg_2" BEL
"i_Core/i_VmeInterface/DataReg_1" BEL "i_Core/i_VmeInterface/DataReg_1" BEL
"i_Core/i_VmeInterface/DataReg_0" BEL "i_Core/i_VmeInterface/DataReg_0" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_25" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_24" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_23" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_22" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_21" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_20" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_19" BEL "i_Core/i_VmeAccessMonostable/Counter_c_19" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_18" BEL "i_Core/i_VmeAccessMonostable/Counter_c_18" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_17" BEL "i_Core/i_VmeAccessMonostable/Counter_c_17" BEL
...@@ -455,9 +462,13 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL ...@@ -455,9 +462,13 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_2" BEL "i_Core/i_VmeAccessMonostable/Counter_c_2" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_1" BEL "i_Core/i_VmeAccessMonostable/Counter_c_1" BEL
"i_Core/i_VmeAccessMonostable/Counter_c_0" BEL "i_Core/i_VmeAccessMonostable/Counter_c_0" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db3_2" BEL "i_Core/i_VmeAccessMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db3_1" BEL "i_Core/i_ClearMonostable/Counter_c_25" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db3_0" BEL "i_Core/i_ClearMonostable/Counter_c_24" BEL
"i_Core/i_ClearMonostable/Counter_c_23" BEL
"i_Core/i_ClearMonostable/Counter_c_22" BEL
"i_Core/i_ClearMonostable/Counter_c_21" BEL
"i_Core/i_ClearMonostable/Counter_c_20" BEL
"i_Core/i_ClearMonostable/Counter_c_19" BEL "i_Core/i_ClearMonostable/Counter_c_19" BEL
"i_Core/i_ClearMonostable/Counter_c_18" BEL "i_Core/i_ClearMonostable/Counter_c_18" BEL
"i_Core/i_ClearMonostable/Counter_c_17" BEL "i_Core/i_ClearMonostable/Counter_c_17" BEL
...@@ -478,9 +489,7 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL ...@@ -478,9 +489,7 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_ClearMonostable/Counter_c_2" BEL "i_Core/i_ClearMonostable/Counter_c_2" BEL
"i_Core/i_ClearMonostable/Counter_c_1" BEL "i_Core/i_ClearMonostable/Counter_c_1" BEL
"i_Core/i_ClearMonostable/Counter_c_0" BEL "i_Core/i_ClearMonostable/Counter_c_0" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db3_2" BEL "i_Core/i_ClearMonostable/AsynchInAX_db4_3" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db3_1" BEL
"i_Core/i_ClearMonostable/AsynchInAX_db3_0" BEL
"i_Core/i_Debouncer/Counter_c_15" BEL "i_Core/i_Debouncer/Counter_c_15" BEL
"i_Core/i_Debouncer/Counter_c_14" BEL "i_Core/i_Debouncer/Counter_c_14" BEL
"i_Core/i_Debouncer/Counter_c_13" BEL "i_Core/i_Debouncer/Counter_c_13" BEL
...@@ -959,11 +968,15 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL ...@@ -959,11 +968,15 @@ TIMEGRP Si57x_ik = BEL "i_Core/Si57xDivider_c_21" BEL
"i_Core/i_VmeInterface/AckTimeout_c_1" BEL "i_Core/i_VmeInterface/AckTimeout_c_1" BEL
"i_Core/i_VmeInterface/AckTimeout_c_3" BEL "i_Core/i_VmeInterface/AckTimeout_c_3" BEL
"i_Core/i_VmeInterface/AckTimeout_c_0" BEL "Si57x_BUFG" BEL "i_Core/i_VmeInterface/AckTimeout_c_0" BEL "Si57x_BUFG" BEL
"i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0" BEL "i_Core/i_ClearMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_Slv2SerWB/AckI_xb3_0" BEL "i_Core/Mshreg_VmeSysReset_dx_1" "i_Core/i_ClearMonostable/AsynchInAX_db4_2" BEL
BEL "i_Core/VmeSysReset_dx_1" BEL "i_Core/Mshreg_VmeSysReset_dx_1" BEL "i_Core/VmeSysReset_dx_1" BEL
"i_Core/i_VmeAccessMonostable/Mshreg_AsynchInAX_db4_2" BEL
"i_Core/i_VmeAccessMonostable/AsynchInAX_db4_2" BEL
"i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2" BEL "i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2" BEL
"i_Core/i_Debouncer/BouncingSignal_x_2" BEL "PllSysRef12_ok" BEL "i_Core/i_Debouncer/BouncingSignal_x_2" BEL
"i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0" BEL
"i_Core/i_Slv2SerWB/AckI_xb3_0" BEL "PllSysRef12_ok" BEL
"PllSysRef12_okn" BEL "SysAppClk_ok" BEL "PllFmc1Ref1_ok" BEL "PllSysRef12_okn" BEL "SysAppClk_ok" BEL "PllFmc1Ref1_ok" BEL
"PllFmc2Ref1_ok" BEL "PllDdsClk_ok" BEL "PllFmc2Ref1_ok" BEL "PllDdsClk_ok" BEL
"i_Core/i_InterruptManager/Mram_int_fifo21/DP" BEL "i_Core/i_InterruptManager/Mram_int_fifo21/DP" BEL
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.ptwx
View file @ 265c6bd0
...@@ -329,4 +329,4 @@ ...@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)> <!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)> <!ELEMENT twValue (#PCDATA)>
]> ]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.435" best="7.898" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.413" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="4.464" best="3.869" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.442" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport> <twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.429" best="7.904" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.225" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="4.826" best="3.507" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.468" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
trunk/firmware/XilinxISE/SystemFpga/SFpga.syr
View file @ 265c6bd0
...@@ -4,13 +4,13 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. ...@@ -4,13 +4,13 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.20 secs Total CPU time to Xst completion: 0.52 secs
--> Parameter xsthdpdir set to xst --> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.20 secs Total CPU time to Xst completion: 0.52 secs
--> Reading design: SFpga.prj --> Reading design: SFpga.prj
...@@ -273,14 +273,14 @@ WARNING:Xst:653 - Signal <Gbit1Sys2App_o> is used but never assigned. This sourc ...@@ -273,14 +273,14 @@ WARNING:Xst:653 - Signal <Gbit1Sys2App_o> is used but never assigned. This sourc
WARNING:Xst:653 - Signal <Gbit2Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal <Gbit2Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit3Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal <Gbit3Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND. WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
Found 22-bit register for signal <VcTcXoDivider_c>. Found 24-bit register for signal <VcTcXoDivider_c>.
Found 22-bit register for signal <VmeSysClkDivider_c>. Found 24-bit register for signal <VmeSysClkDivider_c>.
Found 2-bit register for signal <VmeSysReset_dx>. Found 2-bit register for signal <VmeSysReset_dx>.
Found 1-bit register for signal <Rst_rq>. Found 1-bit register for signal <Rst_rq>.
Found 22-bit register for signal <Si57xDivider_c>. Found 24-bit register for signal <Si57xDivider_c>.
Found 22-bit adder for signal <Si57xDivider_c[21]_GND_2_o_add_9_OUT> created at line 380. Found 24-bit adder for signal <Si57xDivider_c[23]_GND_2_o_add_9_OUT> created at line 380.
Found 22-bit adder for signal <VcTcXoDivider_c[21]_GND_2_o_add_12_OUT> created at line 383. Found 24-bit adder for signal <VcTcXoDivider_c[23]_GND_2_o_add_12_OUT> created at line 383.
Found 22-bit adder for signal <VmeSysClkDivider_c[21]_GND_2_o_add_15_OUT> created at line 386. Found 24-bit adder for signal <VmeSysClkDivider_c[23]_GND_2_o_add_15_OUT> created at line 386.
Found 1-bit 4-to-1 multiplexer for signal <a_FpLed7> created at line 388. Found 1-bit 4-to-1 multiplexer for signal <a_FpLed7> created at line 388.
Found 1-bit tristate buffer for signal <WRModeDef2_io> created at line 296 Found 1-bit tristate buffer for signal <WRModeDef2_io> created at line 296
Found 1-bit tristate buffer for signal <Sfp2ModeDef2_io> created at line 300 Found 1-bit tristate buffer for signal <Sfp2ModeDef2_io> created at line 300
...@@ -317,22 +317,22 @@ WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourc ...@@ -317,22 +317,22 @@ WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourc
Found 1-bit tristate buffer for signal <VAdjInhibit_ozn> created at line 634 Found 1-bit tristate buffer for signal <VAdjInhibit_ozn> created at line 634
Summary: Summary:
inferred 3 Adder/Subtractor(s). inferred 3 Adder/Subtractor(s).
inferred 69 D-type flip-flop(s). inferred 75 D-type flip-flop(s).
inferred 1 Multiplexer(s). inferred 1 Multiplexer(s).
inferred 33 Tristate(s). inferred 33 Tristate(s).
Unit <SystemFpga> synthesized. Unit <SystemFpga> synthesized.
Synthesizing Unit <Monostable>. Synthesizing Unit <Monostable>.
Related source file is "/vfc_svn/hdl/design/monostable.v". Related source file is "/vfc_svn/hdl/design/monostable.v".
g_CounterBits = 20 g_CounterBits = 26
Found 3-bit register for signal <AsynchInAX_db3>. Found 4-bit register for signal <AsynchInAX_db4>.
Found 20-bit register for signal <Counter_c>. Found 26-bit register for signal <Counter_c>.
Found 1-bit register for signal <SynchOutput_oq>. Found 1-bit register for signal <SynchOutput_oq>.
Found 1-bit register for signal <AsynchIn_ax>. Found 1-bit register for signal <AsynchIn_ax>.
Found 20-bit adder for signal <Counter_c[19]_GND_25_o_add_6_OUT> created at line 20. Found 26-bit adder for signal <Counter_c[25]_GND_25_o_add_6_OUT> created at line 20.
Summary: Summary:
inferred 1 Adder/Subtractor(s). inferred 1 Adder/Subtractor(s).
inferred 25 D-type flip-flop(s). inferred 32 D-type flip-flop(s).
Unit <Monostable> synthesized. Unit <Monostable> synthesized.
Synthesizing Unit <Debouncer>. Synthesizing Unit <Debouncer>.
...@@ -611,8 +611,9 @@ Macro Statistics ...@@ -611,8 +611,9 @@ Macro Statistics
# Adders/Subtractors : 13 # Adders/Subtractors : 13
12-bit adder : 1 12-bit adder : 1
16-bit adder : 2 16-bit adder : 2
20-bit adder : 2 22-bit adder : 1
22-bit adder : 4 24-bit adder : 3
26-bit adder : 2
3-bit adder : 2 3-bit adder : 2
4-bit addsub : 1 4-bit addsub : 1
9-bit adder : 1 9-bit adder : 1
...@@ -621,12 +622,13 @@ Macro Statistics ...@@ -621,12 +622,13 @@ Macro Statistics
12-bit register : 1 12-bit register : 1
16-bit register : 2 16-bit register : 2
2-bit register : 4 2-bit register : 4
20-bit register : 2 22-bit register : 1
22-bit register : 4 24-bit register : 3
3-bit register : 6 26-bit register : 2
3-bit register : 4
31-bit register : 1 31-bit register : 1
32-bit register : 15 32-bit register : 15
4-bit register : 1 4-bit register : 3
7-bit register : 1 7-bit register : 1
8-bit register : 3 8-bit register : 3
9-bit register : 1 9-bit register : 1
...@@ -653,7 +655,7 @@ Macro Statistics ...@@ -653,7 +655,7 @@ Macro Statistics
1-bit tristate buffer : 65 1-bit tristate buffer : 65
# FSMs : 2 # FSMs : 2
# Xors : 4 # Xors : 4
1-bit xor3 : 2 1-bit xor2 : 2
1-bit xor6 : 2 1-bit xor6 : 2
========================================================================= =========================================================================
...@@ -720,13 +722,13 @@ Macro Statistics ...@@ -720,13 +722,13 @@ Macro Statistics
3-bit adder : 2 3-bit adder : 2
# Counters : 10 # Counters : 10
16-bit up counter : 1 16-bit up counter : 1
20-bit up counter : 2 24-bit up counter : 3
22-bit up counter : 3 26-bit up counter : 2
3-bit up counter : 2 3-bit up counter : 2
4-bit updown counter : 1 4-bit updown counter : 1
9-bit up counter : 1 9-bit up counter : 1
# Registers : 680 # Registers : 682
Flip-Flops : 680 Flip-Flops : 682
# Comparators : 9 # Comparators : 9
1-bit comparator equal : 1 1-bit comparator equal : 1
12-bit comparator equal : 1 12-bit comparator equal : 1
...@@ -747,7 +749,7 @@ Macro Statistics ...@@ -747,7 +749,7 @@ Macro Statistics
7-bit 2-to-1 multiplexer : 1 7-bit 2-to-1 multiplexer : 1
# FSMs : 2 # FSMs : 2
# Xors : 4 # Xors : 4
1-bit xor3 : 2 1-bit xor2 : 2
1-bit xor6 : 2 1-bit xor6 : 2
========================================================================= =========================================================================
...@@ -832,6 +834,8 @@ Final Macro Processing ... ...@@ -832,6 +834,8 @@ Final Macro Processing ...
Processing Unit <SFpga> : Processing Unit <SFpga> :
Found 2-bit shift register for signal <i_Core/VmeSysReset_dx_1>. Found 2-bit shift register for signal <i_Core/VmeSysReset_dx_1>.
Found 3-bit shift register for signal <i_Core/i_VmeAccessMonostable/AsynchInAX_db4_2>.
Found 3-bit shift register for signal <i_Core/i_ClearMonostable/AsynchInAX_db4_2>.
Found 3-bit shift register for signal <i_Core/i_Debouncer/BouncingSignal_x_2>. Found 3-bit shift register for signal <i_Core/i_Debouncer/BouncingSignal_x_2>.
Found 2-bit shift register for signal <i_Core/i_Slv2SerWB/AckI_xb3_0>. Found 2-bit shift register for signal <i_Core/i_Slv2SerWB/AckI_xb3_0>.
Unit <SFpga> processed. Unit <SFpga> processed.
...@@ -840,11 +844,11 @@ Unit <SFpga> processed. ...@@ -840,11 +844,11 @@ Unit <SFpga> processed.
Final Register Report Final Register Report
Macro Statistics Macro Statistics
# Registers : 793 # Registers : 807
Flip-Flops : 793 Flip-Flops : 807
# Shift Registers : 3 # Shift Registers : 5
2-bit shift register : 2 2-bit shift register : 2
3-bit shift register : 1 3-bit shift register : 3
========================================================================= =========================================================================
...@@ -867,32 +871,32 @@ Top Level Output File Name : SFpga.ngc ...@@ -867,32 +871,32 @@ Top Level Output File Name : SFpga.ngc
Primitive and Black Box Usage: Primitive and Black Box Usage:
------------------------------ ------------------------------
# BELS : 1430 # BELS : 1497
# GND : 1 # GND : 1
# INV : 29 # INV : 29
# LUT1 : 163 # LUT1 : 181
# LUT2 : 163 # LUT2 : 166
# LUT3 : 121 # LUT3 : 130
# LUT4 : 112 # LUT4 : 113
# LUT5 : 148 # LUT5 : 146
# LUT6 : 307 # LUT6 : 299
# MUXCY : 186 # MUXCY : 204
# MUXF7 : 18 # MUXF7 : 28
# VCC : 1 # VCC : 1
# XORCY : 181 # XORCY : 199
# FlipFlops/Latches : 796 # FlipFlops/Latches : 812
# FD : 189 # FD : 191
# FDE : 99 # FDE : 101
# FDPE : 1 # FDPE : 1
# FDR : 135 # FDR : 135
# FDRE : 313 # FDRE : 325
# FDS : 26 # FDS : 26
# FDSE : 33 # FDSE : 33
# RAMS : 3 # RAMS : 3
# RAM16X1D : 2 # RAM16X1D : 2
# RAM32M : 1 # RAM32M : 1
# Shift Registers : 3 # Shift Registers : 5
# SRLC16E : 3 # SRLC16E : 5
# Clock Buffers : 4 # Clock Buffers : 4
# BUFG : 1 # BUFG : 1
# BUFGP : 3 # BUFGP : 3
...@@ -912,18 +916,18 @@ Selected Device : 6slx150tfgg676-3 ...@@ -912,18 +916,18 @@ Selected Device : 6slx150tfgg676-3
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 796 out of 184304 0% Number of Slice Registers: 812 out of 184304 0%
Number of Slice LUTs: 1054 out of 92152 1% Number of Slice LUTs: 1077 out of 92152 1%
Number used as Logic: 1043 out of 92152 1% Number used as Logic: 1064 out of 92152 1%
Number used as Memory: 11 out of 21680 0% Number used as Memory: 13 out of 21680 0%
Number used as RAM: 8 Number used as RAM: 8
Number used as SRL: 3 Number used as SRL: 5
Slice Logic Distribution: Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 1274 Number of LUT Flip Flop pairs used: 1293
Number with an unused Flip Flop: 478 out of 1274 37% Number with an unused Flip Flop: 481 out of 1293 37%
Number with an unused LUT: 220 out of 1274 17% Number with an unused LUT: 216 out of 1293 16%
Number of fully used LUT-FF pairs: 576 out of 1274 45% Number of fully used LUT-FF pairs: 596 out of 1293 46%
Number of unique control sets: 32 Number of unique control sets: 32
IO Utilization: IO Utilization:
...@@ -954,9 +958,9 @@ Clock Information: ...@@ -954,9 +958,9 @@ Clock Information:
-----------------------------------+-----------------------------------------------+-------+ -----------------------------------+-----------------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load | Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+-----------------------------------------------+-------+ -----------------------------------+-----------------------------------------------+-------+
Si57x_ik | IBUFGDS+BUFG | 688 | Si57x_ik | IBUFGDS+BUFG | 702 |
VcTcXo_ik | BUFGP | 22 | VcTcXo_ik | BUFGP | 24 |
VmeSysClk_ik | BUFGP | 22 | VmeSysClk_ik | BUFGP | 24 |
i_Core/i_VmeInterface/stb_o | NONE(i_Core/i_VmeAccessMonostable/AsynchIn_ax)| 1 | i_Core/i_VmeInterface/stb_o | NONE(i_Core/i_VmeAccessMonostable/AsynchIn_ax)| 1 |
i_Core/Rst_rq | NONE(i_Core/i_ClearMonostable/AsynchIn_ax) | 1 | i_Core/Rst_rq | NONE(i_Core/i_ClearMonostable/AsynchIn_ax) | 1 |
SysAppClk_ik | BUFGP | 68 | SysAppClk_ik | BUFGP | 68 |
...@@ -983,7 +987,7 @@ All values displayed in nanoseconds (ns) ...@@ -983,7 +987,7 @@ All values displayed in nanoseconds (ns)
========================================================================= =========================================================================
Timing constraint: Default period analysis for Clock 'Si57x_ik' Timing constraint: Default period analysis for Clock 'Si57x_ik'
Clock period: 8.328ns (frequency: 120.083MHz) Clock period: 8.328ns (frequency: 120.083MHz)
Total number of paths / destination ports: 44586 / 1579 Total number of paths / destination ports: 45452 / 1617
------------------------------------------------------------------------- -------------------------------------------------------------------------
Delay: 8.328ns (Levels of Logic = 5) Delay: 8.328ns (Levels of Logic = 5)
Source: i_Core/i_VmeInterface/adr_o_21_1 (FF) Source: i_Core/i_VmeInterface/adr_o_21_1 (FF)
...@@ -1000,7 +1004,7 @@ Delay: 8.328ns (Levels of Logic = 5) ...@@ -1000,7 +1004,7 @@ Delay: 8.328ns (Levels of Logic = 5)
LUT4:I1->O 1 0.235 0.688 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1) LUT4:I1->O 1 0.235 0.688 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1)
LUT5:I3->O 5 0.250 0.715 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11 (i_Core/StbSpiMaster) LUT5:I3->O 5 0.250 0.715 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11 (i_Core/StbSpiMaster)
LUT6:I5->O 58 0.254 1.601 i_Core/i_AddressDecoderWB/Ack_o (i_Core/AckMaster) LUT6:I5->O 58 0.254 1.601 i_Core/i_AddressDecoderWB/Ack_o (i_Core/AckMaster)
LUT3:I2->O 32 0.254 1.291 i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_27_o2 (i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_27_o) LUT3:I2->O 32 0.254 1.291 i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_33_o2 (i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_33_o)
FDSE:CE 0.302 i_Core/i_VmeInterface/DataReg_0 FDSE:CE 0.302 i_Core/i_VmeInterface/DataReg_0
---------------------------------------- ----------------------------------------
Total 8.328ns (2.074ns logic, 6.254ns route) Total 8.328ns (2.074ns logic, 6.254ns route)
...@@ -1008,16 +1012,16 @@ Delay: 8.328ns (Levels of Logic = 5) ...@@ -1008,16 +1012,16 @@ Delay: 8.328ns (Levels of Logic = 5)
========================================================================= =========================================================================
Timing constraint: Default period analysis for Clock 'VcTcXo_ik' Timing constraint: Default period analysis for Clock 'VcTcXo_ik'
Clock period: 2.319ns (frequency: 431.248MHz) Clock period: 2.365ns (frequency: 422.770MHz)
Total number of paths / destination ports: 253 / 22 Total number of paths / destination ports: 300 / 24
------------------------------------------------------------------------- -------------------------------------------------------------------------
Delay: 2.319ns (Levels of Logic = 23) Delay: 2.365ns (Levels of Logic = 25)
Source: i_Core/VcTcXoDivider_c_0 (FF) Source: i_Core/VcTcXoDivider_c_0 (FF)
Destination: i_Core/VcTcXoDivider_c_21 (FF) Destination: i_Core/VcTcXoDivider_c_23 (FF)
Source Clock: VcTcXo_ik rising Source Clock: VcTcXo_ik rising
Destination Clock: VcTcXo_ik rising Destination Clock: VcTcXo_ik rising
Data Path: i_Core/VcTcXoDivider_c_0 to i_Core/VcTcXoDivider_c_21 Data Path: i_Core/VcTcXoDivider_c_0 to i_Core/VcTcXoDivider_c_23
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
...@@ -1043,25 +1047,27 @@ Delay: 2.319ns (Levels of Logic = 23) ...@@ -1043,25 +1047,27 @@ Delay: 2.319ns (Levels of Logic = 23)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<17> (i_Core/Mcount_VcTcXoDivider_c_cy<17>) MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<17> (i_Core/Mcount_VcTcXoDivider_c_cy<17>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<18> (i_Core/Mcount_VcTcXoDivider_c_cy<18>) MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<18> (i_Core/Mcount_VcTcXoDivider_c_cy<18>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<19> (i_Core/Mcount_VcTcXoDivider_c_cy<19>) MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<19> (i_Core/Mcount_VcTcXoDivider_c_cy<19>)
MUXCY:CI->O 0 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<20> (i_Core/Mcount_VcTcXoDivider_c_cy<20>) MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<20> (i_Core/Mcount_VcTcXoDivider_c_cy<20>)
XORCY:CI->O 1 0.206 0.000 i_Core/Mcount_VcTcXoDivider_c_xor<21> (i_Core/Result<21>1) MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<21> (i_Core/Mcount_VcTcXoDivider_c_cy<21>)
FD:D 0.074 i_Core/VcTcXoDivider_c_21 MUXCY:CI->O 0 0.023 0.000 i_Core/Mcount_VcTcXoDivider_c_cy<22> (i_Core/Mcount_VcTcXoDivider_c_cy<22>)
XORCY:CI->O 1 0.206 0.000 i_Core/Mcount_VcTcXoDivider_c_xor<23> (i_Core/Result<23>1)
FD:D 0.074 i_Core/VcTcXoDivider_c_23
---------------------------------------- ----------------------------------------
Total 2.319ns (1.740ns logic, 0.579ns route) Total 2.365ns (1.787ns logic, 0.579ns route)
(75.0% logic, 25.0% route) (75.5% logic, 24.5% route)
========================================================================= =========================================================================
Timing constraint: Default period analysis for Clock 'VmeSysClk_ik' Timing constraint: Default period analysis for Clock 'VmeSysClk_ik'
Clock period: 2.319ns (frequency: 431.248MHz) Clock period: 2.365ns (frequency: 422.770MHz)
Total number of paths / destination ports: 253 / 22 Total number of paths / destination ports: 300 / 24
------------------------------------------------------------------------- -------------------------------------------------------------------------
Delay: 2.319ns (Levels of Logic = 23) Delay: 2.365ns (Levels of Logic = 25)
Source: i_Core/VmeSysClkDivider_c_0 (FF) Source: i_Core/VmeSysClkDivider_c_0 (FF)
Destination: i_Core/VmeSysClkDivider_c_21 (FF) Destination: i_Core/VmeSysClkDivider_c_23 (FF)
Source Clock: VmeSysClk_ik rising Source Clock: VmeSysClk_ik rising
Destination Clock: VmeSysClk_ik rising Destination Clock: VmeSysClk_ik rising
Data Path: i_Core/VmeSysClkDivider_c_0 to i_Core/VmeSysClkDivider_c_21 Data Path: i_Core/VmeSysClkDivider_c_0 to i_Core/VmeSysClkDivider_c_23
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
...@@ -1087,12 +1093,14 @@ Delay: 2.319ns (Levels of Logic = 23) ...@@ -1087,12 +1093,14 @@ Delay: 2.319ns (Levels of Logic = 23)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<17> (i_Core/Mcount_VmeSysClkDivider_c_cy<17>) MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<17> (i_Core/Mcount_VmeSysClkDivider_c_cy<17>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<18> (i_Core/Mcount_VmeSysClkDivider_c_cy<18>) MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<18> (i_Core/Mcount_VmeSysClkDivider_c_cy<18>)
MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<19> (i_Core/Mcount_VmeSysClkDivider_c_cy<19>) MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<19> (i_Core/Mcount_VmeSysClkDivider_c_cy<19>)
MUXCY:CI->O 0 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<20> (i_Core/Mcount_VmeSysClkDivider_c_cy<20>) MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<20> (i_Core/Mcount_VmeSysClkDivider_c_cy<20>)
XORCY:CI->O 1 0.206 0.000 i_Core/Mcount_VmeSysClkDivider_c_xor<21> (i_Core/Result<21>) MUXCY:CI->O 1 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<21> (i_Core/Mcount_VmeSysClkDivider_c_cy<21>)
FD:D 0.074 i_Core/VmeSysClkDivider_c_21 MUXCY:CI->O 0 0.023 0.000 i_Core/Mcount_VmeSysClkDivider_c_cy<22> (i_Core/Mcount_VmeSysClkDivider_c_cy<22>)
XORCY:CI->O 1 0.206 0.000 i_Core/Mcount_VmeSysClkDivider_c_xor<23> (i_Core/Result<23>)
FD:D 0.074 i_Core/VmeSysClkDivider_c_23
---------------------------------------- ----------------------------------------
Total 2.319ns (1.740ns logic, 0.579ns route) Total 2.365ns (1.787ns logic, 0.579ns route)
(75.0% logic, 25.0% route) (75.5% logic, 24.5% route)
========================================================================= =========================================================================
Timing constraint: Default period analysis for Clock 'i_Core/i_VmeInterface/stb_o' Timing constraint: Default period analysis for Clock 'i_Core/i_VmeInterface/stb_o'
...@@ -1176,7 +1184,7 @@ Offset: 8.362ns (Levels of Logic = 6) ...@@ -1176,7 +1184,7 @@ Offset: 8.362ns (Levels of Logic = 6)
IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF) IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF)
LUT6:I1->O 5 0.254 0.943 i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error) LUT6:I1->O 5 0.254 0.943 i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error)
LUT4:I1->O 2 0.235 0.725 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o311 (N5) LUT4:I1->O 2 0.235 0.725 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o311 (N5)
LUT6:I4->O 1 0.250 0.808 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o87_SW0 (N259) LUT6:I4->O 1 0.250 0.808 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o87_SW0 (N263)
LUT6:I3->O 12 0.235 0.909 i_Core/i_VmeInterface/selected (i_Core/i_VmeInterface/selected) LUT6:I3->O 12 0.235 0.909 i_Core/i_VmeInterface/selected (i_Core/i_VmeInterface/selected)
LUT5:I4->O 24 0.254 1.172 i_Core/i_VmeInterface/_n0350_inv1 (i_Core/i_VmeInterface/_n0350_inv) LUT5:I4->O 24 0.254 1.172 i_Core/i_VmeInterface/_n0350_inv1 (i_Core/i_VmeInterface/_n0350_inv)
FDRE:CE 0.302 i_Core/i_VmeInterface/adr_o_0 FDRE:CE 0.302 i_Core/i_VmeInterface/adr_o_0
...@@ -1228,15 +1236,15 @@ Timing constraint: Default OFFSET OUT AFTER for Clock 'VmeSysClk_ik' ...@@ -1228,15 +1236,15 @@ Timing constraint: Default OFFSET OUT AFTER for Clock 'VmeSysClk_ik'
Total number of paths / destination ports: 2 / 2 Total number of paths / destination ports: 2 / 2
------------------------------------------------------------------------- -------------------------------------------------------------------------
Offset: 4.828ns (Levels of Logic = 2) Offset: 4.828ns (Levels of Logic = 2)
Source: i_Core/VmeSysClkDivider_c_21 (FF) Source: i_Core/VmeSysClkDivider_c_23 (FF)
Destination: FpLed_onb8<7> (PAD) Destination: FpLed_onb8<7> (PAD)
Source Clock: VmeSysClk_ik rising Source Clock: VmeSysClk_ik rising
Data Path: i_Core/VmeSysClkDivider_c_21 to FpLed_onb8<7> Data Path: i_Core/VmeSysClkDivider_c_23 to FpLed_onb8<7>
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
FD:C->Q 3 0.525 0.759 i_Core/VmeSysClkDivider_c_21 (i_Core/VmeSysClkDivider_c_21) FD:C->Q 3 0.525 0.759 i_Core/VmeSysClkDivider_c_23 (i_Core/VmeSysClkDivider_c_23)
LUT5:I3->O 1 0.250 0.579 i_Core/Mmux_a_FpLed711 (i_Core/a_FpLed7) LUT5:I3->O 1 0.250 0.579 i_Core/Mmux_a_FpLed711 (i_Core/a_FpLed7)
OBUFT:T->O 2.715 FpLed_onb8_7_OBUFT (FpLed_onb8<7>) OBUFT:T->O 2.715 FpLed_onb8_7_OBUFT (FpLed_onb8<7>)
---------------------------------------- ----------------------------------------
...@@ -1248,15 +1256,15 @@ Timing constraint: Default OFFSET OUT AFTER for Clock 'VcTcXo_ik' ...@@ -1248,15 +1256,15 @@ Timing constraint: Default OFFSET OUT AFTER for Clock 'VcTcXo_ik'
Total number of paths / destination ports: 2 / 2 Total number of paths / destination ports: 2 / 2
------------------------------------------------------------------------- -------------------------------------------------------------------------
Offset: 4.724ns (Levels of Logic = 2) Offset: 4.724ns (Levels of Logic = 2)
Source: i_Core/VcTcXoDivider_c_21 (FF) Source: i_Core/VcTcXoDivider_c_23 (FF)
Destination: FpLed_onb8<7> (PAD) Destination: FpLed_onb8<7> (PAD)
Source Clock: VcTcXo_ik rising Source Clock: VcTcXo_ik rising
Data Path: i_Core/VcTcXoDivider_c_21 to FpLed_onb8<7> Data Path: i_Core/VcTcXoDivider_c_23 to FpLed_onb8<7>
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
FD:C->Q 3 0.525 0.651 i_Core/VcTcXoDivider_c_21 (i_Core/VcTcXoDivider_c_21) FD:C->Q 3 0.525 0.651 i_Core/VcTcXoDivider_c_23 (i_Core/VcTcXoDivider_c_23)
LUT5:I4->O 1 0.254 0.579 i_Core/Mmux_a_FpLed711 (i_Core/a_FpLed7) LUT5:I4->O 1 0.254 0.579 i_Core/Mmux_a_FpLed711 (i_Core/a_FpLed7)
OBUFT:T->O 2.715 FpLed_onb8_7_OBUFT (FpLed_onb8<7>) OBUFT:T->O 2.715 FpLed_onb8_7_OBUFT (FpLed_onb8<7>)
---------------------------------------- ----------------------------------------
...@@ -1277,7 +1285,7 @@ Delay: 6.896ns (Levels of Logic = 4) ...@@ -1277,7 +1285,7 @@ Delay: 6.896ns (Levels of Logic = 4)
---------------------------------------- ------------ ---------------------------------------- ------------
IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF) IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF)
LUT6:I1->O 5 0.254 0.823 i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error) LUT6:I1->O 5 0.254 0.823 i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error)
LUT2:I0->O 1 0.250 0.579 i_Core/VmeGa_ib5n[4]_UseGa_i_OR_1_o_inv1 (i_Core/VmeGa_ib5n[4]_UseGa_i_OR_1_o_inv) LUT2:I0->O 1 0.250 0.579 i_Core/VmeGa_ib5n[4]_UseGa_i_OR_7_o_inv1 (i_Core/VmeGa_ib5n[4]_UseGa_i_OR_7_o_inv)
OBUFT:T->O 2.715 FpLed_onb8_2_OBUFT (FpLed_onb8<2>) OBUFT:T->O 2.715 FpLed_onb8_2_OBUFT (FpLed_onb8<2>)
---------------------------------------- ----------------------------------------
Total 6.896ns (4.447ns logic, 2.449ns route) Total 6.896ns (4.447ns logic, 2.449ns route)
...@@ -1295,8 +1303,8 @@ Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ...@@ -1295,8 +1303,8 @@ Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------------------+---------+---------+---------+---------+ ---------------------------+---------+---------+---------+---------+
Si57x_ik | 8.328| | | | Si57x_ik | 8.328| | | |
SysAppClk_ik | 1.178| | | | SysAppClk_ik | 1.178| | | |
i_Core/Rst_rq | 1.215| | | | i_Core/Rst_rq | 1.141| | | |
i_Core/i_VmeInterface/stb_o| 1.215| | | | i_Core/i_VmeInterface/stb_o| 1.141| | | |
---------------------------+---------+---------+---------+---------+ ---------------------------+---------+---------+---------+---------+
Clock to Setup on destination clock SysAppClk_ik Clock to Setup on destination clock SysAppClk_ik
...@@ -1313,7 +1321,7 @@ Clock to Setup on destination clock VcTcXo_ik ...@@ -1313,7 +1321,7 @@ Clock to Setup on destination clock VcTcXo_ik
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+ ---------------+---------+---------+---------+---------+
VcTcXo_ik | 2.319| | | | VcTcXo_ik | 2.365| | | |
---------------+---------+---------+---------+---------+ ---------------+---------+---------+---------+---------+
Clock to Setup on destination clock VmeSysClk_ik Clock to Setup on destination clock VmeSysClk_ik
...@@ -1321,7 +1329,7 @@ Clock to Setup on destination clock VmeSysClk_ik ...@@ -1321,7 +1329,7 @@ Clock to Setup on destination clock VmeSysClk_ik
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+ ---------------+---------+---------+---------+---------+
VmeSysClk_ik | 2.319| | | | VmeSysClk_ik | 2.365| | | |
---------------+---------+---------+---------+---------+ ---------------+---------+---------+---------+---------+
Clock to Setup on destination clock i_Core/Rst_rq Clock to Setup on destination clock i_Core/Rst_rq
...@@ -1343,12 +1351,12 @@ i_Core/i_VmeInterface/stb_o| 2.049| | | | ...@@ -1343,12 +1351,12 @@ i_Core/i_VmeInterface/stb_o| 2.049| | | |
========================================================================= =========================================================================
Total REAL time to Xst completion: 19.00 secs Total REAL time to Xst completion: 18.00 secs
Total CPU time to Xst completion: 19.43 secs Total CPU time to Xst completion: 18.24 secs
--> -->
Total memory usage is 279568 kilobytes Total memory usage is 280720 kilobytes
Number of errors : 0 ( 0 filtered) Number of errors : 0 ( 0 filtered)
Number of warnings : 126 ( 0 filtered) Number of warnings : 126 ( 0 filtered)
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.twr
View file @ 265c6bd0
...@@ -26,19 +26,19 @@ INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on ...@@ -26,19 +26,19 @@ INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
================================================================================ ================================================================================
Timing constraint: TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%; Timing constraint: TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%;
44725 paths analyzed, 2978 endpoints analyzed, 0 failing endpoints 45589 paths analyzed, 3055 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 7.898ns. Minimum period is 7.904ns.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_6 (SLICE_X59Y78.C4), 310 paths Paths for end point i_Core/i_SpiMasterWB/Config2_qb32_2 (SLICE_X67Y82.CE), 48 paths
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (setup path): 0.435ns (requirement - (data path - clock path skew + uncertainty)) Slack (setup path): 0.429ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_SpiMasterWB/Config1_qb32_0 (FF) Source: i_Core/i_VmeInterface/adr_o_11 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_6 (FF) Destination: i_Core/i_SpiMasterWB/Config2_qb32_2 (FF)
Requirement: 8.333ns Requirement: 8.333ns
Data Path Delay: 8.022ns (Levels of Logic = 5) Data Path Delay: 8.021ns (Levels of Logic = 5)
Clock Path Skew: 0.159ns (0.905 - 0.746) Clock Path Skew: 0.152ns (1.046 - 0.894)
Source Clock: Si57x_BUFG rising at 0.000ns Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns
...@@ -49,40 +49,41 @@ Slack (setup path): 0.435ns (requirement - (data path - clock path skew + un ...@@ -49,40 +49,41 @@ Slack (setup path): 0.435ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_SpiMasterWB/Config1_qb32_0 to i_Core/i_SpiMasterWB/ShiftIn_qb32_6 Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_11 to i_Core/i_SpiMasterWB/Config2_qb32_2
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X69Y74.AQ Tcko 0.430 i_Core/i_SpiMasterWB/Config1_qb32<19> SLICE_X77Y100.DQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<11>
i_Core/i_SpiMasterWB/Config1_qb32_0 i_Core/i_VmeInterface/adr_o_11
SLICE_X67Y74.A4 net (fanout=2) 1.775 i_Core/i_SpiMasterWB/Config1_qb32<0> SLICE_X75Y100.B2 net (fanout=4) 1.196 i_Core/i_VmeInterface/adr_o<11>
SLICE_X67Y74.A Tilo 0.259 i_Core/i_SpiMasterWB/Config1_qb32<2> SLICE_X75Y100.B Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o122 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o12
SLICE_X70Y69.C5 net (fanout=3) 1.434 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o121 SLICE_X75Y100.A5 net (fanout=4) 0.231 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o11
SLICE_X70Y69.CMUX Topcc 0.441 N261 SLICE_X75Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_lut i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_cy SLICE_X75Y93.B5 net (fanout=1) 0.883 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1
SLICE_X70Y71.A6 net (fanout=1) 0.526 N261 SLICE_X75Y93.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
SLICE_X70Y71.A Tilo 0.235 N299 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
i_Core/i_SpiMasterWB/_n0817_inv_SW0 SLICE_X67Y81.C6 net (fanout=5) 1.915 i_Core/StbSpiMaster
SLICE_X60Y77.B2 net (fanout=1) 1.658 N84 SLICE_X67Y81.C Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<31>
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31> i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o1
i_Core/i_SpiMasterWB/_n0817_inv SLICE_X67Y82.A5 net (fanout=3) 0.420 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o
SLICE_X59Y78.C4 net (fanout=32) 0.637 i_Core/i_SpiMasterWB/_n0817_inv SLICE_X67Y82.A Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<30>
SLICE_X59Y78.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<6> i_Core/i_SpiMasterWB/_n0745_inv
i_Core/i_SpiMasterWB/ShiftIn_qb32_6_rstpot SLICE_X67Y82.CE net (fanout=9) 1.243 i_Core/i_SpiMasterWB/_n0745_inv
i_Core/i_SpiMasterWB/ShiftIn_qb32_6 SLICE_X67Y82.CLK Tceck 0.408 i_Core/i_SpiMasterWB/Config2_qb32<30>
i_Core/i_SpiMasterWB/Config2_qb32_2
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 8.022ns (1.992ns logic, 6.030ns route) Total 8.021ns (2.133ns logic, 5.888ns route)
(24.8% logic, 75.2% route) (26.6% logic, 73.4% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (setup path): 0.738ns (requirement - (data path - clock path skew + uncertainty)) Slack (setup path): 0.561ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_SpiMasterWB/TxCounter_cb12_5 (FF) Source: i_Core/i_VmeInterface/adr_o_9 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_6 (FF) Destination: i_Core/i_SpiMasterWB/Config2_qb32_2 (FF)
Requirement: 8.333ns Requirement: 8.333ns
Data Path Delay: 7.553ns (Levels of Logic = 5) Data Path Delay: 7.889ns (Levels of Logic = 5)
Clock Path Skew: -0.007ns (0.166 - 0.173) Clock Path Skew: 0.152ns (1.046 - 0.894)
Source Clock: Si57x_BUFG rising at 0.000ns Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns
...@@ -93,40 +94,41 @@ Slack (setup path): 0.738ns (requirement - (data path - clock path skew + un ...@@ -93,40 +94,41 @@ Slack (setup path): 0.738ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_SpiMasterWB/TxCounter_cb12_5 to i_Core/i_SpiMasterWB/ShiftIn_qb32_6 Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_9 to i_Core/i_SpiMasterWB/Config2_qb32_2
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X58Y76.DQ Tcko 0.476 i_Core/i_SpiMasterWB/TxCounter_cb12<5> SLICE_X77Y100.BQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<11>
i_Core/i_SpiMasterWB/TxCounter_cb12_5 i_Core/i_VmeInterface/adr_o_9
SLICE_X66Y74.B6 net (fanout=3) 1.068 i_Core/i_SpiMasterWB/TxCounter_cb12<5> SLICE_X75Y100.C2 net (fanout=4) 0.752 i_Core/i_VmeInterface/adr_o<9>
SLICE_X66Y74.B Tilo 0.235 i_Core/i_SpiMasterWB/Config1_qb32<6> SLICE_X75Y100.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o124 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o11
SLICE_X70Y69.C4 net (fanout=3) 1.650 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o123 SLICE_X75Y100.A2 net (fanout=4) 0.543 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
SLICE_X70Y69.CMUX Topcc 0.441 N261 SLICE_X75Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_lut i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_cy SLICE_X75Y93.B5 net (fanout=1) 0.883 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1
SLICE_X70Y71.A6 net (fanout=1) 0.526 N261 SLICE_X75Y93.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
SLICE_X70Y71.A Tilo 0.235 N299 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
i_Core/i_SpiMasterWB/_n0817_inv_SW0 SLICE_X67Y81.C6 net (fanout=5) 1.915 i_Core/StbSpiMaster
SLICE_X60Y77.B2 net (fanout=1) 1.658 N84 SLICE_X67Y81.C Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<31>
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31> i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o1
i_Core/i_SpiMasterWB/_n0817_inv SLICE_X67Y82.A5 net (fanout=3) 0.420 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o
SLICE_X59Y78.C4 net (fanout=32) 0.637 i_Core/i_SpiMasterWB/_n0817_inv SLICE_X67Y82.A Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<30>
SLICE_X59Y78.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<6> i_Core/i_SpiMasterWB/_n0745_inv
i_Core/i_SpiMasterWB/ShiftIn_qb32_6_rstpot SLICE_X67Y82.CE net (fanout=9) 1.243 i_Core/i_SpiMasterWB/_n0745_inv
i_Core/i_SpiMasterWB/ShiftIn_qb32_6 SLICE_X67Y82.CLK Tceck 0.408 i_Core/i_SpiMasterWB/Config2_qb32<30>
i_Core/i_SpiMasterWB/Config2_qb32_2
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 7.553ns (2.014ns logic, 5.539ns route) Total 7.889ns (2.133ns logic, 5.756ns route)
(26.7% logic, 73.3% route) (27.0% logic, 73.0% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (setup path): 0.795ns (requirement - (data path - clock path skew + uncertainty)) Slack (setup path): 0.566ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_13 (FF) Source: i_Core/i_VmeInterface/adr_o_10 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_6 (FF) Destination: i_Core/i_SpiMasterWB/Config2_qb32_2 (FF)
Requirement: 8.333ns Requirement: 8.333ns
Data Path Delay: 7.598ns (Levels of Logic = 6) Data Path Delay: 7.884ns (Levels of Logic = 5)
Clock Path Skew: 0.095ns (0.994 - 0.899) Clock Path Skew: 0.152ns (1.046 - 0.894)
Source Clock: Si57x_BUFG rising at 0.000ns Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns
...@@ -137,45 +139,44 @@ Slack (setup path): 0.795ns (requirement - (data path - clock path skew + un ...@@ -137,45 +139,44 @@ Slack (setup path): 0.795ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_13 to i_Core/i_SpiMasterWB/ShiftIn_qb32_6 Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_10 to i_Core/i_SpiMasterWB/Config2_qb32_2
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X79Y97.BQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<15> SLICE_X77Y100.CQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<11>
i_Core/i_VmeInterface/adr_o_13 i_Core/i_VmeInterface/adr_o_10
SLICE_X81Y97.B1 net (fanout=4) 0.741 i_Core/i_VmeInterface/adr_o<13> SLICE_X75Y100.C4 net (fanout=4) 0.747 i_Core/i_VmeInterface/adr_o<10>
SLICE_X81Y97.B Tilo 0.259 i_Core/i_VmeInterface/adr_o<10> SLICE_X75Y100.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o12 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o11
SLICE_X81Y97.A6 net (fanout=4) 0.554 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o11 SLICE_X75Y100.A2 net (fanout=4) 0.543 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
SLICE_X81Y97.A Tilo 0.259 i_Core/i_VmeInterface/adr_o<10> SLICE_X75Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1
SLICE_X75Y88.B3 net (fanout=1) 1.560 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1 SLICE_X75Y93.B5 net (fanout=1) 0.883 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1
SLICE_X75Y88.B Tilo 0.259 i_Core/i_VmeInterface/ack_d SLICE_X75Y93.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X60Y77.C6 net (fanout=5) 1.716 i_Core/StbSpiMaster SLICE_X67Y81.C6 net (fanout=5) 1.915 i_Core/StbSpiMaster
SLICE_X60Y77.C Tilo 0.255 i_Core/i_SpiMasterWB/ShiftIn_qb32<31> SLICE_X67Y81.C Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<31>
i_Core/i_SpiMasterWB/_n0649_inv11_1 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o1
SLICE_X60Y77.B4 net (fanout=1) 0.301 i_Core/i_SpiMasterWB/_n0649_inv11 SLICE_X67Y82.A5 net (fanout=3) 0.420 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31> SLICE_X67Y82.A Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<30>
i_Core/i_SpiMasterWB/_n0817_inv i_Core/i_SpiMasterWB/_n0745_inv
SLICE_X59Y78.C4 net (fanout=32) 0.637 i_Core/i_SpiMasterWB/_n0817_inv SLICE_X67Y82.CE net (fanout=9) 1.243 i_Core/i_SpiMasterWB/_n0745_inv
SLICE_X59Y78.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<6> SLICE_X67Y82.CLK Tceck 0.408 i_Core/i_SpiMasterWB/Config2_qb32<30>
i_Core/i_SpiMasterWB/ShiftIn_qb32_6_rstpot i_Core/i_SpiMasterWB/Config2_qb32_2
i_Core/i_SpiMasterWB/ShiftIn_qb32_6
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 7.598ns (2.089ns logic, 5.509ns route) Total 7.884ns (2.133ns logic, 5.751ns route)
(27.5% logic, 72.5% route) (27.1% logic, 72.9% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_16 (SLICE_X63Y76.C6), 310 paths Paths for end point i_Core/i_SpiMasterWB/Config2_qb32_17 (SLICE_X67Y82.CE), 48 paths
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (setup path): 0.442ns (requirement - (data path - clock path skew + uncertainty)) Slack (setup path): 0.447ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_SpiMasterWB/Config1_qb32_0 (FF) Source: i_Core/i_VmeInterface/adr_o_11 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_16 (FF) Destination: i_Core/i_SpiMasterWB/Config2_qb32_17 (FF)
Requirement: 8.333ns Requirement: 8.333ns
Data Path Delay: 8.012ns (Levels of Logic = 5) Data Path Delay: 8.003ns (Levels of Logic = 5)
Clock Path Skew: 0.156ns (0.902 - 0.746) Clock Path Skew: 0.152ns (1.046 - 0.894)
Source Clock: Si57x_BUFG rising at 0.000ns Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns
...@@ -186,40 +187,41 @@ Slack (setup path): 0.442ns (requirement - (data path - clock path skew + un ...@@ -186,40 +187,41 @@ Slack (setup path): 0.442ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_SpiMasterWB/Config1_qb32_0 to i_Core/i_SpiMasterWB/ShiftIn_qb32_16 Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_11 to i_Core/i_SpiMasterWB/Config2_qb32_17
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X69Y74.AQ Tcko 0.430 i_Core/i_SpiMasterWB/Config1_qb32<19> SLICE_X77Y100.DQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<11>
i_Core/i_SpiMasterWB/Config1_qb32_0 i_Core/i_VmeInterface/adr_o_11
SLICE_X67Y74.A4 net (fanout=2) 1.775 i_Core/i_SpiMasterWB/Config1_qb32<0> SLICE_X75Y100.B2 net (fanout=4) 1.196 i_Core/i_VmeInterface/adr_o<11>
SLICE_X67Y74.A Tilo 0.259 i_Core/i_SpiMasterWB/Config1_qb32<2> SLICE_X75Y100.B Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o122 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o12
SLICE_X70Y69.C5 net (fanout=3) 1.434 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o121 SLICE_X75Y100.A5 net (fanout=4) 0.231 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o11
SLICE_X70Y69.CMUX Topcc 0.441 N261 SLICE_X75Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_lut i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_cy SLICE_X75Y93.B5 net (fanout=1) 0.883 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1
SLICE_X70Y71.A6 net (fanout=1) 0.526 N261 SLICE_X75Y93.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
SLICE_X70Y71.A Tilo 0.235 N299 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
i_Core/i_SpiMasterWB/_n0817_inv_SW0 SLICE_X67Y81.C6 net (fanout=5) 1.915 i_Core/StbSpiMaster
SLICE_X60Y77.B2 net (fanout=1) 1.658 N84 SLICE_X67Y81.C Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<31>
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31> i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o1
i_Core/i_SpiMasterWB/_n0817_inv SLICE_X67Y82.A5 net (fanout=3) 0.420 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o
SLICE_X63Y76.C6 net (fanout=32) 0.627 i_Core/i_SpiMasterWB/_n0817_inv SLICE_X67Y82.A Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<30>
SLICE_X63Y76.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<16> i_Core/i_SpiMasterWB/_n0745_inv
i_Core/i_SpiMasterWB/ShiftIn_qb32_16_rstpot SLICE_X67Y82.CE net (fanout=9) 1.243 i_Core/i_SpiMasterWB/_n0745_inv
i_Core/i_SpiMasterWB/ShiftIn_qb32_16 SLICE_X67Y82.CLK Tceck 0.390 i_Core/i_SpiMasterWB/Config2_qb32<30>
i_Core/i_SpiMasterWB/Config2_qb32_17
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 8.012ns (1.992ns logic, 6.020ns route) Total 8.003ns (2.115ns logic, 5.888ns route)
(24.9% logic, 75.1% route) (26.4% logic, 73.6% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (setup path): 0.740ns (requirement - (data path - clock path skew + uncertainty)) Slack (setup path): 0.579ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_SpiMasterWB/TxCounter_cb12_5 (FF) Source: i_Core/i_VmeInterface/adr_o_9 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_16 (FF) Destination: i_Core/i_SpiMasterWB/Config2_qb32_17 (FF)
Requirement: 8.333ns Requirement: 8.333ns
Data Path Delay: 7.543ns (Levels of Logic = 5) Data Path Delay: 7.871ns (Levels of Logic = 5)
Clock Path Skew: -0.015ns (0.254 - 0.269) Clock Path Skew: 0.152ns (1.046 - 0.894)
Source Clock: Si57x_BUFG rising at 0.000ns Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns
...@@ -230,40 +232,41 @@ Slack (setup path): 0.740ns (requirement - (data path - clock path skew + un ...@@ -230,40 +232,41 @@ Slack (setup path): 0.740ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_SpiMasterWB/TxCounter_cb12_5 to i_Core/i_SpiMasterWB/ShiftIn_qb32_16 Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_9 to i_Core/i_SpiMasterWB/Config2_qb32_17
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X58Y76.DQ Tcko 0.476 i_Core/i_SpiMasterWB/TxCounter_cb12<5> SLICE_X77Y100.BQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<11>
i_Core/i_SpiMasterWB/TxCounter_cb12_5 i_Core/i_VmeInterface/adr_o_9
SLICE_X66Y74.B6 net (fanout=3) 1.068 i_Core/i_SpiMasterWB/TxCounter_cb12<5> SLICE_X75Y100.C2 net (fanout=4) 0.752 i_Core/i_VmeInterface/adr_o<9>
SLICE_X66Y74.B Tilo 0.235 i_Core/i_SpiMasterWB/Config1_qb32<6> SLICE_X75Y100.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o124 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o11
SLICE_X70Y69.C4 net (fanout=3) 1.650 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o123 SLICE_X75Y100.A2 net (fanout=4) 0.543 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
SLICE_X70Y69.CMUX Topcc 0.441 N261 SLICE_X75Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_lut i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_cy SLICE_X75Y93.B5 net (fanout=1) 0.883 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1
SLICE_X70Y71.A6 net (fanout=1) 0.526 N261 SLICE_X75Y93.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
SLICE_X70Y71.A Tilo 0.235 N299 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
i_Core/i_SpiMasterWB/_n0817_inv_SW0 SLICE_X67Y81.C6 net (fanout=5) 1.915 i_Core/StbSpiMaster
SLICE_X60Y77.B2 net (fanout=1) 1.658 N84 SLICE_X67Y81.C Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<31>
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31> i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o1
i_Core/i_SpiMasterWB/_n0817_inv SLICE_X67Y82.A5 net (fanout=3) 0.420 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o
SLICE_X63Y76.C6 net (fanout=32) 0.627 i_Core/i_SpiMasterWB/_n0817_inv SLICE_X67Y82.A Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<30>
SLICE_X63Y76.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<16> i_Core/i_SpiMasterWB/_n0745_inv
i_Core/i_SpiMasterWB/ShiftIn_qb32_16_rstpot SLICE_X67Y82.CE net (fanout=9) 1.243 i_Core/i_SpiMasterWB/_n0745_inv
i_Core/i_SpiMasterWB/ShiftIn_qb32_16 SLICE_X67Y82.CLK Tceck 0.390 i_Core/i_SpiMasterWB/Config2_qb32<30>
i_Core/i_SpiMasterWB/Config2_qb32_17
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 7.543ns (2.014ns logic, 5.529ns route) Total 7.871ns (2.115ns logic, 5.756ns route)
(26.7% logic, 73.3% route) (26.9% logic, 73.1% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (setup path): 0.802ns (requirement - (data path - clock path skew + uncertainty)) Slack (setup path): 0.584ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_13 (FF) Source: i_Core/i_VmeInterface/adr_o_10 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_16 (FF) Destination: i_Core/i_SpiMasterWB/Config2_qb32_17 (FF)
Requirement: 8.333ns Requirement: 8.333ns
Data Path Delay: 7.588ns (Levels of Logic = 6) Data Path Delay: 7.866ns (Levels of Logic = 5)
Clock Path Skew: 0.092ns (0.991 - 0.899) Clock Path Skew: 0.152ns (1.046 - 0.894)
Source Clock: Si57x_BUFG rising at 0.000ns Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns
...@@ -274,45 +277,44 @@ Slack (setup path): 0.802ns (requirement - (data path - clock path skew + un ...@@ -274,45 +277,44 @@ Slack (setup path): 0.802ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_13 to i_Core/i_SpiMasterWB/ShiftIn_qb32_16 Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_10 to i_Core/i_SpiMasterWB/Config2_qb32_17
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X79Y97.BQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<15> SLICE_X77Y100.CQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<11>
i_Core/i_VmeInterface/adr_o_13 i_Core/i_VmeInterface/adr_o_10
SLICE_X81Y97.B1 net (fanout=4) 0.741 i_Core/i_VmeInterface/adr_o<13> SLICE_X75Y100.C4 net (fanout=4) 0.747 i_Core/i_VmeInterface/adr_o<10>
SLICE_X81Y97.B Tilo 0.259 i_Core/i_VmeInterface/adr_o<10> SLICE_X75Y100.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o12 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o11
SLICE_X81Y97.A6 net (fanout=4) 0.554 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o11 SLICE_X75Y100.A2 net (fanout=4) 0.543 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
SLICE_X81Y97.A Tilo 0.259 i_Core/i_VmeInterface/adr_o<10> SLICE_X75Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1
SLICE_X75Y88.B3 net (fanout=1) 1.560 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1 SLICE_X75Y93.B5 net (fanout=1) 0.883 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1
SLICE_X75Y88.B Tilo 0.259 i_Core/i_VmeInterface/ack_d SLICE_X75Y93.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X60Y77.C6 net (fanout=5) 1.716 i_Core/StbSpiMaster SLICE_X67Y81.C6 net (fanout=5) 1.915 i_Core/StbSpiMaster
SLICE_X60Y77.C Tilo 0.255 i_Core/i_SpiMasterWB/ShiftIn_qb32<31> SLICE_X67Y81.C Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<31>
i_Core/i_SpiMasterWB/_n0649_inv11_1 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o1
SLICE_X60Y77.B4 net (fanout=1) 0.301 i_Core/i_SpiMasterWB/_n0649_inv11 SLICE_X67Y82.A5 net (fanout=3) 0.420 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31> SLICE_X67Y82.A Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<30>
i_Core/i_SpiMasterWB/_n0817_inv i_Core/i_SpiMasterWB/_n0745_inv
SLICE_X63Y76.C6 net (fanout=32) 0.627 i_Core/i_SpiMasterWB/_n0817_inv SLICE_X67Y82.CE net (fanout=9) 1.243 i_Core/i_SpiMasterWB/_n0745_inv
SLICE_X63Y76.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<16> SLICE_X67Y82.CLK Tceck 0.390 i_Core/i_SpiMasterWB/Config2_qb32<30>
i_Core/i_SpiMasterWB/ShiftIn_qb32_16_rstpot i_Core/i_SpiMasterWB/Config2_qb32_17
i_Core/i_SpiMasterWB/ShiftIn_qb32_16
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 7.588ns (2.089ns logic, 5.499ns route) Total 7.866ns (2.115ns logic, 5.751ns route)
(27.5% logic, 72.5% route) (26.9% logic, 73.1% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_22 (SLICE_X62Y76.C6), 310 paths Paths for end point i_Core/i_SpiMasterWB/Config2_qb32_30 (SLICE_X67Y82.CE), 48 paths
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (setup path): 0.453ns (requirement - (data path - clock path skew + uncertainty)) Slack (setup path): 0.455ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_SpiMasterWB/Config1_qb32_0 (FF) Source: i_Core/i_VmeInterface/adr_o_11 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_22 (FF) Destination: i_Core/i_SpiMasterWB/Config2_qb32_30 (FF)
Requirement: 8.333ns Requirement: 8.333ns
Data Path Delay: 8.001ns (Levels of Logic = 5) Data Path Delay: 7.995ns (Levels of Logic = 5)
Clock Path Skew: 0.156ns (0.902 - 0.746) Clock Path Skew: 0.152ns (1.046 - 0.894)
Source Clock: Si57x_BUFG rising at 0.000ns Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns
...@@ -323,40 +325,41 @@ Slack (setup path): 0.453ns (requirement - (data path - clock path skew + un ...@@ -323,40 +325,41 @@ Slack (setup path): 0.453ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_SpiMasterWB/Config1_qb32_0 to i_Core/i_SpiMasterWB/ShiftIn_qb32_22 Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_11 to i_Core/i_SpiMasterWB/Config2_qb32_30
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X69Y74.AQ Tcko 0.430 i_Core/i_SpiMasterWB/Config1_qb32<19> SLICE_X77Y100.DQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<11>
i_Core/i_SpiMasterWB/Config1_qb32_0 i_Core/i_VmeInterface/adr_o_11
SLICE_X67Y74.A4 net (fanout=2) 1.775 i_Core/i_SpiMasterWB/Config1_qb32<0> SLICE_X75Y100.B2 net (fanout=4) 1.196 i_Core/i_VmeInterface/adr_o<11>
SLICE_X67Y74.A Tilo 0.259 i_Core/i_SpiMasterWB/Config1_qb32<2> SLICE_X75Y100.B Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o122 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o12
SLICE_X70Y69.C5 net (fanout=3) 1.434 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o121 SLICE_X75Y100.A5 net (fanout=4) 0.231 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o11
SLICE_X70Y69.CMUX Topcc 0.441 N261 SLICE_X75Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_lut i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_cy SLICE_X75Y93.B5 net (fanout=1) 0.883 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1
SLICE_X70Y71.A6 net (fanout=1) 0.526 N261 SLICE_X75Y93.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
SLICE_X70Y71.A Tilo 0.235 N299 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
i_Core/i_SpiMasterWB/_n0817_inv_SW0 SLICE_X67Y81.C6 net (fanout=5) 1.915 i_Core/StbSpiMaster
SLICE_X60Y77.B2 net (fanout=1) 1.658 N84 SLICE_X67Y81.C Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<31>
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31> i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o1
i_Core/i_SpiMasterWB/_n0817_inv SLICE_X67Y82.A5 net (fanout=3) 0.420 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o
SLICE_X62Y76.C6 net (fanout=32) 0.640 i_Core/i_SpiMasterWB/_n0817_inv SLICE_X67Y82.A Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<30>
SLICE_X62Y76.CLK Tas 0.349 i_Core/i_SpiMasterWB/ShiftIn_qb32<23> i_Core/i_SpiMasterWB/_n0745_inv
i_Core/i_SpiMasterWB/ShiftIn_qb32_22_rstpot SLICE_X67Y82.CE net (fanout=9) 1.243 i_Core/i_SpiMasterWB/_n0745_inv
i_Core/i_SpiMasterWB/ShiftIn_qb32_22 SLICE_X67Y82.CLK Tceck 0.382 i_Core/i_SpiMasterWB/Config2_qb32<30>
i_Core/i_SpiMasterWB/Config2_qb32_30
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 8.001ns (1.968ns logic, 6.033ns route) Total 7.995ns (2.107ns logic, 5.888ns route)
(24.6% logic, 75.4% route) (26.4% logic, 73.6% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (setup path): 0.751ns (requirement - (data path - clock path skew + uncertainty)) Slack (setup path): 0.587ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_SpiMasterWB/TxCounter_cb12_5 (FF) Source: i_Core/i_VmeInterface/adr_o_9 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_22 (FF) Destination: i_Core/i_SpiMasterWB/Config2_qb32_30 (FF)
Requirement: 8.333ns Requirement: 8.333ns
Data Path Delay: 7.532ns (Levels of Logic = 5) Data Path Delay: 7.863ns (Levels of Logic = 5)
Clock Path Skew: -0.015ns (0.254 - 0.269) Clock Path Skew: 0.152ns (1.046 - 0.894)
Source Clock: Si57x_BUFG rising at 0.000ns Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns
...@@ -367,40 +370,41 @@ Slack (setup path): 0.751ns (requirement - (data path - clock path skew + un ...@@ -367,40 +370,41 @@ Slack (setup path): 0.751ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_SpiMasterWB/TxCounter_cb12_5 to i_Core/i_SpiMasterWB/ShiftIn_qb32_22 Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_9 to i_Core/i_SpiMasterWB/Config2_qb32_30
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X58Y76.DQ Tcko 0.476 i_Core/i_SpiMasterWB/TxCounter_cb12<5> SLICE_X77Y100.BQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<11>
i_Core/i_SpiMasterWB/TxCounter_cb12_5 i_Core/i_VmeInterface/adr_o_9
SLICE_X66Y74.B6 net (fanout=3) 1.068 i_Core/i_SpiMasterWB/TxCounter_cb12<5> SLICE_X75Y100.C2 net (fanout=4) 0.752 i_Core/i_VmeInterface/adr_o<9>
SLICE_X66Y74.B Tilo 0.235 i_Core/i_SpiMasterWB/Config1_qb32<6> SLICE_X75Y100.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o124 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o11
SLICE_X70Y69.C4 net (fanout=3) 1.650 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o123 SLICE_X75Y100.A2 net (fanout=4) 0.543 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
SLICE_X70Y69.CMUX Topcc 0.441 N261 SLICE_X75Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_lut i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_cy SLICE_X75Y93.B5 net (fanout=1) 0.883 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1
SLICE_X70Y71.A6 net (fanout=1) 0.526 N261 SLICE_X75Y93.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
SLICE_X70Y71.A Tilo 0.235 N299 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
i_Core/i_SpiMasterWB/_n0817_inv_SW0 SLICE_X67Y81.C6 net (fanout=5) 1.915 i_Core/StbSpiMaster
SLICE_X60Y77.B2 net (fanout=1) 1.658 N84 SLICE_X67Y81.C Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<31>
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31> i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o1
i_Core/i_SpiMasterWB/_n0817_inv SLICE_X67Y82.A5 net (fanout=3) 0.420 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o
SLICE_X62Y76.C6 net (fanout=32) 0.640 i_Core/i_SpiMasterWB/_n0817_inv SLICE_X67Y82.A Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<30>
SLICE_X62Y76.CLK Tas 0.349 i_Core/i_SpiMasterWB/ShiftIn_qb32<23> i_Core/i_SpiMasterWB/_n0745_inv
i_Core/i_SpiMasterWB/ShiftIn_qb32_22_rstpot SLICE_X67Y82.CE net (fanout=9) 1.243 i_Core/i_SpiMasterWB/_n0745_inv
i_Core/i_SpiMasterWB/ShiftIn_qb32_22 SLICE_X67Y82.CLK Tceck 0.382 i_Core/i_SpiMasterWB/Config2_qb32<30>
i_Core/i_SpiMasterWB/Config2_qb32_30
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 7.532ns (1.990ns logic, 5.542ns route) Total 7.863ns (2.107ns logic, 5.756ns route)
(26.4% logic, 73.6% route) (26.8% logic, 73.2% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (setup path): 0.813ns (requirement - (data path - clock path skew + uncertainty)) Slack (setup path): 0.592ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_13 (FF) Source: i_Core/i_VmeInterface/adr_o_10 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_22 (FF) Destination: i_Core/i_SpiMasterWB/Config2_qb32_30 (FF)
Requirement: 8.333ns Requirement: 8.333ns
Data Path Delay: 7.577ns (Levels of Logic = 6) Data Path Delay: 7.858ns (Levels of Logic = 5)
Clock Path Skew: 0.092ns (0.991 - 0.899) Clock Path Skew: 0.152ns (1.046 - 0.894)
Source Clock: Si57x_BUFG rising at 0.000ns Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns
...@@ -411,121 +415,117 @@ Slack (setup path): 0.813ns (requirement - (data path - clock path skew + un ...@@ -411,121 +415,117 @@ Slack (setup path): 0.813ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_13 to i_Core/i_SpiMasterWB/ShiftIn_qb32_22 Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_10 to i_Core/i_SpiMasterWB/Config2_qb32_30
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X79Y97.BQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<15> SLICE_X77Y100.CQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<11>
i_Core/i_VmeInterface/adr_o_13 i_Core/i_VmeInterface/adr_o_10
SLICE_X81Y97.B1 net (fanout=4) 0.741 i_Core/i_VmeInterface/adr_o<13> SLICE_X75Y100.C4 net (fanout=4) 0.747 i_Core/i_VmeInterface/adr_o<10>
SLICE_X81Y97.B Tilo 0.259 i_Core/i_VmeInterface/adr_o<10> SLICE_X75Y100.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o12 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o11
SLICE_X81Y97.A6 net (fanout=4) 0.554 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o11 SLICE_X75Y100.A2 net (fanout=4) 0.543 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
SLICE_X81Y97.A Tilo 0.259 i_Core/i_VmeInterface/adr_o<10> SLICE_X75Y100.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o1
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1
SLICE_X75Y88.B3 net (fanout=1) 1.560 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1 SLICE_X75Y93.B5 net (fanout=1) 0.883 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1
SLICE_X75Y88.B Tilo 0.259 i_Core/i_VmeInterface/ack_d SLICE_X75Y93.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X60Y77.C6 net (fanout=5) 1.716 i_Core/StbSpiMaster SLICE_X67Y81.C6 net (fanout=5) 1.915 i_Core/StbSpiMaster
SLICE_X60Y77.C Tilo 0.255 i_Core/i_SpiMasterWB/ShiftIn_qb32<31> SLICE_X67Y81.C Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<31>
i_Core/i_SpiMasterWB/_n0649_inv11_1 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o1
SLICE_X60Y77.B4 net (fanout=1) 0.301 i_Core/i_SpiMasterWB/_n0649_inv11 SLICE_X67Y82.A5 net (fanout=3) 0.420 i_Core/i_SpiMasterWB/Cyc_i_Stb_i_AND_232_o
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31> SLICE_X67Y82.A Tilo 0.259 i_Core/i_SpiMasterWB/Config2_qb32<30>
i_Core/i_SpiMasterWB/_n0817_inv i_Core/i_SpiMasterWB/_n0745_inv
SLICE_X62Y76.C6 net (fanout=32) 0.640 i_Core/i_SpiMasterWB/_n0817_inv SLICE_X67Y82.CE net (fanout=9) 1.243 i_Core/i_SpiMasterWB/_n0745_inv
SLICE_X62Y76.CLK Tas 0.349 i_Core/i_SpiMasterWB/ShiftIn_qb32<23> SLICE_X67Y82.CLK Tceck 0.382 i_Core/i_SpiMasterWB/Config2_qb32<30>
i_Core/i_SpiMasterWB/ShiftIn_qb32_22_rstpot i_Core/i_SpiMasterWB/Config2_qb32_30
i_Core/i_SpiMasterWB/ShiftIn_qb32_22
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 7.577ns (2.065ns logic, 5.512ns route) Total 7.858ns (2.107ns logic, 5.751ns route)
(27.3% logic, 72.7% route) (26.8% logic, 73.2% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Hold Paths: TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%; Hold Paths: TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%;
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Paths for end point i_Core/i_VmeInterface/dat_o_15 (SLICE_X82Y96.D6), 1 path Paths for end point i_Core/i_InterruptManager/Mram_int_fifo22/DP (SLICE_X44Y92.D3), 1 path
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (hold path): 0.413ns (requirement - (clock path skew + uncertainty - data path)) Slack (hold path): 0.225ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_VmeInterface/dat_o_15 (FF) Source: i_Core/i_InterruptManager/int_pointer_w_0 (FF)
Destination: i_Core/i_VmeInterface/dat_o_15 (FF) Destination: i_Core/i_InterruptManager/Mram_int_fifo22/DP (RAM)
Requirement: 0.000ns Requirement: 0.000ns
Data Path Delay: 0.413ns (Levels of Logic = 1) Data Path Delay: 0.227ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns Clock Path Skew: 0.002ns (0.040 - 0.038)
Source Clock: Si57x_BUFG rising at 0.000ns Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.000ns Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_VmeInterface/dat_o_15 to i_Core/i_VmeInterface/dat_o_15 Minimum Data Path at Fast Process Corner: i_Core/i_InterruptManager/int_pointer_w_0 to i_Core/i_InterruptManager/Mram_int_fifo22/DP
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X82Y96.DQ Tcko 0.200 i_Core/i_VmeInterface/dat_o<15> SLICE_X45Y92.AQ Tcko 0.198 i_Core/i_InterruptManager/int_pointer_w<2>
i_Core/i_VmeInterface/dat_o_15 i_Core/i_InterruptManager/int_pointer_w_0
SLICE_X82Y96.D6 net (fanout=8) 0.023 i_Core/i_VmeInterface/dat_o<15> SLICE_X44Y92.D3 net (fanout=9) 0.201 i_Core/i_InterruptManager/int_pointer_w<0>
SLICE_X82Y96.CLK Tah (-Th) -0.190 i_Core/i_VmeInterface/dat_o<15> SLICE_X44Y92.CLK Tah (-Th) 0.172 i_Core/i_InterruptManager/_n0165<6>
i_Core/i_VmeInterface/dat_o_15_dpot i_Core/i_InterruptManager/Mram_int_fifo22/DP
i_Core/i_VmeInterface/dat_o_15
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 0.413ns (0.390ns logic, 0.023ns route) Total 0.227ns (0.026ns logic, 0.201ns route)
(94.4% logic, 5.6% route) (11.5% logic, 88.5% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Paths for end point i_Core/i_VmeInterface/dat_o_19 (SLICE_X82Y92.D6), 1 path Paths for end point i_Core/i_InterruptManager/Mram_int_fifo21/DP (SLICE_X44Y92.D3), 1 path
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (hold path): 0.416ns (requirement - (clock path skew + uncertainty - data path)) Slack (hold path): 0.225ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_VmeInterface/dat_o_19 (FF) Source: i_Core/i_InterruptManager/int_pointer_w_0 (FF)
Destination: i_Core/i_VmeInterface/dat_o_19 (FF) Destination: i_Core/i_InterruptManager/Mram_int_fifo21/DP (RAM)
Requirement: 0.000ns Requirement: 0.000ns
Data Path Delay: 0.416ns (Levels of Logic = 1) Data Path Delay: 0.227ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns Clock Path Skew: 0.002ns (0.040 - 0.038)
Source Clock: Si57x_BUFG rising at 0.000ns Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.000ns Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_VmeInterface/dat_o_19 to i_Core/i_VmeInterface/dat_o_19 Minimum Data Path at Fast Process Corner: i_Core/i_InterruptManager/int_pointer_w_0 to i_Core/i_InterruptManager/Mram_int_fifo21/DP
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X82Y92.DQ Tcko 0.200 i_Core/i_VmeInterface/dat_o<19> SLICE_X45Y92.AQ Tcko 0.198 i_Core/i_InterruptManager/int_pointer_w<2>
i_Core/i_VmeInterface/dat_o_19 i_Core/i_InterruptManager/int_pointer_w_0
SLICE_X82Y92.D6 net (fanout=8) 0.026 i_Core/i_VmeInterface/dat_o<19> SLICE_X44Y92.D3 net (fanout=9) 0.201 i_Core/i_InterruptManager/int_pointer_w<0>
SLICE_X82Y92.CLK Tah (-Th) -0.190 i_Core/i_VmeInterface/dat_o<19> SLICE_X44Y92.CLK Tah (-Th) 0.172 i_Core/i_InterruptManager/_n0165<6>
i_Core/i_VmeInterface/dat_o_19_dpot i_Core/i_InterruptManager/Mram_int_fifo21/DP
i_Core/i_VmeInterface/dat_o_19
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 0.416ns (0.390ns logic, 0.026ns route) Total 0.227ns (0.026ns logic, 0.201ns route)
(93.8% logic, 6.3% route) (11.5% logic, 88.5% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Paths for end point i_Core/i_VmeInterface/VmeDOe_o (SLICE_X70Y98.A6), 1 path Paths for end point i_Core/i_InterruptManager/Mram_int_fifo22/SP (SLICE_X44Y92.D3), 1 path
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (hold path): 0.417ns (requirement - (clock path skew + uncertainty - data path)) Slack (hold path): 0.225ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_VmeInterface/VmeDOe_o (FF) Source: i_Core/i_InterruptManager/int_pointer_w_0 (FF)
Destination: i_Core/i_VmeInterface/VmeDOe_o (FF) Destination: i_Core/i_InterruptManager/Mram_int_fifo22/SP (RAM)
Requirement: 0.000ns Requirement: 0.000ns
Data Path Delay: 0.417ns (Levels of Logic = 1) Data Path Delay: 0.227ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns Clock Path Skew: 0.002ns (0.040 - 0.038)
Source Clock: Si57x_BUFG rising at 0.000ns Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.000ns Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_VmeInterface/VmeDOe_o to i_Core/i_VmeInterface/VmeDOe_o Minimum Data Path at Fast Process Corner: i_Core/i_InterruptManager/int_pointer_w_0 to i_Core/i_InterruptManager/Mram_int_fifo22/SP
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X70Y98.AQ Tcko 0.200 i_Core/i_VmeInterface/VmeDOe_o SLICE_X45Y92.AQ Tcko 0.198 i_Core/i_InterruptManager/int_pointer_w<2>
i_Core/i_VmeInterface/VmeDOe_o i_Core/i_InterruptManager/int_pointer_w_0
SLICE_X70Y98.A6 net (fanout=2) 0.027 i_Core/i_VmeInterface/VmeDOe_o SLICE_X44Y92.D3 net (fanout=9) 0.201 i_Core/i_InterruptManager/int_pointer_w<0>
SLICE_X70Y98.CLK Tah (-Th) -0.190 i_Core/i_VmeInterface/VmeDOe_o SLICE_X44Y92.CLK Tah (-Th) 0.172 i_Core/i_InterruptManager/_n0165<6>
i_Core/i_VmeInterface/Mmux__n031611 i_Core/i_InterruptManager/Mram_int_fifo22/SP
i_Core/i_VmeInterface/VmeDOe_o
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 0.417ns (0.390ns logic, 0.027ns route) Total 0.227ns (0.026ns logic, 0.201ns route)
(93.5% logic, 6.5% route) (11.5% logic, 88.5% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
...@@ -542,17 +542,17 @@ Slack: 5.833ns (period - min period limit) ...@@ -542,17 +542,17 @@ Slack: 5.833ns (period - min period limit)
Slack: 6.934ns (period - min period limit) Slack: 6.934ns (period - min period limit)
Period: 8.333ns Period: 8.333ns
Min period limit: 1.399ns (714.796MHz) (Tcp) Min period limit: 1.399ns (714.796MHz) (Tcp)
Physical resource: i_Core/i_Debouncer/BouncingSignal_x<2>/CLK Physical resource: i_Core/i_ClearMonostable/AsynchInAX_db4<3>/CLK
Logical resource: i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2/CLK Logical resource: i_Core/i_ClearMonostable/Mshreg_AsynchInAX_db4_2/CLK
Location pin: SLICE_X26Y36.CLK Location pin: SLICE_X26Y72.CLK
Clock network: Si57x_BUFG Clock network: Si57x_BUFG
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack: 6.934ns (period - min period limit) Slack: 6.934ns (period - min period limit)
Period: 8.333ns Period: 8.333ns
Min period limit: 1.399ns (714.796MHz) (Tcp) Min period limit: 1.399ns (714.796MHz) (Tcp)
Physical resource: i_Core/VmeSysReset_dx<1>/CLK Physical resource: i_Core/i_ClearMonostable/AsynchInAX_db4<3>/CLK
Logical resource: i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0/CLK Logical resource: i_Core/i_VmeAccessMonostable/Mshreg_AsynchInAX_db4_2/CLK
Location pin: SLICE_X72Y109.CLK Location pin: SLICE_X26Y72.CLK
Clock network: Si57x_BUFG Clock network: Si57x_BUFG
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
...@@ -562,17 +562,17 @@ Timing constraint: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH ...@@ -562,17 +562,17 @@ Timing constraint: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH
129 paths analyzed, 97 endpoints analyzed, 0 failing endpoints 129 paths analyzed, 97 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 3.869ns. Minimum period is 3.507ns.
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_28 (SLICE_X66Y91.CE), 2 paths Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_18 (SLICE_X69Y105.CE), 2 paths
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (setup path): 4.464ns (requirement - (data path - clock path skew + uncertainty)) Slack (setup path): 4.826ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF) Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_28 (FF) Destination: i_Core/i_Slv2SerWB/Dat_xb32_18 (FF)
Requirement: 8.333ns Requirement: 8.333ns
Data Path Delay: 3.807ns (Levels of Logic = 1) Data Path Delay: 3.268ns (Levels of Logic = 1)
Clock Path Skew: -0.027ns (1.040 - 1.067) Clock Path Skew: -0.204ns (0.767 - 0.971)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns
...@@ -583,29 +583,29 @@ Slack (setup path): 4.464ns (requirement - (data path - clock path skew + un ...@@ -583,29 +583,29 @@ Slack (setup path): 4.464ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_28 Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_18
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X42Y101.CQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2> SLICE_X54Y103.CQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_2 i_Core/i_Slv2SerWB/AckI_d3_2
SLICE_X54Y99.A3 net (fanout=1) 1.189 i_Core/i_Slv2SerWB/AckI_d3<2> SLICE_X57Y103.A3 net (fanout=1) 0.592 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X54Y99.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3> SLICE_X57Y103.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1 i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X66Y91.CE net (fanout=7) 1.593 i_Core/i_Slv2SerWB/NewAckI_a SLICE_X69Y105.CE net (fanout=7) 1.533 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X66Y91.CLK Tceck 0.314 i_Core/i_Slv2SerWB/Dat_xb32<31> SLICE_X69Y105.CLK Tceck 0.408 i_Core/i_Slv2SerWB/Dat_xb32<19>
i_Core/i_Slv2SerWB/Dat_xb32_28 i_Core/i_Slv2SerWB/Dat_xb32_18
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 3.807ns (1.025ns logic, 2.782ns route) Total 3.268ns (1.143ns logic, 2.125ns route)
(26.9% logic, 73.1% route) (35.0% logic, 65.0% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (setup path): 4.521ns (requirement - (data path - clock path skew + uncertainty)) Slack (setup path): 4.914ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_1 (FF) Source: i_Core/i_Slv2SerWB/AckI_d3_1 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_28 (FF) Destination: i_Core/i_Slv2SerWB/Dat_xb32_18 (FF)
Requirement: 8.333ns Requirement: 8.333ns
Data Path Delay: 3.750ns (Levels of Logic = 1) Data Path Delay: 3.180ns (Levels of Logic = 1)
Clock Path Skew: -0.027ns (1.040 - 1.067) Clock Path Skew: -0.204ns (0.767 - 0.971)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns
...@@ -616,32 +616,32 @@ Slack (setup path): 4.521ns (requirement - (data path - clock path skew + un ...@@ -616,32 +616,32 @@ Slack (setup path): 4.521ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_28 Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_18
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X42Y101.BQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2> SLICE_X54Y103.BQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_1 i_Core/i_Slv2SerWB/AckI_d3_1
SLICE_X54Y99.A4 net (fanout=2) 1.132 i_Core/i_Slv2SerWB/AckI_d3<1> SLICE_X57Y103.A4 net (fanout=2) 0.504 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X54Y99.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3> SLICE_X57Y103.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1 i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X66Y91.CE net (fanout=7) 1.593 i_Core/i_Slv2SerWB/NewAckI_a SLICE_X69Y105.CE net (fanout=7) 1.533 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X66Y91.CLK Tceck 0.314 i_Core/i_Slv2SerWB/Dat_xb32<31> SLICE_X69Y105.CLK Tceck 0.408 i_Core/i_Slv2SerWB/Dat_xb32<19>
i_Core/i_Slv2SerWB/Dat_xb32_28 i_Core/i_Slv2SerWB/Dat_xb32_18
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 3.750ns (1.025ns logic, 2.725ns route) Total 3.180ns (1.143ns logic, 2.037ns route)
(27.3% logic, 72.7% route) (35.9% logic, 64.1% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_16 (SLICE_X68Y101.CE), 2 paths Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_22 (SLICE_X69Y97.CE), 2 paths
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (setup path): 4.473ns (requirement - (data path - clock path skew + uncertainty)) Slack (setup path): 4.834ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF) Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_16 (FF) Destination: i_Core/i_Slv2SerWB/Dat_xb32_22 (FF)
Requirement: 8.333ns Requirement: 8.333ns
Data Path Delay: 3.622ns (Levels of Logic = 1) Data Path Delay: 3.270ns (Levels of Logic = 1)
Clock Path Skew: -0.203ns (0.770 - 0.973) Clock Path Skew: -0.194ns (0.777 - 0.971)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns
...@@ -652,29 +652,29 @@ Slack (setup path): 4.473ns (requirement - (data path - clock path skew + un ...@@ -652,29 +652,29 @@ Slack (setup path): 4.473ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_16 Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_22
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X42Y101.CQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2> SLICE_X54Y103.CQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_2 i_Core/i_Slv2SerWB/AckI_d3_2
SLICE_X54Y99.A3 net (fanout=1) 1.189 i_Core/i_Slv2SerWB/AckI_d3<2> SLICE_X57Y103.A3 net (fanout=1) 0.592 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X54Y99.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3> SLICE_X57Y103.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1 i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X68Y101.CE net (fanout=7) 1.409 i_Core/i_Slv2SerWB/NewAckI_a SLICE_X69Y97.CE net (fanout=7) 1.535 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X68Y101.CLK Tceck 0.313 i_Core/i_Slv2SerWB/Dat_xb32<19> SLICE_X69Y97.CLK Tceck 0.408 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_16 i_Core/i_Slv2SerWB/Dat_xb32_22
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 3.622ns (1.024ns logic, 2.598ns route) Total 3.270ns (1.143ns logic, 2.127ns route)
(28.3% logic, 71.7% route) (35.0% logic, 65.0% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (setup path): 4.530ns (requirement - (data path - clock path skew + uncertainty)) Slack (setup path): 4.922ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_1 (FF) Source: i_Core/i_Slv2SerWB/AckI_d3_1 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_16 (FF) Destination: i_Core/i_Slv2SerWB/Dat_xb32_22 (FF)
Requirement: 8.333ns Requirement: 8.333ns
Data Path Delay: 3.565ns (Levels of Logic = 1) Data Path Delay: 3.182ns (Levels of Logic = 1)
Clock Path Skew: -0.203ns (0.770 - 0.973) Clock Path Skew: -0.194ns (0.777 - 0.971)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns
...@@ -685,32 +685,32 @@ Slack (setup path): 4.530ns (requirement - (data path - clock path skew + un ...@@ -685,32 +685,32 @@ Slack (setup path): 4.530ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_16 Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_22
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X42Y101.BQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2> SLICE_X54Y103.BQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_1 i_Core/i_Slv2SerWB/AckI_d3_1
SLICE_X54Y99.A4 net (fanout=2) 1.132 i_Core/i_Slv2SerWB/AckI_d3<1> SLICE_X57Y103.A4 net (fanout=2) 0.504 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X54Y99.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3> SLICE_X57Y103.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1 i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X68Y101.CE net (fanout=7) 1.409 i_Core/i_Slv2SerWB/NewAckI_a SLICE_X69Y97.CE net (fanout=7) 1.535 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X68Y101.CLK Tceck 0.313 i_Core/i_Slv2SerWB/Dat_xb32<19> SLICE_X69Y97.CLK Tceck 0.408 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_16 i_Core/i_Slv2SerWB/Dat_xb32_22
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 3.565ns (1.024ns logic, 2.541ns route) Total 3.182ns (1.143ns logic, 2.039ns route)
(28.7% logic, 71.3% route) (35.9% logic, 64.1% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_31 (SLICE_X66Y91.CE), 2 paths Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_17 (SLICE_X69Y105.CE), 2 paths
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (setup path): 4.487ns (requirement - (data path - clock path skew + uncertainty)) Slack (setup path): 4.844ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF) Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_31 (FF) Destination: i_Core/i_Slv2SerWB/Dat_xb32_17 (FF)
Requirement: 8.333ns Requirement: 8.333ns
Data Path Delay: 3.784ns (Levels of Logic = 1) Data Path Delay: 3.250ns (Levels of Logic = 1)
Clock Path Skew: -0.027ns (1.040 - 1.067) Clock Path Skew: -0.204ns (0.767 - 0.971)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns
...@@ -721,29 +721,29 @@ Slack (setup path): 4.487ns (requirement - (data path - clock path skew + un ...@@ -721,29 +721,29 @@ Slack (setup path): 4.487ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_31 Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_17
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X42Y101.CQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2> SLICE_X54Y103.CQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_2 i_Core/i_Slv2SerWB/AckI_d3_2
SLICE_X54Y99.A3 net (fanout=1) 1.189 i_Core/i_Slv2SerWB/AckI_d3<2> SLICE_X57Y103.A3 net (fanout=1) 0.592 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X54Y99.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3> SLICE_X57Y103.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1 i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X66Y91.CE net (fanout=7) 1.593 i_Core/i_Slv2SerWB/NewAckI_a SLICE_X69Y105.CE net (fanout=7) 1.533 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X66Y91.CLK Tceck 0.291 i_Core/i_Slv2SerWB/Dat_xb32<31> SLICE_X69Y105.CLK Tceck 0.390 i_Core/i_Slv2SerWB/Dat_xb32<19>
i_Core/i_Slv2SerWB/Dat_xb32_31 i_Core/i_Slv2SerWB/Dat_xb32_17
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 3.784ns (1.002ns logic, 2.782ns route) Total 3.250ns (1.125ns logic, 2.125ns route)
(26.5% logic, 73.5% route) (34.6% logic, 65.4% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (setup path): 4.544ns (requirement - (data path - clock path skew + uncertainty)) Slack (setup path): 4.932ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_1 (FF) Source: i_Core/i_Slv2SerWB/AckI_d3_1 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_31 (FF) Destination: i_Core/i_Slv2SerWB/Dat_xb32_17 (FF)
Requirement: 8.333ns Requirement: 8.333ns
Data Path Delay: 3.727ns (Levels of Logic = 1) Data Path Delay: 3.162ns (Levels of Logic = 1)
Clock Path Skew: -0.027ns (1.040 - 1.067) Clock Path Skew: -0.204ns (0.767 - 0.971)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns
...@@ -754,105 +754,105 @@ Slack (setup path): 4.544ns (requirement - (data path - clock path skew + un ...@@ -754,105 +754,105 @@ Slack (setup path): 4.544ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_31 Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_17
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X42Y101.BQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2> SLICE_X54Y103.BQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_1 i_Core/i_Slv2SerWB/AckI_d3_1
SLICE_X54Y99.A4 net (fanout=2) 1.132 i_Core/i_Slv2SerWB/AckI_d3<1> SLICE_X57Y103.A4 net (fanout=2) 0.504 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X54Y99.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3> SLICE_X57Y103.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1 i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X66Y91.CE net (fanout=7) 1.593 i_Core/i_Slv2SerWB/NewAckI_a SLICE_X69Y105.CE net (fanout=7) 1.533 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X66Y91.CLK Tceck 0.291 i_Core/i_Slv2SerWB/Dat_xb32<31> SLICE_X69Y105.CLK Tceck 0.390 i_Core/i_Slv2SerWB/Dat_xb32<19>
i_Core/i_Slv2SerWB/Dat_xb32_31 i_Core/i_Slv2SerWB/Dat_xb32_17
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 3.727ns (1.002ns logic, 2.725ns route) Total 3.162ns (1.125ns logic, 2.037ns route)
(26.9% logic, 73.1% route) (35.6% logic, 64.4% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Hold Paths: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%; Hold Paths: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%;
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_14 (SLICE_X66Y101.CX), 1 path Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_21 (SLICE_X69Y97.BX), 1 path
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (hold path): 0.442ns (requirement - (clock path skew + uncertainty - data path)) Slack (hold path): 0.468ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_14 (FF) Source: i_Core/i_Slv2SerWB/DatInShReg_b32_21 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_14 (FF) Destination: i_Core/i_Slv2SerWB/Dat_xb32_21 (FF)
Requirement: 0.000ns Requirement: 0.000ns
Data Path Delay: 0.442ns (Levels of Logic = 0) Data Path Delay: 0.472ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns Clock Path Skew: 0.004ns (0.044 - 0.040)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.000ns Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_14 to i_Core/i_Slv2SerWB/Dat_xb32_14 Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_21 to i_Core/i_Slv2SerWB/Dat_xb32_21
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X66Y100.CQ Tcko 0.200 i_Core/i_Slv2SerWB/DatInShReg_b32<15> SLICE_X69Y99.BQ Tcko 0.198 i_Core/i_Slv2SerWB/DatInShReg_b32<23>
i_Core/i_Slv2SerWB/DatInShReg_b32_14 i_Core/i_Slv2SerWB/DatInShReg_b32_21
SLICE_X66Y101.CX net (fanout=2) 0.194 i_Core/i_Slv2SerWB/DatInShReg_b32<14> SLICE_X69Y97.BX net (fanout=2) 0.215 i_Core/i_Slv2SerWB/DatInShReg_b32<21>
SLICE_X66Y101.CLK Tckdi (-Th) -0.048 i_Core/i_Slv2SerWB/Dat_xb32<15> SLICE_X69Y97.CLK Tckdi (-Th) -0.059 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_14 i_Core/i_Slv2SerWB/Dat_xb32_21
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 0.442ns (0.248ns logic, 0.194ns route) Total 0.472ns (0.257ns logic, 0.215ns route)
(56.1% logic, 43.9% route) (54.4% logic, 45.6% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_15 (SLICE_X66Y101.DX), 1 path Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_23 (SLICE_X69Y97.DX), 1 path
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (hold path): 0.442ns (requirement - (clock path skew + uncertainty - data path)) Slack (hold path): 0.468ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_15 (FF) Source: i_Core/i_Slv2SerWB/DatInShReg_b32_23 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_15 (FF) Destination: i_Core/i_Slv2SerWB/Dat_xb32_23 (FF)
Requirement: 0.000ns Requirement: 0.000ns
Data Path Delay: 0.442ns (Levels of Logic = 0) Data Path Delay: 0.472ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns Clock Path Skew: 0.004ns (0.044 - 0.040)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.000ns Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_15 to i_Core/i_Slv2SerWB/Dat_xb32_15 Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_23 to i_Core/i_Slv2SerWB/Dat_xb32_23
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X66Y100.DQ Tcko 0.200 i_Core/i_Slv2SerWB/DatInShReg_b32<15> SLICE_X69Y99.DQ Tcko 0.198 i_Core/i_Slv2SerWB/DatInShReg_b32<23>
i_Core/i_Slv2SerWB/DatInShReg_b32_15 i_Core/i_Slv2SerWB/DatInShReg_b32_23
SLICE_X66Y101.DX net (fanout=2) 0.194 i_Core/i_Slv2SerWB/DatInShReg_b32<15> SLICE_X69Y97.DX net (fanout=2) 0.215 i_Core/i_Slv2SerWB/DatInShReg_b32<23>
SLICE_X66Y101.CLK Tckdi (-Th) -0.048 i_Core/i_Slv2SerWB/Dat_xb32<15> SLICE_X69Y97.CLK Tckdi (-Th) -0.059 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_15 i_Core/i_Slv2SerWB/Dat_xb32_23
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 0.442ns (0.248ns logic, 0.194ns route) Total 0.472ns (0.257ns logic, 0.215ns route)
(56.1% logic, 43.9% route) (54.4% logic, 45.6% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_8 (SLICE_X61Y99.AX), 1 path Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_22 (SLICE_X69Y97.CX), 1 path
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack (hold path): 0.451ns (requirement - (clock path skew + uncertainty - data path)) Slack (hold path): 0.470ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_8 (FF) Source: i_Core/i_Slv2SerWB/DatInShReg_b32_22 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_8 (FF) Destination: i_Core/i_Slv2SerWB/Dat_xb32_22 (FF)
Requirement: 0.000ns Requirement: 0.000ns
Data Path Delay: 0.455ns (Levels of Logic = 0) Data Path Delay: 0.474ns (Levels of Logic = 0)
Clock Path Skew: 0.004ns (0.040 - 0.036) Clock Path Skew: 0.004ns (0.044 - 0.040)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.000ns Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_8 to i_Core/i_Slv2SerWB/Dat_xb32_8 Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_22 to i_Core/i_Slv2SerWB/Dat_xb32_22
Location Delay type Delay(ns) Physical Resource Location Delay type Delay(ns) Physical Resource
Logical Resource(s) Logical Resource(s)
------------------------------------------------- ------------------- ------------------------------------------------- -------------------
SLICE_X61Y100.AQ Tcko 0.198 i_Core/i_Slv2SerWB/DatInShReg_b32<11> SLICE_X69Y99.CQ Tcko 0.198 i_Core/i_Slv2SerWB/DatInShReg_b32<23>
i_Core/i_Slv2SerWB/DatInShReg_b32_8 i_Core/i_Slv2SerWB/DatInShReg_b32_22
SLICE_X61Y99.AX net (fanout=2) 0.198 i_Core/i_Slv2SerWB/DatInShReg_b32<8> SLICE_X69Y97.CX net (fanout=2) 0.217 i_Core/i_Slv2SerWB/DatInShReg_b32<22>
SLICE_X61Y99.CLK Tckdi (-Th) -0.059 i_Core/i_Slv2SerWB/Dat_xb32<11> SLICE_X69Y97.CLK Tckdi (-Th) -0.059 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_8 i_Core/i_Slv2SerWB/Dat_xb32_22
------------------------------------------------- --------------------------- ------------------------------------------------- ---------------------------
Total 0.455ns (0.257ns logic, 0.198ns route) Total 0.474ns (0.257ns logic, 0.217ns route)
(56.5% logic, 43.5% route) (54.2% logic, 45.8% route)
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
...@@ -869,17 +869,17 @@ Slack: 5.833ns (period - min period limit) ...@@ -869,17 +869,17 @@ Slack: 5.833ns (period - min period limit)
Slack: 7.853ns (period - min period limit) Slack: 7.853ns (period - min period limit)
Period: 8.333ns Period: 8.333ns
Min period limit: 0.480ns (2083.333MHz) (Tcp) Min period limit: 0.480ns (2083.333MHz) (Tcp)
Physical resource: i_Core/i_Slv2SerWB/DatInShReg_b32<23>/CLK Physical resource: i_Core/i_Slv2SerWB/AckI_xb3_2/CLK
Logical resource: i_Core/i_Slv2SerWB/DatInShReg_b32_20/CK Logical resource: i_Core/i_Slv2SerWB/AckI_xb3_2/CK
Location pin: SLICE_X68Y99.CLK Location pin: SLICE_X48Y103.CLK
Clock network: SysAppClk_ik_BUFGP Clock network: SysAppClk_ik_BUFGP
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Slack: 7.853ns (period - min period limit) Slack: 7.853ns (period - min period limit)
Period: 8.333ns Period: 8.333ns
Min period limit: 0.480ns (2083.333MHz) (Tcp) Min period limit: 0.480ns (2083.333MHz) (Tcp)
Physical resource: i_Core/i_Slv2SerWB/DatInShReg_b32<23>/CLK Physical resource: i_Core/i_Slv2SerWB/DatInShReg_b32<7>/CLK
Logical resource: i_Core/i_Slv2SerWB/DatInShReg_b32_21/CK Logical resource: i_Core/i_Slv2SerWB/DatInShReg_b32_0/CK
Location pin: SLICE_X68Y99.CLK Location pin: SLICE_X56Y103.CLK
Clock network: SysAppClk_ik_BUFGP Clock network: SysAppClk_ik_BUFGP
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
...@@ -896,8 +896,8 @@ Clock to Setup on destination clock Si57x_ik ...@@ -896,8 +896,8 @@ Clock to Setup on destination clock Si57x_ik
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+ ---------------+---------+---------+---------+---------+
Si57x_ik | 7.898| | | | Si57x_ik | 7.904| | | |
Si57x_ikn | 7.898| | | | Si57x_ikn | 7.904| | | |
---------------+---------+---------+---------+---------+ ---------------+---------+---------+---------+---------+
Clock to Setup on destination clock Si57x_ikn Clock to Setup on destination clock Si57x_ikn
...@@ -905,8 +905,8 @@ Clock to Setup on destination clock Si57x_ikn ...@@ -905,8 +905,8 @@ Clock to Setup on destination clock Si57x_ikn
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+ ---------------+---------+---------+---------+---------+
Si57x_ik | 7.898| | | | Si57x_ik | 7.904| | | |
Si57x_ikn | 7.898| | | | Si57x_ikn | 7.904| | | |
---------------+---------+---------+---------+---------+ ---------------+---------+---------+---------+---------+
Clock to Setup on destination clock SysAppClk_ik Clock to Setup on destination clock SysAppClk_ik
...@@ -914,7 +914,7 @@ Clock to Setup on destination clock SysAppClk_ik ...@@ -914,7 +914,7 @@ Clock to Setup on destination clock SysAppClk_ik
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+ ---------------+---------+---------+---------+---------+
SysAppClk_ik | 3.869| | | | SysAppClk_ik | 3.507| | | |
---------------+---------+---------+---------+---------+ ---------------+---------+---------+---------+---------+
...@@ -923,23 +923,23 @@ Timing summary: ...@@ -923,23 +923,23 @@ Timing summary:
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0) Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 44854 paths, 0 nets, and 4274 connections Constraints cover 45718 paths, 0 nets, and 4267 connections
Design statistics: Design statistics:
Minimum period: 7.898ns{1} (Maximum frequency: 126.614MHz) Minimum period: 7.904ns{1} (Maximum frequency: 126.518MHz)
------------------------------------Footnotes----------------------------------- ------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays. 1) The minimum period statistic assumes all single cycle delays.
Analysis completed Fri Dec 17 11:13:07 2010 Analysis completed Mon Dec 20 08:27:42 2010
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Trace Settings: Trace Settings:
------------------------- -------------------------
Trace Settings Trace Settings
Peak Memory Usage: 389 MB Peak Memory Usage: 397 MB
trunk/firmware/XilinxISE/SystemFpga/SFpga.twx
View file @ 265c6bd0
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.unroutes
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Release 12.3 - par M.70d (nt64) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 11:12:54 2010 Mon Dec 20 08:27:29 2010
All signals are completely routed. All signals are completely routed.
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_envsettings.html
View file @ 265c6bd0
...@@ -22,10 +22,10 @@ ...@@ -22,10 +22,10 @@
</tr> </tr>
<tr> <tr>
<td>Path</td> <td>Path</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
</tr> </tr>
<tr> <tr>
<td>XILINX</td> <td>XILINX</td>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_guide.ncd
View file @ 265c6bd0
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.map
View file @ 265c6bd0
...@@ -10,7 +10,7 @@ Target Device : xc6slx150t ...@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Dec 17 11:11:25 2010 Mapped Date : Mon Dec 20 08:25:44 2010
Mapping design into LUTs... Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
...@@ -89,20 +89,20 @@ Updating timing models... ...@@ -89,20 +89,20 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). (.mrp).
Running timing-driven placement... Running timing-driven placement...
Total REAL time at the beginning of Placer: 16 secs Total REAL time at the beginning of Placer: 30 secs
Total CPU time at the beginning of Placer: 12 secs Total CPU time at the beginning of Placer: 13 secs
Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:fbd9bf1c) REAL time: 21 secs Phase 1.1 Initial Placement Analysis (Checksum:ee27935a) REAL time: 36 secs
Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked
and 2 are not locked. If you would like to print the names of these IOs, and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:fbd9bf1c) REAL time: 22 secs Phase 2.7 Design Feasibility Check (Checksum:ee27935a) REAL time: 36 secs
Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:fbd9bf1c) REAL time: 22 secs Phase 3.31 Local Placement Optimization (Checksum:ee27935a) REAL time: 36 secs
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
... ...
...@@ -120,42 +120,42 @@ WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found ...@@ -120,42 +120,42 @@ WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
discouraged as it may lead to very poor timing results. It is recommended discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design. that this error condition be corrected in the design.
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:b9a90c54) REAL time: 29 secs (Checksum:d3736e22) REAL time: 44 secs
Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:b9a90c54) REAL time: 29 secs Phase 5.36 Local Placement Optimization (Checksum:d3736e22) REAL time: 44 secs
Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:b9a90c54) REAL time: 29 secs Phase 6.30 Global Clock Region Assignment (Checksum:d3736e22) REAL time: 44 secs
Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization
... ...
Phase 7.3 Local Placement Optimization (Checksum:5a4374ed) REAL time: 30 secs Phase 7.3 Local Placement Optimization (Checksum:d47075b5) REAL time: 45 secs
Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:b9b9c566) REAL time: 30 secs Phase 8.5 Local Placement Optimization (Checksum:d384eabe) REAL time: 45 secs
Phase 9.8 Global Placement Phase 9.8 Global Placement
... ........
....................... .......................
................ .....................................
...... ....
Phase 9.8 Global Placement (Checksum:94595592) REAL time: 36 secs Phase 9.8 Global Placement (Checksum:7253f7a8) REAL time: 52 secs
Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:94595592) REAL time: 36 secs Phase 10.5 Local Placement Optimization (Checksum:7253f7a8) REAL time: 52 secs
Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:df505277) REAL time: 47 secs Phase 11.18 Placement Optimization (Checksum:85580283) REAL time: 1 mins 2 secs
Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:df505277) REAL time: 47 secs Phase 12.5 Local Placement Optimization (Checksum:85580283) REAL time: 1 mins 2 secs
Phase 13.34 Placement Validation Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:967c17e4) REAL time: 47 secs Phase 13.34 Placement Validation (Checksum:8244a4e2) REAL time: 1 mins 3 secs
Total REAL time to Placer completion: 52 secs Total REAL time to Placer completion: 1 mins 7 secs
Total CPU time to Placer completion: 47 secs Total CPU time to Placer completion: 48 secs
Running post-placement packing... Running post-placement packing...
Writing output files... Writing output files...
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The
...@@ -261,41 +261,41 @@ Design Summary: ...@@ -261,41 +261,41 @@ Design Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 83 Number of warnings: 83
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1% Number of Slice Registers: 812 out of 184,304 1%
Number used as Flip Flops: 796 Number used as Flip Flops: 812
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 934 out of 92,152 1% Number of Slice LUTs: 954 out of 92,152 1%
Number used as logic: 891 out of 92,152 1% Number used as logic: 911 out of 92,152 1%
Number using O6 output only: 571 Number using O6 output only: 573
Number using O5 output only: 154 Number using O5 output only: 172
Number using O5 and O6: 166 Number using O5 and O6: 166
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1% Number used as Memory: 13 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
Number using O6 output only: 4 Number using O6 output only: 4
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 4 Number using O5 and O6: 4
Number used as Single Port RAM: 0 Number used as Single Port RAM: 0
Number used as Shift Register: 3 Number used as Shift Register: 5
Number using O6 output only: 3 Number using O6 output only: 5
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 32 Number used exclusively as route-thrus: 30
Number with same-slice register load: 23 Number with same-slice register load: 21
Number with same-slice carry load: 9 Number with same-slice carry load: 9
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 374 out of 23,038 1% Number of occupied Slices: 365 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,101 Number of LUT Flip Flop pairs used: 1,098
Number with an unused Flip Flop: 386 out of 1,101 35% Number with an unused Flip Flop: 364 out of 1,098 33%
Number with an unused LUT: 167 out of 1,101 15% Number with an unused LUT: 144 out of 1,098 13%
Number of fully used LUT-FF pairs: 548 out of 1,101 49% Number of fully used LUT-FF pairs: 590 out of 1,098 53%
Number of unique control sets: 32 Number of unique control sets: 32
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 85 out of 184,304 1% to control set restrictions: 83 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of one Flip Flop within a slice. A control set is a unique combination of
...@@ -336,11 +336,11 @@ Specific Feature Utilization: ...@@ -336,11 +336,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.02 Average Fanout of Non-Clock Nets: 3.01
Peak Memory Usage: 629 MB Peak Memory Usage: 630 MB
Total REAL time to MAP completion: 54 secs Total REAL time to MAP completion: 1 mins 10 secs
Total CPU time to MAP completion: 49 secs Total CPU time to MAP completion: 50 secs
Mapping completed. Mapping completed.
See MAP report file "SFpga_map.mrp" for details. See MAP report file "SFpga_map.mrp" for details.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.mrp
View file @ 265c6bd0
...@@ -10,48 +10,48 @@ Target Device : xc6slx150t ...@@ -10,48 +10,48 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Dec 17 11:11:25 2010 Mapped Date : Mon Dec 20 08:25:44 2010
Design Summary Design Summary
-------------- --------------
Number of errors: 0 Number of errors: 0
Number of warnings: 83 Number of warnings: 83
Slice Logic Utilization: Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1% Number of Slice Registers: 812 out of 184,304 1%
Number used as Flip Flops: 796 Number used as Flip Flops: 812
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 934 out of 92,152 1% Number of Slice LUTs: 954 out of 92,152 1%
Number used as logic: 891 out of 92,152 1% Number used as logic: 911 out of 92,152 1%
Number using O6 output only: 571 Number using O6 output only: 573
Number using O5 output only: 154 Number using O5 output only: 172
Number using O5 and O6: 166 Number using O5 and O6: 166
Number used as ROM: 0 Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1% Number used as Memory: 13 out of 21,680 1%
Number used as Dual Port RAM: 8 Number used as Dual Port RAM: 8
Number using O6 output only: 4 Number using O6 output only: 4
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 4 Number using O5 and O6: 4
Number used as Single Port RAM: 0 Number used as Single Port RAM: 0
Number used as Shift Register: 3 Number used as Shift Register: 5
Number using O6 output only: 3 Number using O6 output only: 5
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 0 Number using O5 and O6: 0
Number used exclusively as route-thrus: 32 Number used exclusively as route-thrus: 30
Number with same-slice register load: 23 Number with same-slice register load: 21
Number with same-slice carry load: 9 Number with same-slice carry load: 9
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 374 out of 23,038 1% Number of occupied Slices: 365 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,101 Number of LUT Flip Flop pairs used: 1,098
Number with an unused Flip Flop: 386 out of 1,101 35% Number with an unused Flip Flop: 364 out of 1,098 33%
Number with an unused LUT: 167 out of 1,101 15% Number with an unused LUT: 144 out of 1,098 13%
Number of fully used LUT-FF pairs: 548 out of 1,101 49% Number of fully used LUT-FF pairs: 590 out of 1,098 53%
Number of unique control sets: 32 Number of unique control sets: 32
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 85 out of 184,304 1% to control set restrictions: 83 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of one Flip Flop within a slice. A control set is a unique combination of
...@@ -92,11 +92,11 @@ Specific Feature Utilization: ...@@ -92,11 +92,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.02 Average Fanout of Non-Clock Nets: 3.01
Peak Memory Usage: 629 MB Peak Memory Usage: 630 MB
Total REAL time to MAP completion: 54 secs Total REAL time to MAP completion: 1 mins 10 secs
Total CPU time to MAP completion: 49 secs Total CPU time to MAP completion: 50 secs
Table of Contents Table of Contents
----------------- -----------------
...@@ -299,10 +299,10 @@ WARNING:PhysDesignRules:367 - The signal ...@@ -299,10 +299,10 @@ WARNING:PhysDesignRules:367 - The signal
Section 3 - Informational Section 3 - Informational
------------------------- -------------------------
INFO:LIT:243 - Logical network N450 has no load. INFO:LIT:243 - Logical network N456 has no load.
INFO:LIT:395 - The above info message is repeated 51 more times for the INFO:LIT:395 - The above info message is repeated 51 more times for the
following (max. 5 shown): following (max. 5 shown):
N452, N458,
VmeAm_ib6<2>_IBUF, VmeAm_ib6<2>_IBUF,
VmeAm_ib6<1>_IBUF, VmeAm_ib6<1>_IBUF,
VmeDs_inb2<2>_IBUF, VmeDs_inb2<2>_IBUF,
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.ncd
View file @ 265c6bd0
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.ngm
View file @ 265c6bd0
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.xrpt
View file @ 265c6bd0
...@@ -5,14 +5,14 @@ ...@@ -5,14 +5,14 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Fri Dec 17 11:12:20 2010"> <application stringID="Map" timeStamp="Mon Dec 20 08:26:54 2010">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
<column stringID="value"/> <column stringID="value"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="variable" value="Path"/> <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row> </row>
<row stringID="row" value="1"> <row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/> <item stringID="variable" value="PATHEXT"/>
...@@ -64,15 +64,15 @@ ...@@ -64,15 +64,15 @@
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx150t-fgg676-3"/> <item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx150t-fgg676-3"/>
</section> </section>
<task stringID="MAP_PACK_REPORT"> <task stringID="MAP_PACK_REPORT">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="796"> <item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="812">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="796"/> <item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="812"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item> </item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="911"> <item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="933">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="154"/> <item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="172"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="571"/> <item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="573"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="166"/> <item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="166"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
...@@ -84,7 +84,7 @@ ...@@ -84,7 +84,7 @@
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="3"/> <item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="5"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="9"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="9"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/>
...@@ -116,20 +116,20 @@ ...@@ -116,20 +116,20 @@
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/> <item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/> <item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="83"/> <item dataType="int" stringID="MAP_NUM_WARNINGS" value="83"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="644084"/> <item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="645556"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="54 secs "/> <item stringID="MAP_TOTAL_REAL_TIME" value="1 mins 10 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="49 secs "/> <item stringID="MAP_TOTAL_CPU_TIME" value="50 secs "/>
</section> </section>
<section stringID="MAP_SLICE_REPORTING"> <section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="796"> <item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="812">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="796"/> <item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="812"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item> </item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="934"> <item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="954">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="154"/> <item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="172"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="571"/> <item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="573"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="166"/> <item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="166"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
...@@ -141,24 +141,24 @@ ...@@ -141,24 +141,24 @@
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/> <item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="3"/> <item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="5"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="9"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="9"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="23"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="21"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="23"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="21"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="9"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="9"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item> </item>
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="374"> <item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="365">
<item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="70"/> <item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="84"/>
<item AVAILABLE="5420" dataType="int" stringID="MAP_NUM_SLICEM" value="4"/> <item AVAILABLE="5420" dataType="int" stringID="MAP_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="300"/> <item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="277"/>
</item> </item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1101"> <item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1098">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="386"/> <item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="364"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="167"/> <item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="144"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="548"/> <item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="590"/>
</item> </item>
</section> </section>
<section stringID="MAP_IOB_REPORTING"> <section stringID="MAP_IOB_REPORTING">
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_ngdbuild.xrpt
View file @ 265c6bd0
...@@ -5,14 +5,14 @@ ...@@ -5,14 +5,14 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Fri Dec 17 11:11:22 2010"> <application stringID="NgdBuild" timeStamp="Mon Dec 20 08:25:40 2010">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
<column stringID="value"/> <column stringID="value"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="variable" value="Path"/> <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row> </row>
<row stringID="row" value="1"> <row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/> <item stringID="variable" value="PATHEXT"/>
...@@ -68,11 +68,11 @@ ...@@ -68,11 +68,11 @@
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY"> <section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="189"/> <item dataType="int" stringID="NGDBUILD_NUM_FD" value="191"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="99"/> <item dataType="int" stringID="NGDBUILD_NUM_FDE" value="101"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="135"/> <item dataType="int" stringID="NGDBUILD_NUM_FDR" value="135"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="313"/> <item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="325"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/> <item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="33"/> <item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
...@@ -81,30 +81,30 @@ ...@@ -81,30 +81,30 @@
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="29"/> <item dataType="int" stringID="NGDBUILD_NUM_INV" value="29"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUF" value="32"/> <item dataType="int" stringID="NGDBUILD_NUM_IOBUF" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUFDS" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_IOBUFDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="163"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="181"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="163"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="166"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="121"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="130"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="112"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="113"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="148"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="146"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="299"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="204"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="33"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM16X1D" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_RAM16X1D" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="181"/> <item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="199"/>
</section> </section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY"> <section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="4"/> <item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="189"/> <item dataType="int" stringID="NGDBUILD_NUM_FD" value="191"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="99"/> <item dataType="int" stringID="NGDBUILD_NUM_FDE" value="101"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="135"/> <item dataType="int" stringID="NGDBUILD_NUM_FDR" value="135"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="313"/> <item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="325"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/> <item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="33"/> <item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
...@@ -113,23 +113,23 @@ ...@@ -113,23 +113,23 @@
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="29"/> <item dataType="int" stringID="NGDBUILD_NUM_INV" value="29"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="163"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="181"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="163"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="166"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="121"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="130"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="112"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="113"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="148"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="146"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="299"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="204"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="65"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="65"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFTDS" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUFTDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="181"/> <item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="199"/>
</section> </section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY"> <section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/> <section stringID="NGDBUILD_CORE_INSTANCES"/>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.csv
View file @ 265c6bd0
#Release 12.3 - par M.70d (nt64) #Release 12.3 - par M.70d (nt64)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. #Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Fri Dec 17 11:12:54 2010 #Mon Dec 20 08:27:29 2010
# #
## NOTE: This file is designed to be imported into a spreadsheet program ## NOTE: This file is designed to be imported into a spreadsheet program
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.txt
View file @ 265c6bd0
Release 12.3 - par M.70d (nt64) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 11:12:54 2010 Mon Dec 20 08:27:29 2010
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_par.xrpt
View file @ 265c6bd0
...@@ -5,14 +5,14 @@ ...@@ -5,14 +5,14 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Fri Dec 17 11:12:31 2010"> <application stringID="par" timeStamp="Mon Dec 20 08:27:07 2010">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
<column stringID="value"/> <column stringID="value"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="variable" value="Path"/> <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row> </row>
<row stringID="row" value="1"> <row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/> <item stringID="variable" value="PATHEXT"/>
...@@ -59,12 +59,12 @@ ...@@ -59,12 +59,12 @@
</task> </task>
<task stringID="PAR_PAR"> <task stringID="PAR_PAR">
<section stringID="PAR_DESIGN_SUMMARY"> <section stringID="PAR_DESIGN_SUMMARY">
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="30 secs "/> <item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="29 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="29 secs "/> <item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="28 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/> <item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/> <item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="32 secs "/> <item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="31 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="32 secs "/> <item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="31 secs "/>
</section> </section>
</task> </task>
<task stringID="PAR_par"> <task stringID="PAR_par">
...@@ -83,9 +83,9 @@ ...@@ -83,9 +83,9 @@
<item label="Routed" stringID="ROUTED" value="ROUTED"/> <item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y4"/> <item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y4"/>
<item label="Locked" stringID="LOCKED" value="No"/> <item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="229.000000"/> <item dataType="float" label="Fanout" stringID="FANOUT" value="220.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.260000"/> <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.242000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.710000"/> <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.696000"/>
</row> </row>
<row stringID="row" value="2"> <row stringID="row" value="2">
<item label="Clock Net" stringID="CLOCK_NET" value="VmeSysClk_ik_BUFGP"/> <item label="Clock Net" stringID="CLOCK_NET" value="VmeSysClk_ik_BUFGP"/>
...@@ -93,8 +93,8 @@ ...@@ -93,8 +93,8 @@
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y9"/> <item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y9"/>
<item label="Locked" stringID="LOCKED" value="No"/> <item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="6.000000"/> <item dataType="float" label="Fanout" stringID="FANOUT" value="6.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.009000"/> <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.008000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.640000"/> <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.643000"/>
</row> </row>
<row stringID="row" value="3"> <row stringID="row" value="3">
<item label="Clock Net" stringID="CLOCK_NET" value="VcTcXo_ik_BUFGP"/> <item label="Clock Net" stringID="CLOCK_NET" value="VcTcXo_ik_BUFGP"/>
...@@ -111,16 +111,16 @@ ...@@ -111,16 +111,16 @@
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y14"/> <item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y14"/>
<item label="Locked" stringID="LOCKED" value="No"/> <item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="16.000000"/> <item dataType="float" label="Fanout" stringID="FANOUT" value="16.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.186000"/> <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.189000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.693000"/> <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.693000"/>
</row> </row>
<row stringID="row" value="5"> <row stringID="row" value="5">
<item label="Clock Net" stringID="CLOCK_NET" value="i_Core/Rst_rq"/> <item label="Clock Net" stringID="CLOCK_NET" value="i_Core/Rst_rq"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/> <item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="Local"/> <item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="223.000000"/> <item dataType="float" label="Fanout" stringID="FANOUT" value="211.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/> <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="7.868000"/> <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="3.873000"/>
</row> </row>
<row stringID="row" value="6"> <row stringID="row" value="6">
<item label="Clock Net" stringID="CLOCK_NET" value="i_Core/i_VmeInterface/stb_o"/> <item label="Clock Net" stringID="CLOCK_NET" value="i_Core/i_VmeInterface/stb_o"/>
...@@ -128,7 +128,7 @@ ...@@ -128,7 +128,7 @@
<item label="Resource" stringID="RESOURCE" value="Local"/> <item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="19.000000"/> <item dataType="float" label="Fanout" stringID="FANOUT" value="19.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/> <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="4.686000"/> <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="4.113000"/>
</row> </row>
</table> </table>
</section> </section>
...@@ -6281,14 +6281,14 @@ ...@@ -6281,14 +6281,14 @@
</task> </task>
</application> </application>
<application stringID="Par" timeStamp="Fri Dec 17 11:12:31 2010"> <application stringID="Par" timeStamp="Mon Dec 20 08:27:07 2010">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
<column stringID="value"/> <column stringID="value"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="variable" value="Path"/> <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row> </row>
<row stringID="row" value="1"> <row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/> <item stringID="variable" value="PATHEXT"/>
...@@ -6327,15 +6327,15 @@ ...@@ -6327,15 +6327,15 @@
</section> </section>
<task label="Device Utilization Summary" stringID="PAR_DEVICE_UTLIZATION"> <task label="Device Utilization Summary" stringID="PAR_DEVICE_UTLIZATION">
<section stringID="PAR_SLICE_REPORTING"> <section stringID="PAR_SLICE_REPORTING">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="796"> <item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="812">
<item dataType="int" stringID="PAR_NUM_SLICE_FF" value="796"/> <item dataType="int" stringID="PAR_NUM_SLICE_FF" value="812"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCH" value="0"/> <item dataType="int" stringID="PAR_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/> <item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/> <item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/>
</item> </item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="934"> <item AVAILABLE="92152" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="954">
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="154"/> <item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="172"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="571"/> <item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="573"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="166"/> <item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="166"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ONLY" value="0"/> <item dataType="int" stringID="PAR_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O6ONLY" value="0"/> <item dataType="int" stringID="PAR_NUM_ROM_O6ONLY" value="0"/>
...@@ -6347,24 +6347,24 @@ ...@@ -6347,24 +6347,24 @@
<item dataType="int" stringID="PAR_NUM_SPRAM_O6ONLY" value="0"/> <item dataType="int" stringID="PAR_NUM_SPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_SPRAM_O5ANDO6" value="0"/> <item dataType="int" stringID="PAR_NUM_SPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="PAR_NUM_SRL_O5ONLY" value="0"/> <item dataType="int" stringID="PAR_NUM_SRL_O5ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_SRL_O6ONLY" value="3"/> <item dataType="int" stringID="PAR_NUM_SRL_O6ONLY" value="5"/>
<item dataType="int" stringID="PAR_NUM_SRL_O5ANDO6" value="0"/> <item dataType="int" stringID="PAR_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO6" value="9"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_EXO6" value="9"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="23"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="21"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_O5ANDO6" value="0"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="23"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="21"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="9"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="9"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/> <item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item> </item>
<item AVAILABLE="23038" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="374"> <item AVAILABLE="23038" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="365">
<item AVAILABLE="6099" dataType="int" stringID="PAR_NUM_SLICEL" value="70"/> <item AVAILABLE="6099" dataType="int" stringID="PAR_NUM_SLICEL" value="84"/>
<item AVAILABLE="5420" dataType="int" stringID="PAR_NUM_SLICEM" value="4"/> <item AVAILABLE="5420" dataType="int" stringID="PAR_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="PAR_NUM_SLICEX" value="300"/> <item AVAILABLE="11519" dataType="int" stringID="PAR_NUM_SLICEX" value="277"/>
</item> </item>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="1101"> <item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="1098">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="386"/> <item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="364"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="167"/> <item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="144"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="548"/> <item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="590"/>
</item> </item>
</section> </section>
<section stringID="PAR_IOB_REPORTING"> <section stringID="PAR_IOB_REPORTING">
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.html
View file @ 265c6bd0
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>SFpga Project Status (12/17/2010 - 11:13:37)</B></TD></TR> <TD ALIGN=CENTER COLSPAN='4'><B>SFpga Project Status (12/15/2010 - 15:17:10)</B></TD></TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>SystemFpga.xise</TD> <TD>SystemFpga.xise</TD>
...@@ -25,7 +25,7 @@ No Errors</TD> ...@@ -25,7 +25,7 @@ No Errors</TD>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD> <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/*.xmsgs?&DataKey=Warning'>319 Warnings (0 new)</A></TD> <TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/*.xmsgs?&DataKey=Warning'>319 Warnings (2 new)</A></TD>
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
...@@ -60,13 +60,13 @@ System Settings</A> ...@@ -60,13 +60,13 @@ System Settings</A>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD> <TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>796</TD> <TD ALIGN=RIGHT>812</TD>
<TD ALIGN=RIGHT>184,304</TD> <TD ALIGN=RIGHT>184,304</TD>
<TD ALIGN=RIGHT>1%</TD> <TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>796</TD> <TD ALIGN=RIGHT>812</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
...@@ -90,25 +90,25 @@ System Settings</A> ...@@ -90,25 +90,25 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>934</TD> <TD ALIGN=RIGHT>954</TD>
<TD ALIGN=RIGHT>92,152</TD> <TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>1%</TD> <TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>891</TD> <TD ALIGN=RIGHT>911</TD>
<TD ALIGN=RIGHT>92,152</TD> <TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>1%</TD> <TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>571</TD> <TD ALIGN=RIGHT>573</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>154</TD> <TD ALIGN=RIGHT>172</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
...@@ -126,7 +126,7 @@ System Settings</A> ...@@ -126,7 +126,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
<TD ALIGN=RIGHT>11</TD> <TD ALIGN=RIGHT>13</TD>
<TD ALIGN=RIGHT>21,680</TD> <TD ALIGN=RIGHT>21,680</TD>
<TD ALIGN=RIGHT>1%</TD> <TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
...@@ -162,13 +162,13 @@ System Settings</A> ...@@ -162,13 +162,13 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Shift Register</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Shift Register</TD>
<TD ALIGN=RIGHT>3</TD> <TD ALIGN=RIGHT>5</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>3</TD> <TD ALIGN=RIGHT>5</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
...@@ -186,13 +186,13 @@ System Settings</A> ...@@ -186,13 +186,13 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
<TD ALIGN=RIGHT>32</TD> <TD ALIGN=RIGHT>30</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
<TD ALIGN=RIGHT>23</TD> <TD ALIGN=RIGHT>21</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
...@@ -210,33 +210,33 @@ System Settings</A> ...@@ -210,33 +210,33 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>374</TD> <TD ALIGN=RIGHT>365</TD>
<TD ALIGN=RIGHT>23,038</TD> <TD ALIGN=RIGHT>23,038</TD>
<TD ALIGN=RIGHT>1%</TD> <TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>1,101</TD> <TD ALIGN=RIGHT>1,098</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>386</TD> <TD ALIGN=RIGHT>364</TD>
<TD ALIGN=RIGHT>1,101</TD> <TD ALIGN=RIGHT>1,098</TD>
<TD ALIGN=RIGHT>35%</TD> <TD ALIGN=RIGHT>33%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>167</TD> <TD ALIGN=RIGHT>144</TD>
<TD ALIGN=RIGHT>1,101</TD> <TD ALIGN=RIGHT>1,098</TD>
<TD ALIGN=RIGHT>15%</TD> <TD ALIGN=RIGHT>13%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>548</TD> <TD ALIGN=RIGHT>590</TD>
<TD ALIGN=RIGHT>1,101</TD> <TD ALIGN=RIGHT>1,098</TD>
<TD ALIGN=RIGHT>49%</TD> <TD ALIGN=RIGHT>53%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
...@@ -246,7 +246,7 @@ System Settings</A> ...@@ -246,7 +246,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
<TD ALIGN=RIGHT>85</TD> <TD ALIGN=RIGHT>83</TD>
<TD ALIGN=RIGHT>184,304</TD> <TD ALIGN=RIGHT>184,304</TD>
<TD ALIGN=RIGHT>1%</TD> <TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
...@@ -426,7 +426,7 @@ System Settings</A> ...@@ -426,7 +426,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>3.02</TD> <TD ALIGN=RIGHT>3.01</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
...@@ -463,23 +463,23 @@ System Settings</A> ...@@ -463,23 +463,23 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri 17. Dec 11:11:16 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>126 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Info'>12 Infos (0 new)</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 08:25:30 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>126 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Info'>12 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri 17. Dec 11:11:23 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>14 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 08:25:41 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>14 Warnings (2 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri 17. Dec 11:12:20 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Warning'>83 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (1 new)</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 08:26:54 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Warning'>83 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (2 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri 17. Dec 11:12:55 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/par.xmsgs?&DataKey=Warning'>49 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 08:27:30 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/par.xmsgs?&DataKey=Warning'>49 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR> <TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Fri 17. Dec 11:13:07 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/trce.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 08:27:42 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/trce.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Fri 17. Dec 11:13:31 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>47 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Mon 20. Dec 08:28:06 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>47 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE> </TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu 16. Dec 17:57:34 2010</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu 16. Dec 17:57:34 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.ibs'>IBIS Model</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed 15. Dec 15:16:36 2010</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.ibs'>IBIS Model</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed 15. Dec 15:16:36 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri 17. Dec 11:13:31 2010</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon 20. Dec 08:28:06 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri 17. Dec 11:13:36 2010</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon 20. Dec 08:28:11 2010</TD></TR>
</TABLE> </TABLE>
<br><center><b>Date Generated:</b> 12/17/2010 - 11:13:37</center> <br><center><b>Date Generated:</b> 12/20/2010 - 09:29:22</center>
</BODY></HTML> </BODY></HTML>
\ No newline at end of file
trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.xml
View file @ 265c6bd0
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<DesignSummary rev="15"> <DesignSummary rev="17">
<CmdHistory> <CmdHistory>
</CmdHistory> </CmdHistory>
</DesignSummary> </DesignSummary>
trunk/firmware/XilinxISE/SystemFpga/SFpga_usage.xml
View file @ 265c6bd0
...@@ -4,798 +4,806 @@ ...@@ -4,798 +4,806 @@
changes made to this file may result in unpredictable changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<DeviceUsageSummary rev="15"> <DeviceUsageSummary rev="17">
<DesignStatistics TimeStamp="Fri Dec 17 11:13:31 2010"><group name="NetStatistics"> <DesignStatistics TimeStamp="Mon Dec 20 08:28:05 2010"><group name="NetStatistics">
<item name="NumNets_Active" rev="15"> <item name="NumNets_Active" rev="17">
<attrib name="value" value="1863"/></item> <attrib name="value" value="1875"/></item>
<item name="NumNets_Gnd" rev="15"> <item name="NumNets_Gnd" rev="17">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
<item name="NumNets_Vcc" rev="15"> <item name="NumNets_Vcc" rev="17">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="15"> <item name="NumNodesOfType_Active_BOUNCEACROSS" rev="17">
<attrib name="value" value="30"/></item> <attrib name="value" value="31"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="15"> <item name="NumNodesOfType_Active_BOUNCEIN" rev="17">
<attrib name="value" value="225"/></item> <attrib name="value" value="197"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="15"> <item name="NumNodesOfType_Active_BUFGOUT" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="15"> <item name="NumNodesOfType_Active_BUFHINP2OUT" rev="17">
<attrib name="value" value="17"/></item> <attrib name="value" value="14"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="15"> <item name="NumNodesOfType_Active_CLKPIN" rev="17">
<attrib name="value" value="259"/></item> <attrib name="value" value="250"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="15"> <item name="NumNodesOfType_Active_CLKPINFEED" rev="17">
<attrib name="value" value="21"/></item> <attrib name="value" value="18"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="15"> <item name="NumNodesOfType_Active_CNTRLPIN" rev="17">
<attrib name="value" value="310"/></item> <attrib name="value" value="307"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="15"> <item name="NumNodesOfType_Active_DOUBLE" rev="17">
<attrib name="value" value="2002"/></item> <attrib name="value" value="1931"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="15"> <item name="NumNodesOfType_Active_GENERIC" rev="17">
<attrib name="value" value="358"/></item> <attrib name="value" value="358"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="15"> <item name="NumNodesOfType_Active_GLOBAL" rev="17">
<attrib name="value" value="146"/></item> <attrib name="value" value="129"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="15"> <item name="NumNodesOfType_Active_INPUT" rev="17">
<attrib name="value" value="50"/></item> <attrib name="value" value="56"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="15"> <item name="NumNodesOfType_Active_IOBIN2OUT" rev="17">
<attrib name="value" value="245"/></item> <attrib name="value" value="245"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="15"> <item name="NumNodesOfType_Active_IOBOUTPUT" rev="17">
<attrib name="value" value="245"/></item> <attrib name="value" value="245"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="15"> <item name="NumNodesOfType_Active_LUTINPUT" rev="17">
<attrib name="value" value="3702"/></item> <attrib name="value" value="3703"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="15"> <item name="NumNodesOfType_Active_OUTBOUND" rev="17">
<attrib name="value" value="1554"/></item> <attrib name="value" value="1566"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="15"> <item name="NumNodesOfType_Active_OUTPUT" rev="17">
<attrib name="value" value="1413"/></item> <attrib name="value" value="1430"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="15"> <item name="NumNodesOfType_Active_PADINPUT" rev="17">
<attrib name="value" value="137"/></item> <attrib name="value" value="137"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="15"> <item name="NumNodesOfType_Active_PADOUTPUT" rev="17">
<attrib name="value" value="116"/></item> <attrib name="value" value="116"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="15"> <item name="NumNodesOfType_Active_PINBOUNCE" rev="17">
<attrib name="value" value="814"/></item> <attrib name="value" value="813"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="15"> <item name="NumNodesOfType_Active_PINFEED" rev="17">
<attrib name="value" value="4282"/></item> <attrib name="value" value="4267"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="15"> <item name="NumNodesOfType_Active_QUAD" rev="17">
<attrib name="value" value="5514"/></item> <attrib name="value" value="5506"/></item>
<item name="NumNodesOfType_Active_REGINPUT" rev="15"> <item name="NumNodesOfType_Active_REGINPUT" rev="17">
<attrib name="value" value="282"/></item> <attrib name="value" value="280"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="15"> <item name="NumNodesOfType_Active_SINGLE" rev="17">
<attrib name="value" value="2320"/></item> <attrib name="value" value="2294"/></item>
<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="15"> <item name="NumNodesOfType_Vcc_CNTRLPIN" rev="17">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_GENERIC" rev="15"> <item name="NumNodesOfType_Vcc_GENERIC" rev="17">
<attrib name="value" value="13"/></item> <attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="15"> <item name="NumNodesOfType_Vcc_HVCCOUT" rev="17">
<attrib name="value" value="136"/></item> <attrib name="value" value="141"/></item>
<item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="15"> <item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="17">
<attrib name="value" value="13"/></item> <attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_IOBOUTPUT" rev="15"> <item name="NumNodesOfType_Vcc_IOBOUTPUT" rev="17">
<attrib name="value" value="13"/></item> <attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_KVCCOUT" rev="15"> <item name="NumNodesOfType_Vcc_KVCCOUT" rev="17">
<attrib name="value" value="6"/></item> <attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="15"> <item name="NumNodesOfType_Vcc_LUTINPUT" rev="17">
<attrib name="value" value="340"/></item> <attrib name="value" value="370"/></item>
<item name="NumNodesOfType_Vcc_PADINPUT" rev="15"> <item name="NumNodesOfType_Vcc_PADINPUT" rev="17">
<attrib name="value" value="13"/></item> <attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_PINBOUNCE" rev="15"> <item name="NumNodesOfType_Vcc_PINBOUNCE" rev="17">
<attrib name="value" value="13"/></item> <attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="15"> <item name="NumNodesOfType_Vcc_PINFEED" rev="17">
<attrib name="value" value="353"/></item> <attrib name="value" value="383"/></item>
<item name="NumNodesOfType_Vcc_REGINPUT" rev="15"> <item name="NumNodesOfType_Vcc_REGINPUT" rev="17">
<attrib name="value" value="11"/></item> <attrib name="value" value="11"/></item>
</group> </group>
<group name="SiteStatistics"> <group name="SiteStatistics">
<item name="BUFG-BUFGMUX" rev="15"> <item name="BUFG-BUFGMUX" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="IOB-IOBM" rev="15"> <item name="IOB-IOBM" rev="17">
<attrib name="value" value="161"/></item> <attrib name="value" value="161"/></item>
<item name="IOB-IOBS" rev="15"> <item name="IOB-IOBS" rev="17">
<attrib name="value" value="165"/></item> <attrib name="value" value="165"/></item>
<item name="SLICEL-SLICEM" rev="15"> <item name="SLICEL-SLICEM" rev="17">
<attrib name="value" value="25"/></item> <attrib name="value" value="44"/></item>
<item name="SLICEX-SLICEL" rev="15"> <item name="SLICEX-SLICEL" rev="17">
<attrib name="value" value="73"/></item> <attrib name="value" value="55"/></item>
<item name="SLICEX-SLICEM" rev="15"> <item name="SLICEX-SLICEM" rev="17">
<attrib name="value" value="63"/></item> <attrib name="value" value="64"/></item>
</group> </group>
<group name="MiscellaneousStatistics"> <group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="14"> <item name="AGG_BONDED_IO" rev="16">
<attrib name="value" value="330"/></item> <attrib name="value" value="330"/></item>
<item name="AGG_IO" rev="14"> <item name="AGG_IO" rev="16">
<attrib name="value" value="330"/></item> <attrib name="value" value="330"/></item>
<item name="AGG_LOCED_IO" rev="14"> <item name="AGG_LOCED_IO" rev="16">
<attrib name="value" value="328"/></item> <attrib name="value" value="328"/></item>
<item name="AGG_SLICE" rev="14"> <item name="AGG_SLICE" rev="16">
<attrib name="value" value="374"/></item> <attrib name="value" value="365"/></item>
<item name="NUM_BONDED_IOB" rev="14"> <item name="NUM_BONDED_IOB" rev="16">
<attrib name="value" value="326"/></item> <attrib name="value" value="326"/></item>
<item name="NUM_BONDED_IOBM" rev="14"> <item name="NUM_BONDED_IOBM" rev="16">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="NUM_BONDED_IOBS" rev="14"> <item name="NUM_BONDED_IOBS" rev="16">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="NUM_BSFULL" rev="14"> <item name="NUM_BSFULL" rev="16">
<attrib name="value" value="548"/></item> <attrib name="value" value="590"/></item>
<item name="NUM_BSLUTONLY" rev="14"> <item name="NUM_BSLUTONLY" rev="16">
<attrib name="value" value="386"/></item> <attrib name="value" value="364"/></item>
<item name="NUM_BSREGONLY" rev="14"> <item name="NUM_BSREGONLY" rev="16">
<attrib name="value" value="167"/></item> <attrib name="value" value="144"/></item>
<item name="NUM_BSUSED" rev="14"> <item name="NUM_BSUSED" rev="16">
<attrib name="value" value="1101"/></item> <attrib name="value" value="1098"/></item>
<item name="NUM_BUFG" rev="14"> <item name="NUM_BUFG" rev="16">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="NUM_DPRAM_O5ANDO6" rev="14"> <item name="NUM_DPRAM_O5ANDO6" rev="16">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="NUM_DPRAM_O6ONLY" rev="14"> <item name="NUM_DPRAM_O6ONLY" rev="16">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="NUM_LOCED_IOB" rev="14"> <item name="NUM_LOCED_IOB" rev="16">
<attrib name="value" value="324"/></item> <attrib name="value" value="324"/></item>
<item name="NUM_LOCED_IOBM" rev="14"> <item name="NUM_LOCED_IOBM" rev="16">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="NUM_LOCED_IOBS" rev="14"> <item name="NUM_LOCED_IOBS" rev="16">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="14"> <item name="NUM_LOGIC_O5ANDO6" rev="16">
<attrib name="value" value="166"/></item> <attrib name="value" value="166"/></item>
<item name="NUM_LOGIC_O5ONLY" rev="14"> <item name="NUM_LOGIC_O5ONLY" rev="16">
<attrib name="value" value="154"/></item> <attrib name="value" value="172"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="14"> <item name="NUM_LOGIC_O6ONLY" rev="16">
<attrib name="value" value="571"/></item> <attrib name="value" value="573"/></item>
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="14"> <item name="NUM_LUT_RT_DRIVES_CARRY4" rev="16">
<attrib name="value" value="9"/></item> <attrib name="value" value="9"/></item>
<item name="NUM_LUT_RT_DRIVES_FLOP" rev="14"> <item name="NUM_LUT_RT_DRIVES_FLOP" rev="16">
<attrib name="value" value="23"/></item> <attrib name="value" value="21"/></item>
<item name="NUM_LUT_RT_EXO5" rev="14"> <item name="NUM_LUT_RT_EXO5" rev="16">
<attrib name="value" value="23"/></item> <attrib name="value" value="21"/></item>
<item name="NUM_LUT_RT_EXO6" rev="14"> <item name="NUM_LUT_RT_EXO6" rev="16">
<attrib name="value" value="9"/></item> <attrib name="value" value="9"/></item>
<item name="NUM_LUT_RT_O5" rev="14"> <item name="NUM_LUT_RT_O5" rev="16">
<attrib name="value" value="5"/></item> <attrib name="value" value="11"/></item>
<item name="NUM_LUT_RT_O6" rev="14"> <item name="NUM_LUT_RT_O6" rev="16">
<attrib name="value" value="154"/></item> <attrib name="value" value="172"/></item>
<item name="NUM_SLICEL" rev="14"> <item name="NUM_SLICEL" rev="16">
<attrib name="value" value="70"/></item> <attrib name="value" value="84"/></item>
<item name="NUM_SLICEM" rev="14"> <item name="NUM_SLICEM" rev="16">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="NUM_SLICEX" rev="14"> <item name="NUM_SLICEX" rev="16">
<attrib name="value" value="300"/></item> <attrib name="value" value="277"/></item>
<item name="NUM_SLICE_CARRY4" rev="14"> <item name="NUM_SLICE_CARRY4" rev="16">
<attrib name="value" value="52"/></item> <attrib name="value" value="56"/></item>
<item name="NUM_SLICE_CONTROLSET" rev="14"> <item name="NUM_SLICE_CONTROLSET" rev="16">
<attrib name="value" value="32"/></item> <attrib name="value" value="32"/></item>
<item name="NUM_SLICE_CYINIT" rev="14"> <item name="NUM_SLICE_CYINIT" rev="16">
<attrib name="value" value="1274"/></item> <attrib name="value" value="1318"/></item>
<item name="NUM_SLICE_F7MUX" rev="14"> <item name="NUM_SLICE_F7MUX" rev="16">
<attrib name="value" value="18"/></item> <attrib name="value" value="28"/></item>
<item name="NUM_SLICE_FF" rev="14"> <item name="NUM_SLICE_FF" rev="16">
<attrib name="value" value="796"/></item> <attrib name="value" value="812"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="14"> <item name="NUM_SLICE_UNUSEDCTRL" rev="16">
<attrib name="value" value="115"/></item> <attrib name="value" value="115"/></item>
<item name="NUM_SRL_O6ONLY" rev="14"> <item name="NUM_SRL_O6ONLY" rev="16">
<attrib name="value" value="3"/></item> <attrib name="value" value="5"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="14"> <item name="NUM_UNUSABLE_FF_BELS" rev="16">
<attrib name="value" value="85"/></item> <attrib name="value" value="83"/></item>
</group> </group>
</DesignStatistics> </DesignStatistics>
<DeviceUsage TimeStamp="Fri Dec 17 11:13:31 2010"><group name="SiteSummary"> <DeviceUsage TimeStamp="Mon Dec 20 08:28:05 2010"><group name="SiteSummary">
<item name="BUFG" rev="15"> <item name="BUFG" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="BUFG_BUFG" rev="15"> <item name="BUFG_BUFG" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="CARRY4" rev="15"> <item name="CARRY4" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="52"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="56"/></item>
<item name="FF_SR" rev="15"> <item name="FF_SR" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="89"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="86"/></item>
<item name="HARD0" rev="15"> <item name="HARD0" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="11"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="11"/></item>
<item name="IOB" rev="15"> <item name="IOB" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="326"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="326"/></item>
<item name="IOBM" rev="15"> <item name="IOBM" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOBM_OUTBUF" rev="15"> <item name="IOBM_OUTBUF" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOBS" rev="15"> <item name="IOBS" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOB_IMUX" rev="15"> <item name="IOB_IMUX" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="159"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="159"/></item>
<item name="IOB_INBUF" rev="15"> <item name="IOB_INBUF" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="159"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="159"/></item>
<item name="IOB_OUTBUF" rev="15"> <item name="IOB_OUTBUF" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="198"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="198"/></item>
<item name="LUT5" rev="15"> <item name="LUT5" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="348"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="370"/></item>
<item name="LUT6" rev="15"> <item name="LUT6" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="900"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="919"/></item>
<item name="LUT_OR_MEM5" rev="15"> <item name="LUT_OR_MEM5" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="LUT_OR_MEM6" rev="15"> <item name="LUT_OR_MEM6" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="11"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="NULLMUX" rev="15"> <item name="NULLMUX" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="PAD" rev="15"> <item name="PAD" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="330"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="330"/></item>
<item name="REG_SR" rev="15"> <item name="REG_SR" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="707"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="726"/></item>
<item name="SELMUX2_1" rev="15"> <item name="SELMUX2_1" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="28"/></item>
<item name="SLICEL" rev="15"> <item name="SLICEL" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="70"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="84"/></item>
<item name="SLICEM" rev="15"> <item name="SLICEM" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="SLICEX" rev="15"> <item name="SLICEX" rev="17">
<attrib name="total" value="1000000"/><attrib name="used" value="300"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="277"/></item>
</group> </group>
</DeviceUsage> </DeviceUsage>
<ReportConfigData TimeStamp="Fri Dec 17 11:13:31 2010"><group name="REG_SR"> <ReportConfigData TimeStamp="Mon Dec 20 08:28:05 2010"><group name="REG_SR">
<item name="CK" rev="15"> <item name="CK" rev="17">
<attrib name="CK" value="707"/><attrib name="CK_INV" value="0"/></item> <attrib name="CK" value="726"/><attrib name="CK_INV" value="0"/></item>
<item name="LATCH_OR_FF" rev="15"> <item name="LATCH_OR_FF" rev="17">
<attrib name="FF" value="707"/></item> <attrib name="FF" value="726"/></item>
<item name="SRINIT" rev="15"> <item name="SRINIT" rev="17">
<attrib name="SRINIT0" value="655"/><attrib name="SRINIT1" value="52"/></item> <attrib name="SRINIT0" value="674"/><attrib name="SRINIT1" value="52"/></item>
<item name="SYNC_ATTR" rev="15"> <item name="SYNC_ATTR" rev="17">
<attrib name="ASYNC" value="240"/><attrib name="SYNC" value="467"/></item> <attrib name="ASYNC" value="240"/><attrib name="SYNC" value="486"/></item>
</group> </group>
<group name="LUT_OR_MEM5"> <group name="LUT_OR_MEM5">
<item name="CLK" rev="15"> <item name="CLK" rev="17">
<attrib name="CLK" value="4"/><attrib name="CLK_INV" value="0"/></item> <attrib name="CLK" value="4"/><attrib name="CLK_INV" value="0"/></item>
<item name="LUT_OR_MEM" rev="15"> <item name="LUT_OR_MEM" rev="17">
<attrib name="RAM" value="4"/></item> <attrib name="RAM" value="4"/></item>
<item name="RAMMODE" rev="15"> <item name="RAMMODE" rev="17">
<attrib name="DPRAM32" value="4"/></item> <attrib name="DPRAM32" value="4"/></item>
</group> </group>
<group name="LUT_OR_MEM6"> <group name="LUT_OR_MEM6">
<item name="CLK" rev="15"> <item name="CLK" rev="17">
<attrib name="CLK" value="11"/><attrib name="CLK_INV" value="0"/></item> <attrib name="CLK" value="13"/><attrib name="CLK_INV" value="0"/></item>
<item name="LUT_OR_MEM" rev="15"> <item name="LUT_OR_MEM" rev="17">
<attrib name="RAM" value="11"/></item> <attrib name="LUT" value="1"/><attrib name="RAM" value="13"/></item>
<item name="RAMMODE" rev="15"> <item name="RAMMODE" rev="17">
<attrib name="SRL16" value="3"/><attrib name="DPRAM32" value="4"/><attrib name="DPRAM64" value="4"/></item> <attrib name="SRL16" value="5"/><attrib name="DPRAM32" value="4"/><attrib name="DPRAM64" value="4"/></item>
</group> </group>
<group name="IOBM_OUTBUF"> <group name="IOBM_OUTBUF">
<item name="SUSPEND" rev="15"> <item name="SUSPEND" rev="17">
<attrib name="3STATE" value="2"/></item> <attrib name="3STATE" value="2"/></item>
</group> </group>
<group name="SLICEL"> <group name="SLICEL">
<item name="CLK" rev="15"> <item name="CLK" rev="17">
<attrib name="CLK" value="37"/><attrib name="CLK_INV" value="0"/></item> <attrib name="CLK" value="51"/><attrib name="CLK_INV" value="0"/></item>
</group> </group>
<group name="SLICEM"> <group name="SLICEM">
<item name="CLK" rev="15"> <item name="CLK" rev="17">
<attrib name="CLK" value="4"/><attrib name="CLK_INV" value="0"/></item> <attrib name="CLK" value="4"/><attrib name="CLK_INV" value="0"/></item>
</group> </group>
<group name="IOB_OUTBUF"> <group name="IOB_OUTBUF">
<item name="DRIVEATTRBOX" rev="15"> <item name="DRIVEATTRBOX" rev="17">
<attrib name="12" value="167"/></item> <attrib name="12" value="167"/></item>
<item name="SLEW" rev="15"> <item name="SLEW" rev="17">
<attrib name="SLOW" value="167"/></item> <attrib name="SLOW" value="167"/></item>
<item name="SUSPEND" rev="15"> <item name="SUSPEND" rev="17">
<attrib name="3STATE" value="198"/></item> <attrib name="3STATE" value="198"/></item>
</group> </group>
<group name="SLICEX"> <group name="SLICEX">
<item name="CLK" rev="15"> <item name="CLK" rev="17">
<attrib name="CLK" value="218"/><attrib name="CLK_INV" value="0"/></item> <attrib name="CLK" value="195"/><attrib name="CLK_INV" value="0"/></item>
</group> </group>
<group name="IOB_INBUF"> <group name="IOB_INBUF">
<item name="DIFF_TERM" rev="15"> <item name="DIFF_TERM" rev="17">
<attrib name="TRUE" value="1"/></item> <attrib name="TRUE" value="1"/></item>
</group> </group>
<group name="FF_SR"> <group name="FF_SR">
<item name="CK" rev="15"> <item name="CK" rev="17">
<attrib name="CK" value="89"/><attrib name="CK_INV" value="0"/></item> <attrib name="CK" value="86"/><attrib name="CK_INV" value="0"/></item>
<item name="SRINIT" rev="15"> <item name="SRINIT" rev="17">
<attrib name="SRINIT0" value="78"/><attrib name="SRINIT1" value="11"/></item> <attrib name="SRINIT0" value="75"/><attrib name="SRINIT1" value="11"/></item>
<item name="SYNC_ATTR" rev="15"> <item name="SYNC_ATTR" rev="17">
<attrib name="ASYNC" value="49"/><attrib name="SYNC" value="40"/></item> <attrib name="ASYNC" value="53"/><attrib name="SYNC" value="33"/></item>
</group> </group>
</ReportConfigData> </ReportConfigData>
<ReportPinData TimeStamp="Fri Dec 17 11:13:31 2010"><group name="NULLMUX"> <ReportPinData TimeStamp="Mon Dec 20 08:28:05 2010"><group name="NULLMUX">
<item name="0" rev="15"> <item name="0" rev="17">
<attrib name="value" value="3"/></item> <attrib name="value" value="3"/></item>
<item name="OUT" rev="15"> <item name="OUT" rev="17">
<attrib name="value" value="3"/></item> <attrib name="value" value="3"/></item>
</group> </group>
<group name="REG_SR"> <group name="REG_SR">
<item name="CE" rev="15"> <item name="CE" rev="17">
<attrib name="value" value="389"/></item> <attrib name="value" value="404"/></item>
<item name="CK" rev="15"> <item name="CK" rev="17">
<attrib name="value" value="707"/></item> <attrib name="value" value="726"/></item>
<item name="D" rev="15"> <item name="D" rev="17">
<attrib name="value" value="707"/></item> <attrib name="value" value="726"/></item>
<item name="Q" rev="15"> <item name="Q" rev="17">
<attrib name="value" value="707"/></item> <attrib name="value" value="726"/></item>
<item name="SR" rev="15"> <item name="SR" rev="17">
<attrib name="value" value="468"/></item> <attrib name="value" value="487"/></item>
</group> </group>
<group name="LUT_OR_MEM5"> <group name="LUT_OR_MEM5">
<item name="A1" rev="15"> <item name="A1" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="A2" rev="15"> <item name="A2" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="A3" rev="15"> <item name="A3" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="A4" rev="15"> <item name="A4" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="A5" rev="15"> <item name="A5" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="CLK" rev="15"> <item name="CLK" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="DI1" rev="15"> <item name="DI1" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="O5" rev="15"> <item name="O5" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="WA1" rev="15"> <item name="WA1" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="WA2" rev="15"> <item name="WA2" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="WA3" rev="15"> <item name="WA3" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="WA4" rev="15"> <item name="WA4" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="WA5" rev="15"> <item name="WA5" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="WE" rev="15"> <item name="WE" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
</group> </group>
<group name="LUT_OR_MEM6"> <group name="LUT_OR_MEM6">
<item name="A1" rev="15"> <item name="A1" rev="17">
<attrib name="value" value="11"/></item> <attrib name="value" value="13"/></item>
<item name="A2" rev="15"> <item name="A2" rev="17">
<attrib name="value" value="11"/></item> <attrib name="value" value="13"/></item>
<item name="A3" rev="15"> <item name="A3" rev="17">
<attrib name="value" value="11"/></item> <attrib name="value" value="13"/></item>
<item name="A4" rev="15"> <item name="A4" rev="17">
<attrib name="value" value="11"/></item> <attrib name="value" value="14"/></item>
<item name="A5" rev="15"> <item name="A5" rev="17">
<attrib name="value" value="11"/></item> <attrib name="value" value="13"/></item>
<item name="A6" rev="15"> <item name="A6" rev="17">
<attrib name="value" value="11"/></item> <attrib name="value" value="14"/></item>
<item name="CLK" rev="15"> <item name="CLK" rev="17">
<attrib name="value" value="11"/></item> <attrib name="value" value="13"/></item>
<item name="DI1" rev="15"> <item name="DI1" rev="17">
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<item name="DI2" rev="15"> <item name="DI2" rev="17">
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<item name="O6" rev="15"> <item name="O6" rev="17">
<attrib name="value" value="8"/></item> <attrib name="value" value="11"/></item>
<item name="WA1" rev="15"> <item name="WA1" rev="17">
<attrib name="value" value="8"/></item> <attrib name="value" value="8"/></item>
<item name="WA2" rev="15"> <item name="WA2" rev="17">
<attrib name="value" value="8"/></item> <attrib name="value" value="8"/></item>
<item name="WA3" rev="15"> <item name="WA3" rev="17">
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<item name="WA4" rev="15"> <item name="WA4" rev="17">
<attrib name="value" value="8"/></item> <attrib name="value" value="8"/></item>
<item name="WA5" rev="15"> <item name="WA5" rev="17">
<attrib name="value" value="8"/></item> <attrib name="value" value="8"/></item>
<item name="WA6" rev="15"> <item name="WA6" rev="17">
<attrib name="value" value="8"/></item> <attrib name="value" value="8"/></item>
<item name="WE" rev="15"> <item name="WE" rev="17">
<attrib name="value" value="11"/></item> <attrib name="value" value="13"/></item>
</group> </group>
<group name="IOBM_OUTBUF"> <group name="IOBM_OUTBUF">
<item name="IN" rev="15"> <item name="IN" rev="17">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="OUT" rev="15"> <item name="OUT" rev="17">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="OUTN" rev="15"> <item name="OUTN" rev="17">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
</group> </group>
<group name="SLICEL"> <group name="SLICEL">
<item name="A" rev="15"> <item name="A" rev="17">
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<item name="A1" rev="15"> <item name="A1" rev="17">
<attrib name="value" value="11"/></item> <attrib name="value" value="13"/></item>
<item name="A2" rev="15"> <item name="A2" rev="17">
<attrib name="value" value="11"/></item> <attrib name="value" value="17"/></item>
<item name="A3" rev="15"> <item name="A3" rev="17">
<attrib name="value" value="14"/></item> <attrib name="value" value="20"/></item>
<item name="A4" rev="15"> <item name="A4" rev="17">
<attrib name="value" value="48"/></item> <attrib name="value" value="58"/></item>
<item name="A5" rev="15"> <item name="A5" rev="17">
<attrib name="value" value="29"/></item> <attrib name="value" value="34"/></item>
<item name="A6" rev="15"> <item name="A6" rev="17">
<attrib name="value" value="61"/></item> <attrib name="value" value="71"/></item>
<item name="AMUX" rev="15"> <item name="AMUX" rev="17">
<attrib name="value" value="19"/></item> <attrib name="value" value="18"/></item>
<item name="AQ" rev="15"> <item name="AQ" rev="17">
<attrib name="value" value="37"/></item>
<item name="AX" rev="15">
<attrib name="value" value="8"/></item>
<item name="B" rev="15">
<attrib name="value" value="9"/></item>
<item name="B1" rev="15">
<attrib name="value" value="8"/></item>
<item name="B2" rev="15">
<attrib name="value" value="9"/></item>
<item name="B3" rev="15">
<attrib name="value" value="12"/></item>
<item name="B4" rev="15">
<attrib name="value" value="47"/></item> <attrib name="value" value="47"/></item>
<item name="B5" rev="15"> <item name="AX" rev="17">
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<item name="S0" rev="15"> <item name="S2" rev="17">
<attrib name="value" value="52"/></item> <attrib name="value" value="52"/></item>
<item name="S1" rev="15"> <item name="S3" rev="17">
<attrib name="value" value="51"/></item> <attrib name="value" value="51"/></item>
<item name="S2" rev="15">
<attrib name="value" value="47"/></item>
<item name="S3" rev="15">
<attrib name="value" value="46"/></item>
</group> </group>
<group name="IOBS"> <group name="IOBS">
<item name="DIFFO_IN" rev="15"> <item name="DIFFO_IN" rev="17">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="PAD" rev="15"> <item name="PAD" rev="17">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
</group> </group>
<group name="LUT5"> <group name="LUT5">
<item name="A1" rev="15"> <item name="A1" rev="17">
<attrib name="value" value="47"/></item>
<item name="A2" rev="15">
<attrib name="value" value="48"/></item> <attrib name="value" value="48"/></item>
<item name="A3" rev="15"> <item name="A2" rev="17">
<attrib name="value" value="50"/></item>
<item name="A3" rev="17">
<attrib name="value" value="125"/></item> <attrib name="value" value="125"/></item>
<item name="A4" rev="15"> <item name="A4" rev="17">
<attrib name="value" value="130"/></item> <attrib name="value" value="130"/></item>
<item name="A5" rev="15"> <item name="A5" rev="17">
<attrib name="value" value="80"/></item> <attrib name="value" value="81"/></item>
<item name="O5" rev="15"> <item name="O5" rev="17">
<attrib name="value" value="348"/></item> <attrib name="value" value="370"/></item>
</group> </group>
<group name="LUT6"> <group name="LUT6">
<item name="A1" rev="15"> <item name="A1" rev="17">
<attrib name="value" value="311"/></item> <attrib name="value" value="303"/></item>
<item name="A2" rev="15"> <item name="A2" rev="17">
<attrib name="value" value="481"/></item> <attrib name="value" value="472"/></item>
<item name="A3" rev="15"> <item name="A3" rev="17">
<attrib name="value" value="575"/></item> <attrib name="value" value="568"/></item>
<item name="A4" rev="15"> <item name="A4" rev="17">
<attrib name="value" value="827"/></item> <attrib name="value" value="845"/></item>
<item name="A5" rev="15"> <item name="A5" rev="17">
<attrib name="value" value="749"/></item> <attrib name="value" value="751"/></item>
<item name="A6" rev="15"> <item name="A6" rev="17">
<attrib name="value" value="885"/></item> <attrib name="value" value="908"/></item>
<item name="O6" rev="15"> <item name="O6" rev="17">
<attrib name="value" value="900"/></item> <attrib name="value" value="919"/></item>
</group> </group>
<group name="SELMUX2_1"> <group name="SELMUX2_1">
<item name="0" rev="15"> <item name="0" rev="17">
<attrib name="value" value="18"/></item> <attrib name="value" value="28"/></item>
<item name="1" rev="15"> <item name="1" rev="17">
<attrib name="value" value="18"/></item> <attrib name="value" value="28"/></item>
<item name="OUT" rev="15"> <item name="OUT" rev="17">
<attrib name="value" value="18"/></item> <attrib name="value" value="28"/></item>
<item name="S0" rev="15"> <item name="S0" rev="17">
<attrib name="value" value="18"/></item> <attrib name="value" value="28"/></item>
</group> </group>
<group name="IOB_IMUX"> <group name="IOB_IMUX">
<item name="I" rev="15"> <item name="I" rev="17">
<attrib name="value" value="159"/></item> <attrib name="value" value="159"/></item>
<item name="OUT" rev="15"> <item name="OUT" rev="17">
<attrib name="value" value="159"/></item> <attrib name="value" value="159"/></item>
</group> </group>
<group name="IOB"> <group name="IOB">
<item name="DIFFI_IN" rev="15"> <item name="DIFFI_IN" rev="17">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
<item name="I" rev="15"> <item name="I" rev="17">
<attrib name="value" value="159"/></item> <attrib name="value" value="159"/></item>
<item name="O" rev="15"> <item name="O" rev="17">
<attrib name="value" value="198"/></item> <attrib name="value" value="198"/></item>
<item name="PAD" rev="15"> <item name="PAD" rev="17">
<attrib name="value" value="326"/></item> <attrib name="value" value="326"/></item>
<item name="PADOUT" rev="15"> <item name="PADOUT" rev="17">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
<item name="T" rev="15"> <item name="T" rev="17">
<attrib name="value" value="44"/></item> <attrib name="value" value="44"/></item>
</group> </group>
<group name="HARD0"> <group name="HARD0">
<item name="0" rev="15"> <item name="0" rev="17">
<attrib name="value" value="11"/></item> <attrib name="value" value="11"/></item>
</group> </group>
<group name="FF_SR"> <group name="FF_SR">
<item name="CE" rev="15"> <item name="CE" rev="17">
<attrib name="value" value="52"/></item> <attrib name="value" value="49"/></item>
<item name="CK" rev="15"> <item name="CK" rev="17">
<attrib name="value" value="89"/></item> <attrib name="value" value="86"/></item>
<item name="D" rev="15"> <item name="D" rev="17">
<attrib name="value" value="89"/></item> <attrib name="value" value="86"/></item>
<item name="Q" rev="15"> <item name="Q" rev="17">
<attrib name="value" value="89"/></item> <attrib name="value" value="86"/></item>
<item name="SR" rev="15"> <item name="SR" rev="17">
<attrib name="value" value="40"/></item> <attrib name="value" value="33"/></item>
</group> </group>
<group name="BUFG"> <group name="BUFG">
<item name="I0" rev="15"> <item name="I0" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
<item name="O" rev="15"> <item name="O" rev="17">
<attrib name="value" value="4"/></item> <attrib name="value" value="4"/></item>
</group> </group>
</ReportPinData> </ReportPinData>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_xst.xrpt
View file @ 265c6bd0
...@@ -5,14 +5,14 @@ ...@@ -5,14 +5,14 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Fri Dec 17 11:10:57 2010"> <application stringID="Xst" timeStamp="Mon Dec 20 08:25:12 2010">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
<column stringID="value"/> <column stringID="value"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="variable" value="Path"/> <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row> </row>
<row stringID="row" value="1"> <row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/> <item stringID="variable" value="PATHEXT"/>
...@@ -112,10 +112,10 @@ ...@@ -112,10 +112,10 @@
<item dataType="int" stringID="XST_1BIT_REGISTER" value="68"/> <item dataType="int" stringID="XST_1BIT_REGISTER" value="68"/>
<item dataType="int" stringID="XST_16BIT_REGISTER" value="2"/> <item dataType="int" stringID="XST_16BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_2BIT_REGISTER" value="4"/> <item dataType="int" stringID="XST_2BIT_REGISTER" value="4"/>
<item dataType="int" stringID="XST_22BIT_REGISTER" value="4"/> <item dataType="int" stringID="XST_22BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_3BIT_REGISTER" value="6"/> <item dataType="int" stringID="XST_3BIT_REGISTER" value="4"/>
<item dataType="int" stringID="XST_32BIT_REGISTER" value="15"/> <item dataType="int" stringID="XST_32BIT_REGISTER" value="15"/>
<item dataType="int" stringID="XST_4BIT_REGISTER" value="1"/> <item dataType="int" stringID="XST_4BIT_REGISTER" value="3"/>
<item dataType="int" stringID="XST_7BIT_REGISTER" value="1"/> <item dataType="int" stringID="XST_7BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_8BIT_REGISTER" value="3"/> <item dataType="int" stringID="XST_8BIT_REGISTER" value="3"/>
<item dataType="int" stringID="XST_9BIT_REGISTER" value="1"/> <item dataType="int" stringID="XST_9BIT_REGISTER" value="1"/>
...@@ -138,7 +138,7 @@ ...@@ -138,7 +138,7 @@
</item> </item>
<item dataType="int" stringID="XST_FSMS" value="2"/> <item dataType="int" stringID="XST_FSMS" value="2"/>
<item dataType="int" stringID="XST_XORS" value="4"> <item dataType="int" stringID="XST_XORS" value="4">
<item dataType="int" stringID="XST_1BIT_XOR3" value="2"/> <item dataType="int" stringID="XST_1BIT_XOR2" value="2"/>
<item dataType="int" stringID="XST_1BIT_XOR6" value="2"/> <item dataType="int" stringID="XST_1BIT_XOR6" value="2"/>
</item> </item>
</section> </section>
...@@ -152,8 +152,8 @@ ...@@ -152,8 +152,8 @@
<item dataType="int" stringID="XST_3BIT_UP_COUNTER" value="2"/> <item dataType="int" stringID="XST_3BIT_UP_COUNTER" value="2"/>
<item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="1"/> <item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="1"/>
</item> </item>
<item dataType="int" stringID="XST_REGISTERS" value="680"> <item dataType="int" stringID="XST_REGISTERS" value="682">
<item dataType="int" stringID="XST_FLIPFLOPS" value="680"/> <item dataType="int" stringID="XST_FLIPFLOPS" value="682"/>
</item> </item>
<item dataType="int" stringID="XST_COMPARATORS" value="9"> <item dataType="int" stringID="XST_COMPARATORS" value="9">
<item dataType="int" stringID="XST_1BIT_COMPARATOR_EQUAL" value="1"/> <item dataType="int" stringID="XST_1BIT_COMPARATOR_EQUAL" value="1"/>
...@@ -170,17 +170,17 @@ ...@@ -170,17 +170,17 @@
</item> </item>
<item dataType="int" stringID="XST_FSMS" value="2"/> <item dataType="int" stringID="XST_FSMS" value="2"/>
<item dataType="int" stringID="XST_XORS" value="4"> <item dataType="int" stringID="XST_XORS" value="4">
<item dataType="int" stringID="XST_1BIT_XOR3" value="2"/> <item dataType="int" stringID="XST_1BIT_XOR2" value="2"/>
<item dataType="int" stringID="XST_1BIT_XOR6" value="2"/> <item dataType="int" stringID="XST_1BIT_XOR6" value="2"/>
</item> </item>
</section> </section>
<section stringID="XST_FINAL_REGISTER_REPORT"> <section stringID="XST_FINAL_REGISTER_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="793"> <item dataType="int" stringID="XST_REGISTERS" value="807">
<item dataType="int" stringID="XST_FLIPFLOPS" value="793"/> <item dataType="int" stringID="XST_FLIPFLOPS" value="807"/>
</item> </item>
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="3"> <item dataType="int" stringID="XST_SHIFT_REGISTERS" value="5">
<item dataType="int" stringID="XST_2BIT_SHIFT_REGISTER" value="2"/> <item dataType="int" stringID="XST_2BIT_SHIFT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_3BIT_SHIFT_REGISTER" value="1"/> <item dataType="int" stringID="XST_3BIT_SHIFT_REGISTER" value="3"/>
</item> </item>
</section> </section>
<section stringID="XST_PARTITION_REPORT"> <section stringID="XST_PARTITION_REPORT">
...@@ -193,34 +193,34 @@ ...@@ -193,34 +193,34 @@
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="SFpga.ngc"/> <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="SFpga.ngc"/>
</section> </section>
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE"> <section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
<item dataType="int" stringID="XST_BELS" value="1430"> <item dataType="int" stringID="XST_BELS" value="1497">
<item dataType="int" stringID="XST_GND" value="1"/> <item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="29"/> <item dataType="int" stringID="XST_INV" value="29"/>
<item dataType="int" stringID="XST_LUT1" value="163"/> <item dataType="int" stringID="XST_LUT1" value="181"/>
<item dataType="int" stringID="XST_LUT2" value="163"/> <item dataType="int" stringID="XST_LUT2" value="166"/>
<item dataType="int" stringID="XST_LUT3" value="121"/> <item dataType="int" stringID="XST_LUT3" value="130"/>
<item dataType="int" stringID="XST_LUT4" value="112"/> <item dataType="int" stringID="XST_LUT4" value="113"/>
<item dataType="int" stringID="XST_LUT5" value="148"/> <item dataType="int" stringID="XST_LUT5" value="146"/>
<item dataType="int" stringID="XST_LUT6" value="307"/> <item dataType="int" stringID="XST_LUT6" value="299"/>
<item dataType="int" stringID="XST_MUXCY" value="186"/> <item dataType="int" stringID="XST_MUXCY" value="204"/>
<item dataType="int" stringID="XST_MUXF7" value="18"/> <item dataType="int" stringID="XST_MUXF7" value="28"/>
<item dataType="int" stringID="XST_VCC" value="1"/> <item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XORCY" value="181"/> <item dataType="int" stringID="XST_XORCY" value="199"/>
</item> </item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="796"> <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="812">
<item dataType="int" stringID="XST_FD" value="189"/> <item dataType="int" stringID="XST_FD" value="191"/>
<item dataType="int" stringID="XST_FDE" value="99"/> <item dataType="int" stringID="XST_FDE" value="101"/>
<item dataType="int" stringID="XST_FDPE" value="1"/> <item dataType="int" stringID="XST_FDPE" value="1"/>
<item dataType="int" stringID="XST_FDR" value="135"/> <item dataType="int" stringID="XST_FDR" value="135"/>
<item dataType="int" stringID="XST_FDRE" value="313"/> <item dataType="int" stringID="XST_FDRE" value="325"/>
<item dataType="int" stringID="XST_FDS" value="26"/> <item dataType="int" stringID="XST_FDS" value="26"/>
<item dataType="int" stringID="XST_FDSE" value="33"/> <item dataType="int" stringID="XST_FDSE" value="33"/>
</item> </item>
<item dataType="int" stringID="XST_RAMS" value="3"> <item dataType="int" stringID="XST_RAMS" value="3">
<item dataType="int" stringID="XST_RAM16X1D" value="2"/> <item dataType="int" stringID="XST_RAM16X1D" value="2"/>
</item> </item>
<item dataType="int" stringID="XST_SHIFT_REGISTERS" value="3"> <item dataType="int" stringID="XST_SHIFT_REGISTERS" value="5">
<item dataType="int" stringID="XST_SRLC16E" value="3"/> <item dataType="int" stringID="XST_SRLC16E" value="5"/>
</item> </item>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="4"> <item dataType="int" stringID="XST_CLOCK_BUFFERS" value="4">
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="1"/> <item dataType="int" label="-bufg" stringID="XST_BUFG" value="1"/>
...@@ -236,15 +236,15 @@ ...@@ -236,15 +236,15 @@
</section> </section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY"> <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="6slx150tfgg676-3"/> <item stringID="XST_SELECTED_DEVICE" value="6slx150tfgg676-3"/>
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="796"/> <item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="812"/>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="1054"/> <item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="1077"/>
<item AVAILABLE="92152" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="1043"/> <item AVAILABLE="92152" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="1064"/>
<item AVAILABLE="21680" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="11"/> <item AVAILABLE="21680" dataType="int" stringID="XST_NUMBER_USED_AS_MEMORY" value="13"/>
<item dataType="int" stringID="XST_NUMBER_USED_AS_SRL" value="3"/> <item dataType="int" stringID="XST_NUMBER_USED_AS_SRL" value="5"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="1274"/> <item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="1293"/>
<item AVAILABLE="1274" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="478"/> <item AVAILABLE="1293" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="481"/>
<item AVAILABLE="1274" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="220"/> <item AVAILABLE="1293" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="216"/>
<item AVAILABLE="1274" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="576"/> <item AVAILABLE="1293" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="596"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="32"/> <item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="32"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="365"/> <item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="365"/>
<item AVAILABLE="396" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="319"/> <item AVAILABLE="396" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="319"/>
......
trunk/firmware/XilinxISE/SystemFpga/SystemFpga.gise
View file @ 265c6bd0
...@@ -107,7 +107,7 @@ ...@@ -107,7 +107,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1292580677" xil_pn:in_ck="2606969364006439169" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1292580654"> <transform xil_pn:end_ts="1292829931" xil_pn:in_ck="2606969364006439169" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1292829909">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -129,7 +129,7 @@ ...@@ -129,7 +129,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1292580684" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1292580677"> <transform xil_pn:end_ts="1292829942" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1292829931">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -139,7 +139,7 @@ ...@@ -139,7 +139,7 @@
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292580741" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292580684"> <transform xil_pn:end_ts="1292830015" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292829942">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -155,7 +155,7 @@ ...@@ -155,7 +155,7 @@
<outfile xil_pn:name="SFpga_usage.xml"/> <outfile xil_pn:name="SFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292580788" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292580741"> <transform xil_pn:end_ts="1292830063" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292830015">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -170,10 +170,11 @@ ...@@ -170,10 +170,11 @@
<outfile xil_pn:name="SFpga_par.xrpt"/> <outfile xil_pn:name="SFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1292580816" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1292580788"> <transform xil_pn:end_ts="1292830091" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1292830063">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<outfile xil_pn:name="SFpga.ut"/> <outfile xil_pn:name="SFpga.ut"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="sfpga.bgn"/> <outfile xil_pn:name="sfpga.bgn"/>
...@@ -183,9 +184,10 @@ ...@@ -183,9 +184,10 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1292580983" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1292580980"> <transform xil_pn:end_ts="1292832753" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1292832751">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform> </transform>
<transform xil_pn:end_ts="1292422596" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_createIBISModel_spartan6" xil_pn:prop_ck="-6143094129183081966" xil_pn:start_ts="1292422570"> <transform xil_pn:end_ts="1292422596" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_createIBISModel_spartan6" xil_pn:prop_ck="-6143094129183081966" xil_pn:start_ts="1292422570">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
...@@ -197,7 +199,7 @@ ...@@ -197,7 +199,7 @@
<status xil_pn:value="InputRemoved"/> <status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/> <status xil_pn:value="OutputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1292580788" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292580776"> <transform xil_pn:end_ts="1292830063" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292830051">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="SFpga.twr"/> <outfile xil_pn:name="SFpga.twr"/>
......
trunk/firmware/XilinxISE/SystemFpga/SystemFpga.xise
View file @ 265c6bd0
...@@ -97,11 +97,11 @@ ...@@ -97,11 +97,11 @@
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/> <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
......
trunk/firmware/XilinxISE/SystemFpga/_ngo/netlist.lst
View file @ 265c6bd0
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292580676 C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292829930
OK OK
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/map.xmsgs
View file @ 265c6bd0
...@@ -5,11 +5,11 @@ ...@@ -5,11 +5,11 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">N450</arg> has no load. <msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">N456</arg> has no load.
</msg> </msg>
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">51</arg> more times for the following (max. 5 shown): <msg type="info" file="LIT" num="395" delta="new" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">51</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">N452, <arg fmt="%s" index="3">N458,
VmeAm_ib6&lt;2&gt;_IBUF, VmeAm_ib6&lt;2&gt;_IBUF,
VmeAm_ib6&lt;1&gt;_IBUF, VmeAm_ib6&lt;1&gt;_IBUF,
VmeDs_inb2&lt;2&gt;_IBUF, VmeDs_inb2&lt;2&gt;_IBUF,
...@@ -137,7 +137,7 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please ...@@ -137,7 +137,7 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp). <msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg> </msg>
<msg type="info" file="Place" num="834" delta="new" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">330</arg> IOs, <arg fmt="%d" index="2">328</arg> are locked and <arg fmt="%d" index="3">2</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg> <msg type="info" file="Place" num="834" delta="old" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">330</arg> IOs, <arg fmt="%d" index="2">328</arg> are locked and <arg fmt="%d" index="3">2</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg>
</msg> </msg>
<msg type="warning" file="Place" num="1109" delta="old" >A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component &lt;<arg fmt="%s" index="1">VmeSysClk_ik</arg>&gt; is placed at site &lt;<arg fmt="%s" index="2">PAD550</arg>&gt;. The corresponding BUFG component &lt;<arg fmt="%s" index="3">VmeSysClk_ik_BUFGP/BUFG</arg>&gt; is placed at site &lt;<arg fmt="%s" index="4">BUFGMUX_X2Y9</arg>&gt;. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">VmeSysClk_ik.PAD</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. <msg type="warning" file="Place" num="1109" delta="old" >A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component &lt;<arg fmt="%s" index="1">VmeSysClk_ik</arg>&gt; is placed at site &lt;<arg fmt="%s" index="2">PAD550</arg>&gt;. The corresponding BUFG component &lt;<arg fmt="%s" index="3">VmeSysClk_ik_BUFGP/BUFG</arg>&gt; is placed at site &lt;<arg fmt="%s" index="4">BUFGMUX_X2Y9</arg>&gt;. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">VmeSysClk_ik.PAD</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
......
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/ngdbuild.xmsgs
View file @ 265c6bd0
...@@ -5,10 +5,10 @@ ...@@ -5,10 +5,10 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N450</arg>&apos; has no driver <msg type="warning" file="NgdBuild" num="452" delta="new" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N456</arg>&apos; has no driver
</msg> </msg>
<msg type="warning" file="NgdBuild" num="452" delta="old" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N452</arg>&apos; has no driver <msg type="warning" file="NgdBuild" num="452" delta="new" ><arg fmt="%s" index="1">logical</arg> net &apos;<arg fmt="%s" index="2">N458</arg>&apos; has no driver
</msg> </msg>
<msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgM_iob2&lt;1&gt;</arg>&apos; has no legal driver <msg type="warning" file="NgdBuild" num="470" delta="old" ><arg fmt="%s" index="1">bidirect</arg> pad net &apos;<arg fmt="%s" index="2">AFpgaProgM_iob2&lt;1&gt;</arg>&apos; has no legal driver
......
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/pn_parser.xmsgs
View file @ 265c6bd0
...@@ -8,8 +8,38 @@ ...@@ -8,8 +8,38 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages> <messages>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/AddrDecoderWBSys.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Debouncer.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Generic4InputRegs.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Generic4OutputRegs.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/InterruptManagerWB.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Monostable.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/Slv2SerWB.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/SpiMasterWB.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/SystemFpga.v\&quot; into library work</arg> <msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/SystemFpga.v\&quot; into library work</arg>
</msg> </msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/VmeInterfaceWB.v\&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/XilinxWrappers/SFpga.v\&quot; into library work</arg>
</msg>
</messages> </messages>
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport
View file @ 265c6bd0
<?xml version='1.0' encoding='UTF-8'?> <?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" > <report-views version="2.0" >
<header> <header>
<DateModified>2010-12-17T11:09:45</DateModified> <DateModified>2010-12-20T09:27:08</DateModified>
<ModuleName>SFpga</ModuleName> <ModuleName>SFpga</ModuleName>
<SummaryTimeStamp>2010-12-15T15:17:10</SummaryTimeStamp> <SummaryTimeStamp>2010-12-15T15:17:10</SummaryTimeStamp>
<SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath> <SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath>
......
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SystemFpga.projectmgr
View file @ 265c6bd0
...@@ -64,13 +64,13 @@ ...@@ -64,13 +64,13 @@
<ClosedNode>Implement Design/Translate</ClosedNode> <ClosedNode>Implement Design/Translate</ClosedNode>
</ClosedNodes> </ClosedNodes>
<SelectedItems> <SelectedItems>
<SelectedItem>Generate Target PROM/ACE File</SelectedItem> <SelectedItem>Generate Programming File</SelectedItem>
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >14</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >14</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Generate Target PROM/ACE File</CurrentItem> <CurrentItem>Generate Programming File</CurrentItem>
</ItemView> </ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" > <ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes> <ClosedNodes>
......
trunk/firmware/XilinxISE/SystemFpga/par_usage_statistics.html
View file @ 265c6bd0
<TABLE BORDER CELLSPACING=0 WIDTH='100%'> <TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics"> <xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1486</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1498</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4740</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4733</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4740</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4733</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4274</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4267</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>11.5 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>11.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>15.0 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>15.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>21.0 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>20.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>26.5 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>26.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>28.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>28.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>28.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>28.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>28.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>29.7 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>28.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>16.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>15.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>10.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>10.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>8.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>8.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>8.9</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>9.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>9.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>8.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>5.5</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>5.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>5.3</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>5.1</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0984</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0983</xtag-par-property-value></TD></TR>
</xtag-section> </xtag-section>
</TABLE> </TABLE>
trunk/firmware/XilinxISE/SystemFpga/sfpga.bgn
View file @ 265c6bd0
...@@ -5,7 +5,7 @@ C:\Xilinx\12.3\ISE_DS\ISE\. ...@@ -5,7 +5,7 @@ C:\Xilinx\12.3\ISE_DS\ISE\.
"SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3 "SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
Opened constraints file SFpga.pcf. Opened constraints file SFpga.pcf.
Fri Dec 17 11:13:13 2010 Mon Dec 20 08:27:48 2010
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd
......
trunk/firmware/XilinxISE/SystemFpga/sfpga.drc
View file @ 265c6bd0
Release 12.3 Drc M.70d (nt64) Release 12.3 Drc M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 11:13:13 2010 Mon Dec 20 08:27:48 2010
drc -z SFpga.ncd SFpga.pcf drc -z SFpga.ncd SFpga.pcf
......
trunk/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html
View file @ 265c6bd0
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD> <TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">effa8437e76f45ca9db699794ac1987e</xtag-property>.<xtag-property name="ProjectID">F6031676C5FE434A8E9F8A1057A8E48F</xtag-property>.<xtag-property name="ProjectIteration">6</xtag-property></TD> <TD><xtag-property name="RandomID">effa8437e76f45ca9db699794ac1987e</xtag-property>.<xtag-property name="ProjectID">F6031676C5FE434A8E9F8A1057A8E48F</xtag-property>.<xtag-property name="ProjectIteration">7</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD> <TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">fgg676</xtag-property></TD> <TD><xtag-property name="TargetPackage">fgg676</xtag-property></TD>
</TR> </TR>
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD> <TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2010-12-17T11:13:31</xtag-property></TD> <TD><xtag-property name="Date Generated">2010-12-20T08:28:06</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD> <TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD> <TD><xtag-property name="ToolFlow">ISE</xtag-property></TD>
</TR> </TR>
...@@ -87,8 +87,8 @@ ...@@ -87,8 +87,8 @@
<xtag-group><xtag-group-name name="Counters=10">Counters=10</xtag-group-name> <xtag-group><xtag-group-name name="Counters=10">Counters=10</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>16-bit up counter=1</xtag-item1></LI> <LI><xtag-item1>16-bit up counter=1</xtag-item1></LI>
<LI><xtag-item1>20-bit up counter=2</xtag-item1></LI> <LI><xtag-item1>24-bit up counter=3</xtag-item1></LI>
<LI><xtag-item1>22-bit up counter=3</xtag-item1></LI> <LI><xtag-item1>26-bit up counter=2</xtag-item1></LI>
<LI><xtag-item1>3-bit up counter=2</xtag-item1></LI> <LI><xtag-item1>3-bit up counter=2</xtag-item1></LI>
<LI><xtag-item1>4-bit updown counter=1</xtag-item1></LI> <LI><xtag-item1>4-bit updown counter=1</xtag-item1></LI>
<LI><xtag-item1>9-bit up counter=1</xtag-item1></LI> <LI><xtag-item1>9-bit up counter=1</xtag-item1></LI>
...@@ -116,14 +116,14 @@ ...@@ -116,14 +116,14 @@
<LI><xtag-item1>8x8-bit dual-port distributed RAM=1</xtag-item1></LI> <LI><xtag-item1>8x8-bit dual-port distributed RAM=1</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="Registers=680">Registers=680</xtag-group-name> <xtag-group><xtag-group-name name="Registers=682">Registers=682</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>Flip-Flops=680</xtag-item1></LI> <LI><xtag-item1>Flip-Flops=682</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="Xors=4">Xors=4</xtag-group-name> <xtag-group><xtag-group-name name="Xors=4">Xors=4</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>1-bit xor3=2</xtag-item1></LI> <LI><xtag-item1>1-bit xor2=2</xtag-item1></LI>
<LI><xtag-item1>1-bit xor6=2</xtag-item1></LI> <LI><xtag-item1>1-bit xor6=2</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
...@@ -136,14 +136,14 @@ ...@@ -136,14 +136,14 @@
<LI><xtag-item1>AGG_BONDED_IO=330</xtag-item1></LI> <LI><xtag-item1>AGG_BONDED_IO=330</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=330</xtag-item1></LI> <LI><xtag-item1>AGG_IO=330</xtag-item1></LI>
<LI><xtag-item1>AGG_LOCED_IO=328</xtag-item1></LI> <LI><xtag-item1>AGG_LOCED_IO=328</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=374</xtag-item1></LI> <LI><xtag-item1>AGG_SLICE=365</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=326</xtag-item1></LI> <LI><xtag-item1>NUM_BONDED_IOB=326</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOBM=2</xtag-item1></LI> <LI><xtag-item1>NUM_BONDED_IOBM=2</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOBS=2</xtag-item1></LI> <LI><xtag-item1>NUM_BONDED_IOBS=2</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=548</xtag-item1></LI> <LI><xtag-item1>NUM_BSFULL=590</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=386</xtag-item1></LI> <LI><xtag-item1>NUM_BSLUTONLY=364</xtag-item1></LI>
<LI><xtag-item1>NUM_BSREGONLY=167</xtag-item1></LI> <LI><xtag-item1>NUM_BSREGONLY=144</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=1101</xtag-item1></LI> <LI><xtag-item1>NUM_BSUSED=1098</xtag-item1></LI>
<LI><xtag-item1>NUM_BUFG=4</xtag-item1></LI> <LI><xtag-item1>NUM_BUFG=4</xtag-item1></LI>
<LI><xtag-item1>NUM_DPRAM_O5ANDO6=4</xtag-item1></LI> <LI><xtag-item1>NUM_DPRAM_O5ANDO6=4</xtag-item1></LI>
<LI><xtag-item1>NUM_DPRAM_O6ONLY=4</xtag-item1></LI> <LI><xtag-item1>NUM_DPRAM_O6ONLY=4</xtag-item1></LI>
...@@ -151,67 +151,67 @@ ...@@ -151,67 +151,67 @@
<LI><xtag-item1>NUM_LOCED_IOBM=2</xtag-item1></LI> <LI><xtag-item1>NUM_LOCED_IOBM=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOBS=2</xtag-item1></LI> <LI><xtag-item1>NUM_LOCED_IOBS=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=166</xtag-item1></LI> <LI><xtag-item1>NUM_LOGIC_O5ANDO6=166</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ONLY=154</xtag-item1></LI> <LI><xtag-item1>NUM_LOGIC_O5ONLY=172</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=571</xtag-item1></LI> <LI><xtag-item1>NUM_LOGIC_O6ONLY=573</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=9</xtag-item1></LI> <LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=9</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=23</xtag-item1></LI> <LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=21</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO5=23</xtag-item1></LI> <LI><xtag-item1>NUM_LUT_RT_EXO5=21</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO6=9</xtag-item1></LI> <LI><xtag-item1>NUM_LUT_RT_EXO6=9</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O5=5</xtag-item1></LI> <LI><xtag-item1>NUM_LUT_RT_O5=11</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O6=154</xtag-item1></LI> <LI><xtag-item1>NUM_LUT_RT_O6=172</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=70</xtag-item1></LI> <LI><xtag-item1>NUM_SLICEL=84</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEM=4</xtag-item1></LI> <LI><xtag-item1>NUM_SLICEM=4</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=300</xtag-item1></LI> <LI><xtag-item1>NUM_SLICEX=277</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=52</xtag-item1></LI> <LI><xtag-item1>NUM_SLICE_CARRY4=56</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CONTROLSET=32</xtag-item1></LI> <LI><xtag-item1>NUM_SLICE_CONTROLSET=32</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=1274</xtag-item1></LI> <LI><xtag-item1>NUM_SLICE_CYINIT=1318</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_F7MUX=18</xtag-item1></LI> <LI><xtag-item1>NUM_SLICE_F7MUX=28</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=796</xtag-item1></LI> <LI><xtag-item1>NUM_SLICE_FF=812</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=115</xtag-item1></LI> <LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=115</xtag-item1></LI>
<LI><xtag-item1>NUM_SRL_O6ONLY=3</xtag-item1></LI> <LI><xtag-item1>NUM_SRL_O6ONLY=5</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=85</xtag-item1></LI> <LI><xtag-item1>NUM_UNUSABLE_FF_BELS=83</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
</TD> </TD>
<TD> <TD>
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name> <xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>NumNets_Active=1863</xtag-item1></LI> <LI><xtag-item1>NumNets_Active=1875</xtag-item1></LI>
<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI> <LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI>
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI> <LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=30</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=31</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=225</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=197</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=4</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=17</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=14</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=259</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_CLKPIN=250</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=21</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=18</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=310</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=307</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=2002</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_DOUBLE=1931</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=358</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_GENERIC=358</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=146</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_GLOBAL=129</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=50</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_INPUT=56</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=245</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=245</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=245</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=245</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=3702</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=3703</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=1554</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=1566</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=1413</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_OUTPUT=1430</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=137</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_PADINPUT=137</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=116</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=116</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=814</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=813</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=4282</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_PINFEED=4267</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=5514</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_QUAD=5506</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=282</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_REGINPUT=280</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=2320</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Active_SINGLE=2294</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=2</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_GENERIC=13</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_GENERIC=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=136</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=141</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBIN2OUT=13</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_IOBIN2OUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBOUTPUT=13</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_IOBOUTPUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_KVCCOUT=6</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_KVCCOUT=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=340</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=370</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PADINPUT=13</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_PADINPUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINBOUNCE=13</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_PINBOUNCE=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=353</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=383</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_REGINPUT=11</xtag-item1></LI> <LI><xtag-item1>NumNodesOfType_Vcc_REGINPUT=11</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
...@@ -220,9 +220,9 @@ ...@@ -220,9 +220,9 @@
<LI><xtag-item1>BUFG-BUFGMUX=4</xtag-item1></LI> <LI><xtag-item1>BUFG-BUFGMUX=4</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBM=161</xtag-item1></LI> <LI><xtag-item1>IOB-IOBM=161</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBS=165</xtag-item1></LI> <LI><xtag-item1>IOB-IOBS=165</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=25</xtag-item1></LI> <LI><xtag-item1>SLICEL-SLICEM=44</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=73</xtag-item1></LI> <LI><xtag-item1>SLICEX-SLICEL=55</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=63</xtag-item1></LI> <LI><xtag-item1>SLICEX-SLICEM=64</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
</TD> </TD>
...@@ -233,8 +233,8 @@ ...@@ -233,8 +233,8 @@
<UL> <UL>
<LI><xtag-item2>BUFG=4</xtag-item2></LI> <LI><xtag-item2>BUFG=4</xtag-item2></LI>
<LI><xtag-item2>BUFG_BUFG=4</xtag-item2></LI> <LI><xtag-item2>BUFG_BUFG=4</xtag-item2></LI>
<LI><xtag-item2>CARRY4=52</xtag-item2></LI> <LI><xtag-item2>CARRY4=56</xtag-item2></LI>
<LI><xtag-item2>FF_SR=89</xtag-item2></LI> <LI><xtag-item2>FF_SR=86</xtag-item2></LI>
<LI><xtag-item2>HARD0=11</xtag-item2></LI> <LI><xtag-item2>HARD0=11</xtag-item2></LI>
<LI><xtag-item2>IOB=326</xtag-item2></LI> <LI><xtag-item2>IOB=326</xtag-item2></LI>
<LI><xtag-item2>IOBM=2</xtag-item2></LI> <LI><xtag-item2>IOBM=2</xtag-item2></LI>
...@@ -243,17 +243,17 @@ ...@@ -243,17 +243,17 @@
<LI><xtag-item2>IOB_IMUX=159</xtag-item2></LI> <LI><xtag-item2>IOB_IMUX=159</xtag-item2></LI>
<LI><xtag-item2>IOB_INBUF=159</xtag-item2></LI> <LI><xtag-item2>IOB_INBUF=159</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=198</xtag-item2></LI> <LI><xtag-item2>IOB_OUTBUF=198</xtag-item2></LI>
<LI><xtag-item2>LUT5=348</xtag-item2></LI> <LI><xtag-item2>LUT5=370</xtag-item2></LI>
<LI><xtag-item2>LUT6=900</xtag-item2></LI> <LI><xtag-item2>LUT6=919</xtag-item2></LI>
<LI><xtag-item2>LUT_OR_MEM5=4</xtag-item2></LI> <LI><xtag-item2>LUT_OR_MEM5=4</xtag-item2></LI>
<LI><xtag-item2>LUT_OR_MEM6=11</xtag-item2></LI> <LI><xtag-item2>LUT_OR_MEM6=14</xtag-item2></LI>
<LI><xtag-item2>NULLMUX=3</xtag-item2></LI> <LI><xtag-item2>NULLMUX=3</xtag-item2></LI>
<LI><xtag-item2>PAD=330</xtag-item2></LI> <LI><xtag-item2>PAD=330</xtag-item2></LI>
<LI><xtag-item2>REG_SR=707</xtag-item2></LI> <LI><xtag-item2>REG_SR=726</xtag-item2></LI>
<LI><xtag-item2>SELMUX2_1=18</xtag-item2></LI> <LI><xtag-item2>SELMUX2_1=28</xtag-item2></LI>
<LI><xtag-item2>SLICEL=70</xtag-item2></LI> <LI><xtag-item2>SLICEL=84</xtag-item2></LI>
<LI><xtag-item2>SLICEM=4</xtag-item2></LI> <LI><xtag-item2>SLICEM=4</xtag-item2></LI>
<LI><xtag-item2>SLICEX=300</xtag-item2></LI> <LI><xtag-item2>SLICEX=277</xtag-item2></LI>
</UL> </UL>
</xtag-group> </xtag-group>
</TD> </TD>
...@@ -265,9 +265,9 @@ ...@@ -265,9 +265,9 @@
<TD> <TD>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name> <xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL> <UL>
<LI><xtag-item3>CK=[CK:89] [CK_INV:0]</xtag-item3></LI> <LI><xtag-item3>CK=[CK:86] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:78] [SRINIT1:11]</xtag-item3></LI> <LI><xtag-item3>SRINIT=[SRINIT0:75] [SRINIT1:11]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:49] [SYNC:40]</xtag-item3></LI> <LI><xtag-item3>SYNC_ATTR=[ASYNC:53] [SYNC:33]</xtag-item3></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="IOBM_OUTBUF">IOBM_OUTBUF</xtag-group-name> <xtag-group><xtag-group-name name="IOBM_OUTBUF">IOBM_OUTBUF</xtag-group-name>
...@@ -300,24 +300,24 @@ ...@@ -300,24 +300,24 @@
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name> <xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name>
<UL> <UL>
<LI><xtag-item3>CLK=[CLK:11] [CLK_INV:0]</xtag-item3></LI> <LI><xtag-item3>CLK=[CLK:13] [CLK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>LUT_OR_MEM=[RAM:11]</xtag-item3></LI> <LI><xtag-item3>LUT_OR_MEM=[LUT:1] [RAM:13]</xtag-item3></LI>
<LI><xtag-item3>RAMMODE=[SRL16:3] [DPRAM32:4] [DPRAM64:4]</xtag-item3></LI> <LI><xtag-item3>RAMMODE=[SRL16:5] [DPRAM32:4] [DPRAM64:4]</xtag-item3></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name> <xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL> <UL>
<LI><xtag-item3>CK=[CK:707] [CK_INV:0]</xtag-item3></LI> <LI><xtag-item3>CK=[CK:726] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:707]</xtag-item3></LI> <LI><xtag-item3>LATCH_OR_FF=[FF:726]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:655] [SRINIT1:52]</xtag-item3></LI> <LI><xtag-item3>SRINIT=[SRINIT0:674] [SRINIT1:52]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:240] [SYNC:467]</xtag-item3></LI> <LI><xtag-item3>SYNC_ATTR=[ASYNC:240] [SYNC:486]</xtag-item3></LI>
</UL> </UL>
</TD> </TD>
<TD> <TD>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name> <xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL> <UL>
<LI><xtag-item3>CLK=[CLK:37] [CLK_INV:0]</xtag-item3></LI> <LI><xtag-item3>CLK=[CLK:51] [CLK_INV:0]</xtag-item3></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name> <xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name>
...@@ -327,7 +327,7 @@ ...@@ -327,7 +327,7 @@
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name> <xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL> <UL>
<LI><xtag-item3>CLK=[CLK:218] [CLK_INV:0]</xtag-item3></LI> <LI><xtag-item3>CLK=[CLK:195] [CLK_INV:0]</xtag-item3></LI>
</UL> </UL>
</xtag-group> </xtag-group>
</TD> </TD>
...@@ -351,32 +351,32 @@ ...@@ -351,32 +351,32 @@
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name> <xtag-group><xtag-group-name name="CARRY4">CARRY4</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>CIN=40</xtag-item1></LI> <LI><xtag-item1>CIN=44</xtag-item1></LI>
<LI><xtag-item1>CO1=2</xtag-item1></LI> <LI><xtag-item1>CO1=2</xtag-item1></LI>
<LI><xtag-item1>CO2=1</xtag-item1></LI> <LI><xtag-item1>CO2=1</xtag-item1></LI>
<LI><xtag-item1>CO3=41</xtag-item1></LI> <LI><xtag-item1>CO3=45</xtag-item1></LI>
<LI><xtag-item1>CYINIT=12</xtag-item1></LI> <LI><xtag-item1>CYINIT=12</xtag-item1></LI>
<LI><xtag-item1>DI0=51</xtag-item1></LI> <LI><xtag-item1>DI0=55</xtag-item1></LI>
<LI><xtag-item1>DI1=47</xtag-item1></LI> <LI><xtag-item1>DI1=52</xtag-item1></LI>
<LI><xtag-item1>DI2=47</xtag-item1></LI> <LI><xtag-item1>DI2=52</xtag-item1></LI>
<LI><xtag-item1>DI3=41</xtag-item1></LI> <LI><xtag-item1>DI3=45</xtag-item1></LI>
<LI><xtag-item1>O0=48</xtag-item1></LI> <LI><xtag-item1>O0=52</xtag-item1></LI>
<LI><xtag-item1>O1=47</xtag-item1></LI> <LI><xtag-item1>O1=51</xtag-item1></LI>
<LI><xtag-item1>O2=43</xtag-item1></LI> <LI><xtag-item1>O2=48</xtag-item1></LI>
<LI><xtag-item1>O3=43</xtag-item1></LI> <LI><xtag-item1>O3=48</xtag-item1></LI>
<LI><xtag-item1>S0=52</xtag-item1></LI> <LI><xtag-item1>S0=56</xtag-item1></LI>
<LI><xtag-item1>S1=51</xtag-item1></LI> <LI><xtag-item1>S1=55</xtag-item1></LI>
<LI><xtag-item1>S2=47</xtag-item1></LI> <LI><xtag-item1>S2=52</xtag-item1></LI>
<LI><xtag-item1>S3=46</xtag-item1></LI> <LI><xtag-item1>S3=51</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name> <xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>CE=52</xtag-item1></LI> <LI><xtag-item1>CE=49</xtag-item1></LI>
<LI><xtag-item1>CK=89</xtag-item1></LI> <LI><xtag-item1>CK=86</xtag-item1></LI>
<LI><xtag-item1>D=89</xtag-item1></LI> <LI><xtag-item1>D=86</xtag-item1></LI>
<LI><xtag-item1>Q=89</xtag-item1></LI> <LI><xtag-item1>Q=86</xtag-item1></LI>
<LI><xtag-item1>SR=40</xtag-item1></LI> <LI><xtag-item1>SR=33</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="HARD0">HARD0</xtag-group-name> <xtag-group><xtag-group-name name="HARD0">HARD0</xtag-group-name>
...@@ -436,23 +436,23 @@ ...@@ -436,23 +436,23 @@
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name> <xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>A1=47</xtag-item1></LI> <LI><xtag-item1>A1=48</xtag-item1></LI>
<LI><xtag-item1>A2=48</xtag-item1></LI> <LI><xtag-item1>A2=50</xtag-item1></LI>
<LI><xtag-item1>A3=125</xtag-item1></LI> <LI><xtag-item1>A3=125</xtag-item1></LI>
<LI><xtag-item1>A4=130</xtag-item1></LI> <LI><xtag-item1>A4=130</xtag-item1></LI>
<LI><xtag-item1>A5=80</xtag-item1></LI> <LI><xtag-item1>A5=81</xtag-item1></LI>
<LI><xtag-item1>O5=348</xtag-item1></LI> <LI><xtag-item1>O5=370</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name> <xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>A1=311</xtag-item1></LI> <LI><xtag-item1>A1=303</xtag-item1></LI>
<LI><xtag-item1>A2=481</xtag-item1></LI> <LI><xtag-item1>A2=472</xtag-item1></LI>
<LI><xtag-item1>A3=575</xtag-item1></LI> <LI><xtag-item1>A3=568</xtag-item1></LI>
<LI><xtag-item1>A4=827</xtag-item1></LI> <LI><xtag-item1>A4=845</xtag-item1></LI>
<LI><xtag-item1>A5=749</xtag-item1></LI> <LI><xtag-item1>A5=751</xtag-item1></LI>
<LI><xtag-item1>A6=885</xtag-item1></LI> <LI><xtag-item1>A6=908</xtag-item1></LI>
<LI><xtag-item1>O6=900</xtag-item1></LI> <LI><xtag-item1>O6=919</xtag-item1></LI>
</UL> </UL>
</TD> </TD>
<TD> <TD>
...@@ -477,23 +477,23 @@ ...@@ -477,23 +477,23 @@
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name> <xtag-group><xtag-group-name name="LUT_OR_MEM6">LUT_OR_MEM6</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>A1=11</xtag-item1></LI> <LI><xtag-item1>A1=13</xtag-item1></LI>
<LI><xtag-item1>A2=11</xtag-item1></LI> <LI><xtag-item1>A2=13</xtag-item1></LI>
<LI><xtag-item1>A3=11</xtag-item1></LI> <LI><xtag-item1>A3=13</xtag-item1></LI>
<LI><xtag-item1>A4=11</xtag-item1></LI> <LI><xtag-item1>A4=14</xtag-item1></LI>
<LI><xtag-item1>A5=11</xtag-item1></LI> <LI><xtag-item1>A5=13</xtag-item1></LI>
<LI><xtag-item1>A6=11</xtag-item1></LI> <LI><xtag-item1>A6=14</xtag-item1></LI>
<LI><xtag-item1>CLK=11</xtag-item1></LI> <LI><xtag-item1>CLK=13</xtag-item1></LI>
<LI><xtag-item1>DI1=4</xtag-item1></LI> <LI><xtag-item1>DI1=4</xtag-item1></LI>
<LI><xtag-item1>DI2=7</xtag-item1></LI> <LI><xtag-item1>DI2=9</xtag-item1></LI>
<LI><xtag-item1>O6=8</xtag-item1></LI> <LI><xtag-item1>O6=11</xtag-item1></LI>
<LI><xtag-item1>WA1=8</xtag-item1></LI> <LI><xtag-item1>WA1=8</xtag-item1></LI>
<LI><xtag-item1>WA2=8</xtag-item1></LI> <LI><xtag-item1>WA2=8</xtag-item1></LI>
<LI><xtag-item1>WA3=8</xtag-item1></LI> <LI><xtag-item1>WA3=8</xtag-item1></LI>
<LI><xtag-item1>WA4=8</xtag-item1></LI> <LI><xtag-item1>WA4=8</xtag-item1></LI>
<LI><xtag-item1>WA5=8</xtag-item1></LI> <LI><xtag-item1>WA5=8</xtag-item1></LI>
<LI><xtag-item1>WA6=8</xtag-item1></LI> <LI><xtag-item1>WA6=8</xtag-item1></LI>
<LI><xtag-item1>WE=11</xtag-item1></LI> <LI><xtag-item1>WE=13</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="NULLMUX">NULLMUX</xtag-group-name> <xtag-group><xtag-group-name name="NULLMUX">NULLMUX</xtag-group-name>
...@@ -509,66 +509,67 @@ ...@@ -509,66 +509,67 @@
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name> <xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>CE=389</xtag-item1></LI> <LI><xtag-item1>CE=404</xtag-item1></LI>
<LI><xtag-item1>CK=707</xtag-item1></LI> <LI><xtag-item1>CK=726</xtag-item1></LI>
<LI><xtag-item1>D=707</xtag-item1></LI> <LI><xtag-item1>D=726</xtag-item1></LI>
<LI><xtag-item1>Q=707</xtag-item1></LI> <LI><xtag-item1>Q=726</xtag-item1></LI>
<LI><xtag-item1>SR=468</xtag-item1></LI> <LI><xtag-item1>SR=487</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="SELMUX2_1">SELMUX2_1</xtag-group-name> <xtag-group><xtag-group-name name="SELMUX2_1">SELMUX2_1</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>0=18</xtag-item1></LI> <LI><xtag-item1>0=28</xtag-item1></LI>
<LI><xtag-item1>1=18</xtag-item1></LI> <LI><xtag-item1>1=28</xtag-item1></LI>
<LI><xtag-item1>OUT=18</xtag-item1></LI> <LI><xtag-item1>OUT=28</xtag-item1></LI>
<LI><xtag-item1>S0=18</xtag-item1></LI> <LI><xtag-item1>S0=28</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name> <xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>A=8</xtag-item1></LI> <LI><xtag-item1>A=13</xtag-item1></LI>
<LI><xtag-item1>A1=11</xtag-item1></LI> <LI><xtag-item1>A1=13</xtag-item1></LI>
<LI><xtag-item1>A2=11</xtag-item1></LI> <LI><xtag-item1>A2=17</xtag-item1></LI>
<LI><xtag-item1>A3=14</xtag-item1></LI> <LI><xtag-item1>A3=20</xtag-item1></LI>
<LI><xtag-item1>A4=48</xtag-item1></LI> <LI><xtag-item1>A4=58</xtag-item1></LI>
<LI><xtag-item1>A5=29</xtag-item1></LI> <LI><xtag-item1>A5=34</xtag-item1></LI>
<LI><xtag-item1>A6=61</xtag-item1></LI> <LI><xtag-item1>A6=71</xtag-item1></LI>
<LI><xtag-item1>AMUX=19</xtag-item1></LI> <LI><xtag-item1>AMUX=18</xtag-item1></LI>
<LI><xtag-item1>AQ=37</xtag-item1></LI> <LI><xtag-item1>AQ=47</xtag-item1></LI>
<LI><xtag-item1>AX=8</xtag-item1></LI> <LI><xtag-item1>AX=13</xtag-item1></LI>
<LI><xtag-item1>B=9</xtag-item1></LI> <LI><xtag-item1>B=16</xtag-item1></LI>
<LI><xtag-item1>B1=8</xtag-item1></LI> <LI><xtag-item1>B1=12</xtag-item1></LI>
<LI><xtag-item1>B2=9</xtag-item1></LI> <LI><xtag-item1>B2=18</xtag-item1></LI>
<LI><xtag-item1>B3=12</xtag-item1></LI> <LI><xtag-item1>B3=20</xtag-item1></LI>
<LI><xtag-item1>B4=47</xtag-item1></LI> <LI><xtag-item1>B4=59</xtag-item1></LI>
<LI><xtag-item1>B5=27</xtag-item1></LI> <LI><xtag-item1>B5=35</xtag-item1></LI>
<LI><xtag-item1>B6=57</xtag-item1></LI> <LI><xtag-item1>B6=70</xtag-item1></LI>
<LI><xtag-item1>BMUX=18</xtag-item1></LI> <LI><xtag-item1>BMUX=17</xtag-item1></LI>
<LI><xtag-item1>BQ=35</xtag-item1></LI> <LI><xtag-item1>BQ=44</xtag-item1></LI>
<LI><xtag-item1>BX=4</xtag-item1></LI> <LI><xtag-item1>BX=9</xtag-item1></LI>
<LI><xtag-item1>C1=7</xtag-item1></LI> <LI><xtag-item1>C1=10</xtag-item1></LI>
<LI><xtag-item1>C2=8</xtag-item1></LI> <LI><xtag-item1>C2=13</xtag-item1></LI>
<LI><xtag-item1>C3=19</xtag-item1></LI> <LI><xtag-item1>C3=22</xtag-item1></LI>
<LI><xtag-item1>C4=49</xtag-item1></LI> <LI><xtag-item1>C4=66</xtag-item1></LI>
<LI><xtag-item1>C5=32</xtag-item1></LI> <LI><xtag-item1>C5=47</xtag-item1></LI>
<LI><xtag-item1>C6=61</xtag-item1></LI> <LI><xtag-item1>C6=81</xtag-item1></LI>
<LI><xtag-item1>CE=13</xtag-item1></LI> <LI><xtag-item1>CE=25</xtag-item1></LI>
<LI><xtag-item1>CIN=40</xtag-item1></LI> <LI><xtag-item1>CIN=44</xtag-item1></LI>
<LI><xtag-item1>CLK=37</xtag-item1></LI> <LI><xtag-item1>CLK=51</xtag-item1></LI>
<LI><xtag-item1>CMUX=32</xtag-item1></LI> <LI><xtag-item1>CMUX=42</xtag-item1></LI>
<LI><xtag-item1>COUT=40</xtag-item1></LI> <LI><xtag-item1>COUT=44</xtag-item1></LI>
<LI><xtag-item1>CQ=34</xtag-item1></LI> <LI><xtag-item1>CQ=48</xtag-item1></LI>
<LI><xtag-item1>CX=21</xtag-item1></LI> <LI><xtag-item1>CX=32</xtag-item1></LI>
<LI><xtag-item1>D1=8</xtag-item1></LI> <LI><xtag-item1>D=1</xtag-item1></LI>
<LI><xtag-item1>D2=21</xtag-item1></LI> <LI><xtag-item1>D1=7</xtag-item1></LI>
<LI><xtag-item1>D3=23</xtag-item1></LI> <LI><xtag-item1>D2=31</xtag-item1></LI>
<LI><xtag-item1>D4=52</xtag-item1></LI> <LI><xtag-item1>D3=34</xtag-item1></LI>
<LI><xtag-item1>D5=33</xtag-item1></LI> <LI><xtag-item1>D4=68</xtag-item1></LI>
<LI><xtag-item1>D6=61</xtag-item1></LI> <LI><xtag-item1>D5=44</xtag-item1></LI>
<LI><xtag-item1>D6=76</xtag-item1></LI>
<LI><xtag-item1>DMUX=15</xtag-item1></LI> <LI><xtag-item1>DMUX=15</xtag-item1></LI>
<LI><xtag-item1>DQ=32</xtag-item1></LI> <LI><xtag-item1>DQ=42</xtag-item1></LI>
<LI><xtag-item1>DX=5</xtag-item1></LI> <LI><xtag-item1>DX=10</xtag-item1></LI>
<LI><xtag-item1>SR=19</xtag-item1></LI> <LI><xtag-item1>SR=33</xtag-item1></LI>
</UL> </UL>
</TD> </TD>
<TD> <TD>
...@@ -576,95 +577,98 @@ ...@@ -576,95 +577,98 @@
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name> <xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>A=2</xtag-item1></LI> <LI><xtag-item1>A=2</xtag-item1></LI>
<LI><xtag-item1>A1=2</xtag-item1></LI> <LI><xtag-item1>A1=3</xtag-item1></LI>
<LI><xtag-item1>A2=2</xtag-item1></LI> <LI><xtag-item1>A2=3</xtag-item1></LI>
<LI><xtag-item1>A3=2</xtag-item1></LI> <LI><xtag-item1>A3=3</xtag-item1></LI>
<LI><xtag-item1>A4=2</xtag-item1></LI> <LI><xtag-item1>A4=3</xtag-item1></LI>
<LI><xtag-item1>A5=2</xtag-item1></LI> <LI><xtag-item1>A5=3</xtag-item1></LI>
<LI><xtag-item1>A6=2</xtag-item1></LI> <LI><xtag-item1>A6=3</xtag-item1></LI>
<LI><xtag-item1>AI=1</xtag-item1></LI> <LI><xtag-item1>AI=2</xtag-item1></LI>
<LI><xtag-item1>AMUX=1</xtag-item1></LI> <LI><xtag-item1>AMUX=1</xtag-item1></LI>
<LI><xtag-item1>AQ=1</xtag-item1></LI>
<LI><xtag-item1>AX=2</xtag-item1></LI> <LI><xtag-item1>AX=2</xtag-item1></LI>
<LI><xtag-item1>B=2</xtag-item1></LI> <LI><xtag-item1>B=2</xtag-item1></LI>
<LI><xtag-item1>B1=2</xtag-item1></LI> <LI><xtag-item1>B1=3</xtag-item1></LI>
<LI><xtag-item1>B2=2</xtag-item1></LI> <LI><xtag-item1>B2=3</xtag-item1></LI>
<LI><xtag-item1>B3=2</xtag-item1></LI> <LI><xtag-item1>B3=3</xtag-item1></LI>
<LI><xtag-item1>B4=2</xtag-item1></LI> <LI><xtag-item1>B4=3</xtag-item1></LI>
<LI><xtag-item1>B5=2</xtag-item1></LI> <LI><xtag-item1>B5=3</xtag-item1></LI>
<LI><xtag-item1>B6=2</xtag-item1></LI> <LI><xtag-item1>B6=3</xtag-item1></LI>
<LI><xtag-item1>BI=1</xtag-item1></LI> <LI><xtag-item1>BI=2</xtag-item1></LI>
<LI><xtag-item1>BMUX=1</xtag-item1></LI> <LI><xtag-item1>BMUX=1</xtag-item1></LI>
<LI><xtag-item1>BQ=1</xtag-item1></LI>
<LI><xtag-item1>BX=1</xtag-item1></LI> <LI><xtag-item1>BX=1</xtag-item1></LI>
<LI><xtag-item1>C=1</xtag-item1></LI> <LI><xtag-item1>C=1</xtag-item1></LI>
<LI><xtag-item1>C1=3</xtag-item1></LI> <LI><xtag-item1>C1=4</xtag-item1></LI>
<LI><xtag-item1>C2=3</xtag-item1></LI> <LI><xtag-item1>C2=4</xtag-item1></LI>
<LI><xtag-item1>C3=3</xtag-item1></LI> <LI><xtag-item1>C3=4</xtag-item1></LI>
<LI><xtag-item1>C4=3</xtag-item1></LI> <LI><xtag-item1>C4=4</xtag-item1></LI>
<LI><xtag-item1>C5=3</xtag-item1></LI> <LI><xtag-item1>C5=4</xtag-item1></LI>
<LI><xtag-item1>C6=3</xtag-item1></LI> <LI><xtag-item1>C6=4</xtag-item1></LI>
<LI><xtag-item1>CE=4</xtag-item1></LI> <LI><xtag-item1>CE=4</xtag-item1></LI>
<LI><xtag-item1>CI=2</xtag-item1></LI> <LI><xtag-item1>CI=3</xtag-item1></LI>
<LI><xtag-item1>CLK=4</xtag-item1></LI> <LI><xtag-item1>CLK=4</xtag-item1></LI>
<LI><xtag-item1>CMUX=1</xtag-item1></LI> <LI><xtag-item1>CMUX=1</xtag-item1></LI>
<LI><xtag-item1>CQ=1</xtag-item1></LI> <LI><xtag-item1>CQ=2</xtag-item1></LI>
<LI><xtag-item1>CX=2</xtag-item1></LI> <LI><xtag-item1>CX=2</xtag-item1></LI>
<LI><xtag-item1>D1=4</xtag-item1></LI> <LI><xtag-item1>D=1</xtag-item1></LI>
<LI><xtag-item1>D2=4</xtag-item1></LI> <LI><xtag-item1>D1=3</xtag-item1></LI>
<LI><xtag-item1>D3=4</xtag-item1></LI> <LI><xtag-item1>D2=3</xtag-item1></LI>
<LI><xtag-item1>D3=3</xtag-item1></LI>
<LI><xtag-item1>D4=4</xtag-item1></LI> <LI><xtag-item1>D4=4</xtag-item1></LI>
<LI><xtag-item1>D5=4</xtag-item1></LI> <LI><xtag-item1>D5=3</xtag-item1></LI>
<LI><xtag-item1>D6=4</xtag-item1></LI> <LI><xtag-item1>D6=4</xtag-item1></LI>
<LI><xtag-item1>DI=3</xtag-item1></LI> <LI><xtag-item1>DI=2</xtag-item1></LI>
<LI><xtag-item1>DMUX=1</xtag-item1></LI> <LI><xtag-item1>DMUX=1</xtag-item1></LI>
<LI><xtag-item1>DQ=2</xtag-item1></LI> <LI><xtag-item1>DQ=2</xtag-item1></LI>
<LI><xtag-item1>DX=2</xtag-item1></LI> <LI><xtag-item1>DX=3</xtag-item1></LI>
</UL> </UL>
</xtag-group> </xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name> <xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL> <UL>
<LI><xtag-item1>A=117</xtag-item1></LI> <LI><xtag-item1>A=103</xtag-item1></LI>
<LI><xtag-item1>A1=107</xtag-item1></LI> <LI><xtag-item1>A1=91</xtag-item1></LI>
<LI><xtag-item1>A2=152</xtag-item1></LI> <LI><xtag-item1>A2=129</xtag-item1></LI>
<LI><xtag-item1>A3=189</xtag-item1></LI> <LI><xtag-item1>A3=168</xtag-item1></LI>
<LI><xtag-item1>A4=205</xtag-item1></LI> <LI><xtag-item1>A4=184</xtag-item1></LI>
<LI><xtag-item1>A5=204</xtag-item1></LI> <LI><xtag-item1>A5=188</xtag-item1></LI>
<LI><xtag-item1>A6=206</xtag-item1></LI> <LI><xtag-item1>A6=192</xtag-item1></LI>
<LI><xtag-item1>AMUX=51</xtag-item1></LI> <LI><xtag-item1>AMUX=45</xtag-item1></LI>
<LI><xtag-item1>AQ=165</xtag-item1></LI> <LI><xtag-item1>AQ=156</xtag-item1></LI>
<LI><xtag-item1>AX=66</xtag-item1></LI> <LI><xtag-item1>AX=55</xtag-item1></LI>
<LI><xtag-item1>B=84</xtag-item1></LI> <LI><xtag-item1>B=71</xtag-item1></LI>
<LI><xtag-item1>B1=70</xtag-item1></LI> <LI><xtag-item1>B1=72</xtag-item1></LI>
<LI><xtag-item1>B2=117</xtag-item1></LI> <LI><xtag-item1>B2=103</xtag-item1></LI>
<LI><xtag-item1>B3=144</xtag-item1></LI> <LI><xtag-item1>B3=131</xtag-item1></LI>
<LI><xtag-item1>B4=153</xtag-item1></LI> <LI><xtag-item1>B4=139</xtag-item1></LI>
<LI><xtag-item1>B5=158</xtag-item1></LI> <LI><xtag-item1>B5=146</xtag-item1></LI>
<LI><xtag-item1>B6=155</xtag-item1></LI> <LI><xtag-item1>B6=141</xtag-item1></LI>
<LI><xtag-item1>BMUX=38</xtag-item1></LI> <LI><xtag-item1>BMUX=37</xtag-item1></LI>
<LI><xtag-item1>BQ=136</xtag-item1></LI> <LI><xtag-item1>BQ=126</xtag-item1></LI>
<LI><xtag-item1>BX=64</xtag-item1></LI> <LI><xtag-item1>BX=55</xtag-item1></LI>
<LI><xtag-item1>C=55</xtag-item1></LI> <LI><xtag-item1>C=55</xtag-item1></LI>
<LI><xtag-item1>C1=79</xtag-item1></LI> <LI><xtag-item1>C1=75</xtag-item1></LI>
<LI><xtag-item1>C2=94</xtag-item1></LI> <LI><xtag-item1>C2=95</xtag-item1></LI>
<LI><xtag-item1>C3=122</xtag-item1></LI> <LI><xtag-item1>C3=120</xtag-item1></LI>
<LI><xtag-item1>C4=133</xtag-item1></LI> <LI><xtag-item1>C4=131</xtag-item1></LI>
<LI><xtag-item1>C5=139</xtag-item1></LI> <LI><xtag-item1>C5=138</xtag-item1></LI>
<LI><xtag-item1>C6=134</xtag-item1></LI> <LI><xtag-item1>C6=133</xtag-item1></LI>
<LI><xtag-item1>CE=112</xtag-item1></LI> <LI><xtag-item1>CE=104</xtag-item1></LI>
<LI><xtag-item1>CLK=218</xtag-item1></LI> <LI><xtag-item1>CLK=195</xtag-item1></LI>
<LI><xtag-item1>CMUX=31</xtag-item1></LI> <LI><xtag-item1>CMUX=34</xtag-item1></LI>
<LI><xtag-item1>CQ=141</xtag-item1></LI> <LI><xtag-item1>CQ=134</xtag-item1></LI>
<LI><xtag-item1>CX=59</xtag-item1></LI> <LI><xtag-item1>CX=52</xtag-item1></LI>
<LI><xtag-item1>D=88</xtag-item1></LI> <LI><xtag-item1>D=83</xtag-item1></LI>
<LI><xtag-item1>D1=65</xtag-item1></LI> <LI><xtag-item1>D1=68</xtag-item1></LI>
<LI><xtag-item1>D2=101</xtag-item1></LI> <LI><xtag-item1>D2=100</xtag-item1></LI>
<LI><xtag-item1>D3=128</xtag-item1></LI> <LI><xtag-item1>D3=129</xtag-item1></LI>
<LI><xtag-item1>D4=140</xtag-item1></LI> <LI><xtag-item1>D4=140</xtag-item1></LI>
<LI><xtag-item1>D5=150</xtag-item1></LI> <LI><xtag-item1>D5=143</xtag-item1></LI>
<LI><xtag-item1>D6=150</xtag-item1></LI> <LI><xtag-item1>D6=144</xtag-item1></LI>
<LI><xtag-item1>DMUX=46</xtag-item1></LI> <LI><xtag-item1>DMUX=49</xtag-item1></LI>
<LI><xtag-item1>DQ=124</xtag-item1></LI> <LI><xtag-item1>DQ=123</xtag-item1></LI>
<LI><xtag-item1>DX=60</xtag-item1></LI> <LI><xtag-item1>DX=58</xtag-item1></LI>
<LI><xtag-item1>SR=164</xtag-item1></LI> <LI><xtag-item1>SR=143</xtag-item1></LI>
</UL> </UL>
</TD> </TD>
<TD> <TD>
...@@ -752,13 +756,19 @@ ...@@ -752,13 +756,19 @@
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI> <LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI> <LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI> <LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
</xtag-section></UL></TD></TR> </xtag-section></UL></TD></TR>
</TABLE> </TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR> &nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR>
<tr> <tr>
<td><xtag-program-name>_impact</xtag-program-name></td> <td><xtag-program-name>_impact</xtag-program-name></td>
<td><xtag-total-run-started>2</xtag-total-run-started></td> <td><xtag-total-run-started>3</xtag-total-run-started></td>
<td><xtag-total-run-finished>0</xtag-total-run-finished></td> <td><xtag-total-run-finished>2</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td> <td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
...@@ -767,8 +777,8 @@ ...@@ -767,8 +777,8 @@
</tr> </tr>
<tr> <tr>
<td><xtag-program-name>bitgen</xtag-program-name></td> <td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td> <td><xtag-total-run-started>2</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td> <td><xtag-total-run-finished>2</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td> <td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td> <td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td> <td><xtag-total-internal-error>0</xtag-total-internal-error></td>
...@@ -777,8 +787,8 @@ ...@@ -777,8 +787,8 @@
</tr> </tr>
<tr> <tr>
<td><xtag-program-name>map</xtag-program-name></td> <td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td> <td><xtag-total-run-started>2</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td> <td><xtag-total-run-finished>2</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td> <td><xtag-total-error>0</xtag-total-error></td>
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...@@ -787,8 +797,8 @@ ...@@ -787,8 +797,8 @@
</tr> </tr>
<tr> <tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td> <td><xtag-program-name>ngdbuild</xtag-program-name></td>
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...@@ -797,8 +807,8 @@ ...@@ -797,8 +807,8 @@
</tr> </tr>
<tr> <tr>
<td><xtag-program-name>par</xtag-program-name></td> <td><xtag-program-name>par</xtag-program-name></td>
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...@@ -807,8 +817,8 @@ ...@@ -807,8 +817,8 @@
</tr> </tr>
<tr> <tr>
<td><xtag-program-name>trce</xtag-program-name></td> <td><xtag-program-name>trce</xtag-program-name></td>
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...@@ -817,8 +827,8 @@ ...@@ -817,8 +827,8 @@
</tr> </tr>
<tr> <tr>
<td><xtag-program-name>xst</xtag-program-name></td> <td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td> <td><xtag-total-run-started>2</xtag-total-run-started></td>
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...@@ -850,7 +860,7 @@ ...@@ -850,7 +860,7 @@
<TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2010-12-15T15:02:16</xtag-design-property-value></TD> <TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2010-12-15T15:02:16</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>F6031676C5FE434A8E9F8A1057A8E48F</xtag-design-property-value></TD> </TR><TR><TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>F6031676C5FE434A8E9F8A1057A8E48F</xtag-design-property-value></TD>
<TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>6</xtag-process-property-value></TD> <TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>7</xtag-process-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD> </TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD> <TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD>
...@@ -878,13 +888,13 @@ ...@@ -878,13 +888,13 @@
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR> <TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFG</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>3</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>3</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>189</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>191</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>99</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>101</xtag-preunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDPE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDPE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>135</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>135</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>313</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>325</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>26</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>26</xtag-preunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
...@@ -897,18 +907,18 @@ ...@@ -897,18 +907,18 @@
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>29</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>29</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IOBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>32</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_IOBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>32</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IOBUFDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_IOBUFDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>163</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>181</xtag-preunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>163</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>166</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>121</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>130</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>112</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>113</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>148</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>146</xtag-preunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>307</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>299</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>186</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>204</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-preunisim-param-name>=<xtag-preunisim-param-value>18</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>152</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>152</xtag-preunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
...@@ -918,18 +928,18 @@ ...@@ -918,18 +928,18 @@
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_RAM32M</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_RAM32M</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_SRLC16E</xtag-preunisim-param-name>=<xtag-preunisim-param-value>3</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_SRLC16E</xtag-preunisim-param-name>=<xtag-preunisim-param-value>5</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>181</xtag-preunisim-param-value></TD> <TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>199</xtag-preunisim-param-value></TD>
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR> <TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>189</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>191</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>99</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>101</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDPE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDPE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>135</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>135</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDRE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>313</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDRE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>325</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>26</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>26</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDSE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>33</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDSE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>33</xtag-postunisim-param-value></TD>
</TR> </TR>
...@@ -942,18 +952,18 @@ ...@@ -942,18 +952,18 @@
<TR> <TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFGDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>6</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFGDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>6</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>29</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>29</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>163</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>181</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>163</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>166</xtag-postunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>121</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>130</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>112</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>113</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>148</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>146</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>307</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT6</xtag-postunisim-param-name>=<xtag-postunisim-param-value>299</xtag-postunisim-param-value></TD>
</TR> </TR>
<TR> <TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>186</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>204</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-postunisim-param-name>=<xtag-postunisim-param-value>18</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>152</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>152</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD>
</TR> </TR>
...@@ -961,11 +971,11 @@ ...@@ -961,11 +971,11 @@
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-postunisim-param-name>=<xtag-postunisim-param-value>65</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-postunisim-param-name>=<xtag-postunisim-param-value>65</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFTDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFTDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_RAM32M</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_RAM32M</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_SRLC16E</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_SRLC16E</xtag-postunisim-param-name>=<xtag-postunisim-param-value>5</xtag-postunisim-param-value></TD>
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<TR> <TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_TS_TIMESPEC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_TS_TIMESPEC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_VCC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_VCC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>181</xtag-postunisim-param-value></TD> <TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>199</xtag-postunisim-param-value></TD>
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&nbsp;<BR></BODY></HTML> &nbsp;<BR></BODY></HTML>
trunk/firmware/XilinxISE/SystemFpga/webtalk.log
View file @ 265c6bd0
...@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. ...@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information Project Information
-------------------- --------------------
ProjectID=F6031676C5FE434A8E9F8A1057A8E48F ProjectID=F6031676C5FE434A8E9F8A1057A8E48F
ProjectIteration=6 ProjectIteration=7
WebTalk Summary WebTalk Summary
---------------- ----------------
...@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled. ...@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON. INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON. INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-17T11:13:36. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-20T08:28:11. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
trunk/firmware/XilinxISE/SystemFpga/webtalk_pn.xml
View file @ 265c6bd0
...@@ -3,10 +3,10 @@ ...@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Fri Dec 17 11:13:08 2010"> <application name="pn" timeStamp="Mon Dec 20 08:27:43 2010">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/> <property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/>
<property name="ProjectIteration" value="6" type="project"/> <property name="ProjectIteration" value="7" type="project"/>
<property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/> <property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/> <property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/>
</section> </section>
...@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq ...@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/> <property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/>
<property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/> <property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/>
<property name="PROP_intWbtProjectIteration" value="6" type="process"/> <property name="PROP_intWbtProjectIteration" value="7" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> <property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> <property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/> <property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
......
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