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Commit 777894d8 authored by Andrea Boccardi's avatar Andrea Boccardi
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trunk/firmware/XilinxISE/SystemFpga/SFpga.bld
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Release 12.3 ngdbuild M.70d (nt)
Release 12.3 ngdbuild M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc
SFpga.ngd
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3
SFpga.ngc SFpga.ngd
Reading NGO file "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc" ...
Gathering constraint information from source properties...
......@@ -49,10 +49,10 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 16
Total memory usage is 87012 kilobytes
Total memory usage is 155028 kilobytes
Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 5 sec
Total CPU time to NGDBUILD completion: 5 sec
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "SFpga.bld"...
trunk/firmware/XilinxISE/SystemFpga/SFpga.cmd_log
View file @ 777894d8
......@@ -210,3 +210,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
trunk/firmware/XilinxISE/SystemFpga/SFpga.ncd
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trunk/firmware/XilinxISE/SystemFpga/SFpga.ngc
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trunk/firmware/XilinxISE/SystemFpga/SFpga.ngd
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trunk/firmware/XilinxISE/SystemFpga/SFpga.ngr
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trunk/firmware/XilinxISE/SystemFpga/SFpga.pad
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Release 12.3 - par M.70d (nt)
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Jan 28 11:55:01 2011
Fri Jan 28 15:08:32 2011
# NOTE: This file is designed to be imported into a spreadsheet program
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.par
View file @ 777894d8
Release 12.3 par M.70d (nt)
Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
BQPLV2:: Fri Jan 28 11:49:02 2011
PCBE13225:: Fri Jan 28 15:05:49 2011
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
......@@ -26,7 +26,7 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 851 out of 92,152 1%
Number of Slice LUTs: 849 out of 92,152 1%
Number used as logic: 823 out of 92,152 1%
Number using O6 output only: 616
Number using O5 output only: 83
......@@ -42,17 +42,17 @@ Slice Logic Utilization:
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 2
Number used exclusively as route-thrus: 14
Number with same-slice register load: 9
Number used exclusively as route-thrus: 12
Number with same-slice register load: 7
Number with same-slice carry load: 5
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 392 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,060
Number with an unused Flip Flop: 372 out of 1,060 35%
Number with an unused LUT: 209 out of 1,060 19%
Number of fully used LUT-FF pairs: 479 out of 1,060 45%
Number of occupied Slices: 386 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,046
Number with an unused Flip Flop: 356 out of 1,046 34%
Number with an unused LUT: 197 out of 1,046 18%
Number of fully used LUT-FF pairs: 493 out of 1,046 47%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
......@@ -99,8 +99,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 20 secs
Finished initial Timing Analysis. REAL time: 20 secs
Starting initial Timing Analysis. REAL time: 9 secs
Finished initial Timing Analysis. REAL time: 9 secs
WARNING:Par:288 - The signal DdsRamSwpOvr_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PcbRev_ib8<0>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -154,29 +154,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
Starting Router
Phase 1 : 4748 unrouted; REAL time: 23 secs
Phase 1 : 4750 unrouted; REAL time: 11 secs
Phase 2 : 4243 unrouted; REAL time: 30 secs
Phase 2 : 4245 unrouted; REAL time: 14 secs
Phase 3 : 1611 unrouted; REAL time: 5 mins 41 secs
Phase 3 : 1604 unrouted; REAL time: 2 mins 34 secs
Phase 4 : 1611 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 52 secs
Phase 4 : 1604 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 39 secs
Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs
Total REAL time to Router completion: 5 mins 56 secs
Total CPU time to Router completion: 5 mins 54 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Total REAL time to Router completion: 2 mins 41 secs
Total CPU time to Router completion: 2 mins 40 secs
Partition Implementation Status
-------------------------------
......@@ -194,14 +194,14 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| VcTcXo_ik_IBUF_BUFG | BUFGMUX_X3Y16| No | 203 | 0.325 | 1.693 |
| VcTcXo_ik_IBUF_BUFG | BUFGMUX_X3Y16| No | 204 | 0.325 | 1.693 |
+---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 6 | 0.009 | 1.690 |
+---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.189 | 1.692 |
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.190 | 1.693 |
+---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | |
| e/Stb_oq | Local| | 17 | 0.000 | 2.404 |
| e/Stb_oq | Local| | 17 | 0.000 | 2.145 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -220,7 +220,7 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 3.649ns| 4.684ns| 0| 0
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 3.404ns| 4.929ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.439ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | MINPERIOD | 5.833ns| 2.500ns| 0| 0
......@@ -241,10 +241,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 49 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 5 mins 59 secs
Total CPU time to PAR completion: 5 mins 58 secs
Total REAL time to PAR completion: 2 mins 43 secs
Total CPU time to PAR completion: 2 mins 42 secs
Peak Memory Usage: 366 MB
Peak Memory Usage: 559 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.pcf
View file @ 777894d8
//! **************************************************************************
// Written by: Map M.70d on Fri Jan 28 11:48:58 2011
// Written by: Map M.70d on Fri Jan 28 15:05:46 2011
//! **************************************************************************
SCHEMATIC START;
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.ptwx
View file @ 777894d8
......@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="3.649" best="4.684" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.439" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="6.152" best="2.181" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.464" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="3.404" best="4.929" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.439" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="6.152" best="2.181" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.464" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
trunk/firmware/XilinxISE/SystemFpga/SFpga.syr
View file @ 777894d8
Release 12.3 - xst M.70d (nt)
Release 12.3 - xst M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs
Total CPU time to Xst completion: 0.08 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs
Total CPU time to Xst completion: 0.08 secs
--> Reading design: SFpga.prj
......@@ -1032,7 +1032,7 @@ Delay: 2.365ns (Levels of Logic = 25)
=========================================================================
Timing constraint: Default period analysis for Clock 'VcTcXo_ik'
Clock period: 6.551ns (frequency: 152.654MHz)
Total number of paths / destination ports: 26774 / 1542
Total number of paths / destination ports: 26773 / 1542
-------------------------------------------------------------------------
Delay: 6.551ns (Levels of Logic = 10)
Source: i_Core/i_SpiMasterWB/Config2_qb32_2 (FF)
......@@ -1121,7 +1121,7 @@ Offset: 12.206ns (Levels of Logic = 10)
LUT6:I1->O 6 0.254 0.973 i_Core/i_VmeInterface/GapError1 (i_Core/i_VmeInterface/GapError)
LUT4:I1->O 1 0.235 1.035 i_Core/i_VmeInterface/Mmux_BoardBaseAddr_b521 (i_Core/i_VmeInterface/BoardBaseAddr_b5<1>)
LUT6:I0->O 1 0.254 0.808 i_Core/i_VmeInterface/ValidRWBA_a81 (i_Core/i_VmeInterface/ValidRWBA_a8)
LUT6:I3->O 1 0.235 1.035 i_Core/i_VmeInterface/ValidRWBA_a83_SW0 (N294)
LUT6:I3->O 1 0.235 1.035 i_Core/i_VmeInterface/ValidRWBA_a83_SW0 (N296)
LUT6:I0->O 3 0.254 0.879 i_Core/i_VmeInterface/ValidRWBA_a83 (i_Core/i_VmeInterface/ValidRWBA_a)
LUT4:I1->O 1 0.235 0.580 i_Core/i_VmeInterface/State_q_FSM_FFd2-In1_SW0 (N42)
LUT6:I5->O 8 0.254 1.031 i_Core/i_VmeInterface/State_q_FSM_FFd2-In1 (N3)
......@@ -1254,12 +1254,12 @@ i_Core/i_VmeInterface/Stb_oq| 2.049| | | |
=========================================================================
Total REAL time to Xst completion: 28.00 secs
Total CPU time to Xst completion: 27.13 secs
Total REAL time to Xst completion: 18.00 secs
Total CPU time to Xst completion: 17.41 secs
-->
Total memory usage is 155300 kilobytes
Total memory usage is 280792 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 129 ( 0 filtered)
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.twr
View file @ 777894d8
--------------------------------------------------------------------------------
Release 12.3 Trace (nt)
Release 12.3 Trace (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
-n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
Design file: SFpga.ncd
Physical constraint file: SFpga.pcf
......@@ -612,17 +612,17 @@ Timing constraint: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH
129 paths analyzed, 97 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 4.684ns.
Minimum period is 4.929ns.
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_20 (SLICE_X82Y89.CE), 2 paths
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_28 (SLICE_X64Y84.CE), 2 paths
--------------------------------------------------------------------------------
Slack (setup path): 3.649ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 3.404ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_20 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_28 (FF)
Requirement: 8.333ns
Data Path Delay: 4.435ns (Levels of Logic = 1)
Clock Path Skew: -0.214ns (0.855 - 1.069)
Data Path Delay: 4.865ns (Levels of Logic = 1)
Clock Path Skew: -0.029ns (1.040 - 1.069)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -633,7 +633,7 @@ Slack (setup path): 3.649ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_20
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_28
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
......@@ -642,20 +642,20 @@ Slack (setup path): 3.649ns (requirement - (data path - clock path skew + un
SLICE_X71Y99.A4 net (fanout=1) 1.569 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X71Y99.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X82Y89.CE net (fanout=7) 1.817 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X82Y89.CLK Tceck 0.314 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_20
SLICE_X64Y84.CE net (fanout=7) 2.248 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X64Y84.CLK Tceck 0.313 i_Core/i_Slv2SerWB/Dat_xb32<31>
i_Core/i_Slv2SerWB/Dat_xb32_28
------------------------------------------------- ---------------------------
Total 4.435ns (1.049ns logic, 3.386ns route)
(23.7% logic, 76.3% route)
Total 4.865ns (1.048ns logic, 3.817ns route)
(21.5% logic, 78.5% route)
--------------------------------------------------------------------------------
Slack (setup path): 3.710ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 3.465ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_1 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_20 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_28 (FF)
Requirement: 8.333ns
Data Path Delay: 4.374ns (Levels of Logic = 1)
Clock Path Skew: -0.214ns (0.855 - 1.069)
Data Path Delay: 4.804ns (Levels of Logic = 1)
Clock Path Skew: -0.029ns (1.040 - 1.069)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -666,7 +666,7 @@ Slack (setup path): 3.710ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_20
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_28
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
......@@ -675,23 +675,23 @@ Slack (setup path): 3.710ns (requirement - (data path - clock path skew + un
SLICE_X71Y99.A5 net (fanout=2) 1.508 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X71Y99.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X82Y89.CE net (fanout=7) 1.817 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X82Y89.CLK Tceck 0.314 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_20
SLICE_X64Y84.CE net (fanout=7) 2.248 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X64Y84.CLK Tceck 0.313 i_Core/i_Slv2SerWB/Dat_xb32<31>
i_Core/i_Slv2SerWB/Dat_xb32_28
------------------------------------------------- ---------------------------
Total 4.374ns (1.049ns logic, 3.325ns route)
(24.0% logic, 76.0% route)
Total 4.804ns (1.048ns logic, 3.756ns route)
(21.8% logic, 78.2% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_23 (SLICE_X82Y89.CE), 2 paths
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_30 (SLICE_X64Y84.CE), 2 paths
--------------------------------------------------------------------------------
Slack (setup path): 3.672ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 3.448ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_23 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_30 (FF)
Requirement: 8.333ns
Data Path Delay: 4.412ns (Levels of Logic = 1)
Clock Path Skew: -0.214ns (0.855 - 1.069)
Data Path Delay: 4.821ns (Levels of Logic = 1)
Clock Path Skew: -0.029ns (1.040 - 1.069)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -702,7 +702,7 @@ Slack (setup path): 3.672ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_23
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_30
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
......@@ -711,20 +711,20 @@ Slack (setup path): 3.672ns (requirement - (data path - clock path skew + un
SLICE_X71Y99.A4 net (fanout=1) 1.569 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X71Y99.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X82Y89.CE net (fanout=7) 1.817 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X82Y89.CLK Tceck 0.291 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_23
SLICE_X64Y84.CE net (fanout=7) 2.248 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X64Y84.CLK Tceck 0.269 i_Core/i_Slv2SerWB/Dat_xb32<31>
i_Core/i_Slv2SerWB/Dat_xb32_30
------------------------------------------------- ---------------------------
Total 4.412ns (1.026ns logic, 3.386ns route)
(23.3% logic, 76.7% route)
Total 4.821ns (1.004ns logic, 3.817ns route)
(20.8% logic, 79.2% route)
--------------------------------------------------------------------------------
Slack (setup path): 3.733ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 3.509ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_1 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_23 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_30 (FF)
Requirement: 8.333ns
Data Path Delay: 4.351ns (Levels of Logic = 1)
Clock Path Skew: -0.214ns (0.855 - 1.069)
Data Path Delay: 4.760ns (Levels of Logic = 1)
Clock Path Skew: -0.029ns (1.040 - 1.069)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -735,7 +735,7 @@ Slack (setup path): 3.733ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_23
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_30
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
......@@ -744,23 +744,23 @@ Slack (setup path): 3.733ns (requirement - (data path - clock path skew + un
SLICE_X71Y99.A5 net (fanout=2) 1.508 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X71Y99.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X82Y89.CE net (fanout=7) 1.817 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X82Y89.CLK Tceck 0.291 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_23
SLICE_X64Y84.CE net (fanout=7) 2.248 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X64Y84.CLK Tceck 0.269 i_Core/i_Slv2SerWB/Dat_xb32<31>
i_Core/i_Slv2SerWB/Dat_xb32_30
------------------------------------------------- ---------------------------
Total 4.351ns (1.026ns logic, 3.325ns route)
(23.6% logic, 76.4% route)
Total 4.760ns (1.004ns logic, 3.756ns route)
(21.1% logic, 78.9% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_22 (SLICE_X82Y89.CE), 2 paths
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_31 (SLICE_X64Y84.CE), 2 paths
--------------------------------------------------------------------------------
Slack (setup path): 3.674ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 3.451ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_22 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_31 (FF)
Requirement: 8.333ns
Data Path Delay: 4.410ns (Levels of Logic = 1)
Clock Path Skew: -0.214ns (0.855 - 1.069)
Data Path Delay: 4.818ns (Levels of Logic = 1)
Clock Path Skew: -0.029ns (1.040 - 1.069)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -771,7 +771,7 @@ Slack (setup path): 3.674ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_22
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_31
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
......@@ -780,20 +780,20 @@ Slack (setup path): 3.674ns (requirement - (data path - clock path skew + un
SLICE_X71Y99.A4 net (fanout=1) 1.569 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X71Y99.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X82Y89.CE net (fanout=7) 1.817 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X82Y89.CLK Tceck 0.289 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_22
SLICE_X64Y84.CE net (fanout=7) 2.248 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X64Y84.CLK Tceck 0.266 i_Core/i_Slv2SerWB/Dat_xb32<31>
i_Core/i_Slv2SerWB/Dat_xb32_31
------------------------------------------------- ---------------------------
Total 4.410ns (1.024ns logic, 3.386ns route)
(23.2% logic, 76.8% route)
Total 4.818ns (1.001ns logic, 3.817ns route)
(20.8% logic, 79.2% route)
--------------------------------------------------------------------------------
Slack (setup path): 3.735ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 3.512ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_1 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_22 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_31 (FF)
Requirement: 8.333ns
Data Path Delay: 4.349ns (Levels of Logic = 1)
Clock Path Skew: -0.214ns (0.855 - 1.069)
Data Path Delay: 4.757ns (Levels of Logic = 1)
Clock Path Skew: -0.029ns (1.040 - 1.069)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -804,7 +804,7 @@ Slack (setup path): 3.735ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_22
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_31
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
......@@ -813,96 +813,96 @@ Slack (setup path): 3.735ns (requirement - (data path - clock path skew + un
SLICE_X71Y99.A5 net (fanout=2) 1.508 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X71Y99.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X82Y89.CE net (fanout=7) 1.817 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X82Y89.CLK Tceck 0.289 i_Core/i_Slv2SerWB/Dat_xb32<23>
i_Core/i_Slv2SerWB/Dat_xb32_22
SLICE_X64Y84.CE net (fanout=7) 2.248 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X64Y84.CLK Tceck 0.266 i_Core/i_Slv2SerWB/Dat_xb32<31>
i_Core/i_Slv2SerWB/Dat_xb32_31
------------------------------------------------- ---------------------------
Total 4.349ns (1.024ns logic, 3.325ns route)
(23.5% logic, 76.5% route)
Total 4.757ns (1.001ns logic, 3.756ns route)
(21.0% logic, 79.0% route)
--------------------------------------------------------------------------------
Hold Paths: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%;
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_14 (SLICE_X78Y92.CX), 1 path
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_10 (SLICE_X78Y97.CX), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.439ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_14 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_14 (FF)
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_10 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_10 (FF)
Requirement: 0.000ns
Data Path Delay: 0.440ns (Levels of Logic = 0)
Clock Path Skew: 0.001ns (0.041 - 0.040)
Clock Path Skew: 0.001ns (0.043 - 0.042)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_14 to i_Core/i_Slv2SerWB/Dat_xb32_14
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_10 to i_Core/i_Slv2SerWB/Dat_xb32_10
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X79Y93.CQ Tcko 0.198 i_Core/i_Slv2SerWB/DatInShReg_b32<15>
i_Core/i_Slv2SerWB/DatInShReg_b32_14
SLICE_X78Y92.CX net (fanout=2) 0.194 i_Core/i_Slv2SerWB/DatInShReg_b32<14>
SLICE_X78Y92.CLK Tckdi (-Th) -0.048 i_Core/i_Slv2SerWB/Dat_xb32<15>
i_Core/i_Slv2SerWB/Dat_xb32_14
SLICE_X79Y96.CQ Tcko 0.198 i_Core/i_Slv2SerWB/DatInShReg_b32<11>
i_Core/i_Slv2SerWB/DatInShReg_b32_10
SLICE_X78Y97.CX net (fanout=2) 0.194 i_Core/i_Slv2SerWB/DatInShReg_b32<10>
SLICE_X78Y97.CLK Tckdi (-Th) -0.048 i_Core/i_Slv2SerWB/Dat_xb32<11>
i_Core/i_Slv2SerWB/Dat_xb32_10
------------------------------------------------- ---------------------------
Total 0.440ns (0.246ns logic, 0.194ns route)
(55.9% logic, 44.1% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_10 (SLICE_X78Y97.CX), 1 path
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_11 (SLICE_X78Y97.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.441ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_10 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_10 (FF)
Slack (hold path): 0.439ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_11 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_11 (FF)
Requirement: 0.000ns
Data Path Delay: 0.442ns (Levels of Logic = 0)
Data Path Delay: 0.440ns (Levels of Logic = 0)
Clock Path Skew: 0.001ns (0.043 - 0.042)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_10 to i_Core/i_Slv2SerWB/Dat_xb32_10
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_11 to i_Core/i_Slv2SerWB/Dat_xb32_11
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X78Y96.CQ Tcko 0.200 i_Core/i_Slv2SerWB/DatInShReg_b32<11>
i_Core/i_Slv2SerWB/DatInShReg_b32_10
SLICE_X78Y97.CX net (fanout=2) 0.194 i_Core/i_Slv2SerWB/DatInShReg_b32<10>
SLICE_X79Y96.DQ Tcko 0.198 i_Core/i_Slv2SerWB/DatInShReg_b32<11>
i_Core/i_Slv2SerWB/DatInShReg_b32_11
SLICE_X78Y97.DX net (fanout=2) 0.194 i_Core/i_Slv2SerWB/DatInShReg_b32<11>
SLICE_X78Y97.CLK Tckdi (-Th) -0.048 i_Core/i_Slv2SerWB/Dat_xb32<11>
i_Core/i_Slv2SerWB/Dat_xb32_10
i_Core/i_Slv2SerWB/Dat_xb32_11
------------------------------------------------- ---------------------------
Total 0.442ns (0.248ns logic, 0.194ns route)
(56.1% logic, 43.9% route)
Total 0.440ns (0.246ns logic, 0.194ns route)
(55.9% logic, 44.1% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_11 (SLICE_X78Y97.DX), 1 path
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_9 (SLICE_X78Y97.BX), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.441ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_11 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_11 (FF)
Slack (hold path): 0.448ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_9 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_9 (FF)
Requirement: 0.000ns
Data Path Delay: 0.442ns (Levels of Logic = 0)
Data Path Delay: 0.449ns (Levels of Logic = 0)
Clock Path Skew: 0.001ns (0.043 - 0.042)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_11 to i_Core/i_Slv2SerWB/Dat_xb32_11
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_9 to i_Core/i_Slv2SerWB/Dat_xb32_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X78Y96.DQ Tcko 0.200 i_Core/i_Slv2SerWB/DatInShReg_b32<11>
i_Core/i_Slv2SerWB/DatInShReg_b32_11
SLICE_X78Y97.DX net (fanout=2) 0.194 i_Core/i_Slv2SerWB/DatInShReg_b32<11>
SLICE_X79Y96.BQ Tcko 0.198 i_Core/i_Slv2SerWB/DatInShReg_b32<11>
i_Core/i_Slv2SerWB/DatInShReg_b32_9
SLICE_X78Y97.BX net (fanout=2) 0.203 i_Core/i_Slv2SerWB/DatInShReg_b32<9>
SLICE_X78Y97.CLK Tckdi (-Th) -0.048 i_Core/i_Slv2SerWB/Dat_xb32<11>
i_Core/i_Slv2SerWB/Dat_xb32_11
i_Core/i_Slv2SerWB/Dat_xb32_9
------------------------------------------------- ---------------------------
Total 0.442ns (0.248ns logic, 0.194ns route)
(56.1% logic, 43.9% route)
Total 0.449ns (0.246ns logic, 0.203ns route)
(54.8% logic, 45.2% route)
--------------------------------------------------------------------------------
......@@ -919,17 +919,17 @@ Slack: 5.833ns (period - min period limit)
Slack: 7.853ns (period - min period limit)
Period: 8.333ns
Min period limit: 0.480ns (2083.333MHz) (Tcp)
Physical resource: i_Core/i_Slv2SerWB/DatInShReg_b32<31>/CLK
Logical resource: i_Core/i_Slv2SerWB/DatInShReg_b32_28/CK
Location pin: SLICE_X56Y84.CLK
Physical resource: i_Core/i_Slv2SerWB/Dat_xb32<31>/CLK
Logical resource: i_Core/i_Slv2SerWB/Dat_xb32_28/CK
Location pin: SLICE_X64Y84.CLK
Clock network: SysAppClk_ik_BUFGP
--------------------------------------------------------------------------------
Slack: 7.853ns (period - min period limit)
Period: 8.333ns
Min period limit: 0.480ns (2083.333MHz) (Tcp)
Physical resource: i_Core/i_Slv2SerWB/DatInShReg_b32<31>/CLK
Logical resource: i_Core/i_Slv2SerWB/DatInShReg_b32_29/CK
Location pin: SLICE_X56Y84.CLK
Physical resource: i_Core/i_Slv2SerWB/Dat_xb32<31>/CLK
Logical resource: i_Core/i_Slv2SerWB/Dat_xb32_29/CK
Location pin: SLICE_X64Y84.CLK
Clock network: SysAppClk_ik_BUFGP
--------------------------------------------------------------------------------
......@@ -964,7 +964,7 @@ Clock to Setup on destination clock SysAppClk_ik
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
SysAppClk_ik | 4.684| | | |
SysAppClk_ik | 4.929| | | |
---------------+---------+---------+---------+---------+
......@@ -976,20 +976,20 @@ Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 429 paths, 0 nets, and 127 connections
Design statistics:
Minimum period: 4.684ns{1} (Maximum frequency: 213.493MHz)
Minimum period: 4.929ns{1} (Maximum frequency: 202.881MHz)
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Fri Jan 28 11:55:25 2011
Analysis completed Fri Jan 28 15:08:44 2011
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 268 MB
Peak Memory Usage: 390 MB
trunk/firmware/XilinxISE/SystemFpga/SFpga.twx
View file @ 777894d8
......@@ -329,8 +329,8 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 12.3 Trace (nt)</twExecVer><twCopyright>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
<twReport><twHead anchorID="1"><twExecVer>Release 12.3 Trace (nt64)</twExecVer><twCopyright>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
-n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
</twCmdLine><twDesign>SFpga.ncd</twDesign><twDesignPath>SFpga.ncd</twDesignPath><twPCF>SFpga.pcf</twPCF><twPcfPath>SFpga.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="fgg676"><twDevName>xc6slx150t</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRODUCTION 1.12c 2010-09-15</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="3">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="4" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="TIMESPEC TS_Si57x_ik = PERIOD &quot;Si57x_ik&quot; 120 MHz HIGH 50%;" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.500</twMinPer></twConstHead><twPinLimitRpt anchorID="5"><twPinLimitBanner>Component Switching Limit Checks: TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="6" type="MINPERIOD" name="Tbcper_I" slack="5.833" period="8.333" constraintValue="8.333" deviceLimit="2.500" freqLimit="400.000" physResource="Si57x_BUFG/I0" logResource="Si57x_BUFG/I0" locationPin="BUFGMUX_X2Y4.I0" clockNet="Si57x"/><twPinLimit anchorID="7" type="MINPERIOD" name="Tcp" slack="7.858" period="8.333" constraintValue="8.333" deviceLimit="0.475" freqLimit="2105.263" physResource="i_Core/Si57xDivider_c&lt;3&gt;/CLK" logResource="i_Core/Si57xDivider_c_0/CK" locationPin="SLICE_X58Y99.CLK" clockNet="Si57x_BUFG"/><twPinLimit anchorID="8" type="MINPERIOD" name="Tcp" slack="7.858" period="8.333" constraintValue="8.333" deviceLimit="0.475" freqLimit="2105.263" physResource="i_Core/Si57xDivider_c&lt;3&gt;/CLK" logResource="i_Core/Si57xDivider_c_1/CK" locationPin="SLICE_X58Y99.CLK" clockNet="Si57x_BUFG"/></twPinLimitRpt></twConst><twConst anchorID="9" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="TIMESPEC TS_Si57x_ikn = PERIOD &quot;Si57x_ikn&quot; 120 MHz HIGH 50%;" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 120 MHz HIGH 50%;</twConstName><twItemCnt>300</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>80</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.500</twMinPer></twConstHead><twPathRptBanner iPaths="20" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/Si57xDivider_c_22 (SLICE_X58Y104.CIN), 20 paths
</twPathRptBanner><twPathRpt anchorID="10"><twConstPath anchorID="11" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.152</twSlack><twSrc BELType="FF">i_Core/Si57xDivider_c_0</twSrc><twDest BELType="FF">i_Core/Si57xDivider_c_22</twDest><twTotPathDel>2.122</twTotPathDel><twClkSkew dest = "0.244" src = "0.268">0.024</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/Si57xDivider_c_0</twSrc><twDest BELType='FF'>i_Core/Si57xDivider_c_22</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X58Y99.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X58Y99.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;3&gt;</twComp><twBEL>i_Core/Si57xDivider_c_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y99.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.397</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y99.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.472</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;3&gt;</twComp><twBEL>i_Core/Mcount_Si57xDivider_c_lut&lt;0&gt;_INV_0</twBEL><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;3&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y100.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>i_Core/Mcount_Si57xDivider_c_cy&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y100.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.091</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;7&gt;</twComp><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;7&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y101.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>i_Core/Mcount_Si57xDivider_c_cy&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y101.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.091</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;11&gt;</twComp><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;11&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y102.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>i_Core/Mcount_Si57xDivider_c_cy&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y102.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.091</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;15&gt;</twComp><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;15&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y103.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>i_Core/Mcount_Si57xDivider_c_cy&lt;15&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y103.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.091</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;19&gt;</twComp><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;19&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y104.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.082</twDelInfo><twComp>i_Core/Mcount_Si57xDivider_c_cy&lt;19&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y104.CLK</twSite><twDelType>Tcinck</twDelType><twDelInfo twEdge="twRising">0.319</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;23&gt;</twComp><twBEL>i_Core/Mcount_Si57xDivider_c_xor&lt;23&gt;</twBEL><twBEL>i_Core/Si57xDivider_c_22</twBEL></twPathDel><twLogDel>1.631</twLogDel><twRouteDel>0.491</twRouteDel><twTotDel>2.122</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>76.9</twPctLog><twPctRoute>23.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="12"><twConstPath anchorID="13" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.248</twSlack><twSrc BELType="FF">i_Core/Si57xDivider_c_4</twSrc><twDest BELType="FF">i_Core/Si57xDivider_c_22</twDest><twTotPathDel>2.028</twTotPathDel><twClkSkew dest = "0.244" src = "0.266">0.022</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/Si57xDivider_c_4</twSrc><twDest BELType='FF'>i_Core/Si57xDivider_c_22</twDest><twLogLvls>5</twLogLvls><twSrcSite>SLICE_X58Y100.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X58Y100.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;7&gt;</twComp><twBEL>i_Core/Si57xDivider_c_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y100.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.397</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;4&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y100.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.472</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;7&gt;</twComp><twBEL>i_Core/Si57xDivider_c&lt;4&gt;_rt</twBEL><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;7&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y101.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>i_Core/Mcount_Si57xDivider_c_cy&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y101.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.091</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;11&gt;</twComp><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;11&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y102.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>i_Core/Mcount_Si57xDivider_c_cy&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y102.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.091</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;15&gt;</twComp><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;15&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y103.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>i_Core/Mcount_Si57xDivider_c_cy&lt;15&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y103.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.091</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;19&gt;</twComp><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;19&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y104.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.082</twDelInfo><twComp>i_Core/Mcount_Si57xDivider_c_cy&lt;19&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y104.CLK</twSite><twDelType>Tcinck</twDelType><twDelInfo twEdge="twRising">0.319</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;23&gt;</twComp><twBEL>i_Core/Mcount_Si57xDivider_c_xor&lt;23&gt;</twBEL><twBEL>i_Core/Si57xDivider_c_22</twBEL></twPathDel><twLogDel>1.540</twLogDel><twRouteDel>0.488</twRouteDel><twTotDel>2.028</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>75.9</twPctLog><twPctRoute>24.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="14"><twConstPath anchorID="15" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>6.279</twSlack><twSrc BELType="FF">i_Core/Si57xDivider_c_3</twSrc><twDest BELType="FF">i_Core/Si57xDivider_c_22</twDest><twTotPathDel>1.995</twTotPathDel><twClkSkew dest = "0.244" src = "0.268">0.024</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/Si57xDivider_c_3</twSrc><twDest BELType='FF'>i_Core/Si57xDivider_c_22</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X58Y99.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X58Y99.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;3&gt;</twComp><twBEL>i_Core/Si57xDivider_c_3</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y99.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.452</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y99.COUT</twSite><twDelType>Topcyd</twDelType><twDelInfo twEdge="twRising">0.290</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;3&gt;</twComp><twBEL>i_Core/Si57xDivider_c&lt;3&gt;_rt</twBEL><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;3&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y100.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>i_Core/Mcount_Si57xDivider_c_cy&lt;3&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y100.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.091</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;7&gt;</twComp><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;7&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y101.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>i_Core/Mcount_Si57xDivider_c_cy&lt;7&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y101.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.091</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;11&gt;</twComp><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;11&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y102.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>i_Core/Mcount_Si57xDivider_c_cy&lt;11&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y102.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.091</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;15&gt;</twComp><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;15&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y103.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>i_Core/Mcount_Si57xDivider_c_cy&lt;15&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y103.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.091</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;19&gt;</twComp><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;19&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y104.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.082</twDelInfo><twComp>i_Core/Mcount_Si57xDivider_c_cy&lt;19&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X58Y104.CLK</twSite><twDelType>Tcinck</twDelType><twDelInfo twEdge="twRising">0.319</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;23&gt;</twComp><twBEL>i_Core/Mcount_Si57xDivider_c_xor&lt;23&gt;</twBEL><twBEL>i_Core/Si57xDivider_c_22</twBEL></twPathDel><twLogDel>1.449</twLogDel><twRouteDel>0.546</twRouteDel><twTotDel>1.995</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>72.6</twPctLog><twPctRoute>27.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="20" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/Si57xDivider_c_23 (SLICE_X58Y104.CIN), 20 paths
......@@ -339,14 +339,14 @@
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/Si57xDivider_c_23 (SLICE_X58Y104.D6), 1 path
</twPathRptBanner><twPathRpt anchorID="28"><twConstPath anchorID="29" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.464</twSlack><twSrc BELType="FF">i_Core/Si57xDivider_c_23</twSrc><twDest BELType="FF">i_Core/Si57xDivider_c_23</twDest><twTotPathDel>0.464</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>i_Core/Si57xDivider_c_23</twSrc><twDest BELType='FF'>i_Core/Si57xDivider_c_23</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X58Y104.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X58Y104.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;23&gt;</twComp><twBEL>i_Core/Si57xDivider_c_23</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y104.D6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.027</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;23&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X58Y104.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.237</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;23&gt;</twComp><twBEL>i_Core/Si57xDivider_c&lt;23&gt;_rt</twBEL><twBEL>i_Core/Mcount_Si57xDivider_c_xor&lt;23&gt;</twBEL><twBEL>i_Core/Si57xDivider_c_23</twBEL></twPathDel><twLogDel>0.437</twLogDel><twRouteDel>0.027</twRouteDel><twTotDel>0.464</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>94.2</twPctLog><twPctRoute>5.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/Si57xDivider_c_1 (SLICE_X58Y99.B5), 1 path
</twPathRptBanner><twPathRpt anchorID="30"><twConstPath anchorID="31" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.505</twSlack><twSrc BELType="FF">i_Core/Si57xDivider_c_1</twSrc><twDest BELType="FF">i_Core/Si57xDivider_c_1</twDest><twTotPathDel>0.505</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>i_Core/Si57xDivider_c_1</twSrc><twDest BELType='FF'>i_Core/Si57xDivider_c_1</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X58Y99.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X58Y99.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;3&gt;</twComp><twBEL>i_Core/Si57xDivider_c_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y99.B5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.071</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;1&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X58Y99.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.234</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;3&gt;</twComp><twBEL>i_Core/Si57xDivider_c&lt;1&gt;_rt</twBEL><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;3&gt;</twBEL><twBEL>i_Core/Si57xDivider_c_1</twBEL></twPathDel><twLogDel>0.434</twLogDel><twRouteDel>0.071</twRouteDel><twTotDel>0.505</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>85.9</twPctLog><twPctRoute>14.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/Si57xDivider_c_5 (SLICE_X58Y100.B5), 1 path
</twPathRptBanner><twPathRpt anchorID="32"><twConstPath anchorID="33" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.505</twSlack><twSrc BELType="FF">i_Core/Si57xDivider_c_5</twSrc><twDest BELType="FF">i_Core/Si57xDivider_c_5</twDest><twTotPathDel>0.505</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>i_Core/Si57xDivider_c_5</twSrc><twDest BELType='FF'>i_Core/Si57xDivider_c_5</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X58Y100.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X58Y100.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;7&gt;</twComp><twBEL>i_Core/Si57xDivider_c_5</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y100.B5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.071</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;5&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X58Y100.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.234</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;7&gt;</twComp><twBEL>i_Core/Si57xDivider_c&lt;5&gt;_rt</twBEL><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;7&gt;</twBEL><twBEL>i_Core/Si57xDivider_c_5</twBEL></twPathDel><twLogDel>0.434</twLogDel><twRouteDel>0.071</twRouteDel><twTotDel>0.505</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>85.9</twPctLog><twPctRoute>14.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="34"><twPinLimitBanner>Component Switching Limit Checks: TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 120 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="35" type="MINPERIOD" name="Tbcper_I" slack="5.833" period="8.333" constraintValue="8.333" deviceLimit="2.500" freqLimit="400.000" physResource="Si57x_BUFG/I0" logResource="Si57x_BUFG/I0" locationPin="BUFGMUX_X2Y4.I0" clockNet="Si57x"/><twPinLimit anchorID="36" type="MINPERIOD" name="Tcp" slack="7.858" period="8.333" constraintValue="8.333" deviceLimit="0.475" freqLimit="2105.263" physResource="i_Core/Si57xDivider_c&lt;3&gt;/CLK" logResource="i_Core/Si57xDivider_c_0/CK" locationPin="SLICE_X58Y99.CLK" clockNet="Si57x_BUFG"/><twPinLimit anchorID="37" type="MINPERIOD" name="Tcp" slack="7.858" period="8.333" constraintValue="8.333" deviceLimit="0.475" freqLimit="2105.263" physResource="i_Core/Si57xDivider_c&lt;3&gt;/CLK" logResource="i_Core/Si57xDivider_c_1/CK" locationPin="SLICE_X58Y99.CLK" clockNet="Si57x_BUFG"/></twPinLimitRpt></twConst><twConst anchorID="38" twConstType="PERIOD" ><twConstHead uID="3"><twConstName UCFConstName="TIMESPEC TS_SysAppClk_ik = PERIOD &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%;" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%;</twConstName><twItemCnt>129</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>97</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>4.684</twMinPer></twConstHead><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_20 (SLICE_X82Y89.CE), 2 paths
</twPathRptBanner><twPathRpt anchorID="39"><twConstPath anchorID="40" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>3.649</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/AckI_d3_2</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_20</twDest><twTotPathDel>4.435</twTotPathDel><twClkSkew dest = "0.855" src = "1.069">0.214</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/AckI_d3_2</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_20</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X54Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X54Y101.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/AckI_d3_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X71Y99.A4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.569</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X71Y99.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;3&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/NewAckI_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X82Y89.CE</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">1.817</twDelInfo><twComp>i_Core/i_Slv2SerWB/NewAckI_a</twComp></twPathDel><twPathDel><twSite>SLICE_X82Y89.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.314</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;23&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_20</twBEL></twPathDel><twLogDel>1.049</twLogDel><twRouteDel>3.386</twRouteDel><twTotDel>4.435</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>23.7</twPctLog><twPctRoute>76.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="41"><twConstPath anchorID="42" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>3.710</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/AckI_d3_1</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_20</twDest><twTotPathDel>4.374</twTotPathDel><twClkSkew dest = "0.855" src = "1.069">0.214</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/AckI_d3_1</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_20</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X54Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X54Y101.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/AckI_d3_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X71Y99.A5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.508</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X71Y99.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;3&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/NewAckI_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X82Y89.CE</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">1.817</twDelInfo><twComp>i_Core/i_Slv2SerWB/NewAckI_a</twComp></twPathDel><twPathDel><twSite>SLICE_X82Y89.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.314</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;23&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_20</twBEL></twPathDel><twLogDel>1.049</twLogDel><twRouteDel>3.325</twRouteDel><twTotDel>4.374</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>24.0</twPctLog><twPctRoute>76.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_23 (SLICE_X82Y89.CE), 2 paths
</twPathRptBanner><twPathRpt anchorID="43"><twConstPath anchorID="44" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>3.672</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/AckI_d3_2</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_23</twDest><twTotPathDel>4.412</twTotPathDel><twClkSkew dest = "0.855" src = "1.069">0.214</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/AckI_d3_2</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_23</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X54Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X54Y101.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/AckI_d3_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X71Y99.A4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.569</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X71Y99.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;3&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/NewAckI_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X82Y89.CE</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">1.817</twDelInfo><twComp>i_Core/i_Slv2SerWB/NewAckI_a</twComp></twPathDel><twPathDel><twSite>SLICE_X82Y89.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.291</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;23&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_23</twBEL></twPathDel><twLogDel>1.026</twLogDel><twRouteDel>3.386</twRouteDel><twTotDel>4.412</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>23.3</twPctLog><twPctRoute>76.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="45"><twConstPath anchorID="46" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>3.733</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/AckI_d3_1</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_23</twDest><twTotPathDel>4.351</twTotPathDel><twClkSkew dest = "0.855" src = "1.069">0.214</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/AckI_d3_1</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_23</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X54Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X54Y101.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/AckI_d3_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X71Y99.A5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.508</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X71Y99.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;3&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/NewAckI_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X82Y89.CE</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">1.817</twDelInfo><twComp>i_Core/i_Slv2SerWB/NewAckI_a</twComp></twPathDel><twPathDel><twSite>SLICE_X82Y89.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.291</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;23&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_23</twBEL></twPathDel><twLogDel>1.026</twLogDel><twRouteDel>3.325</twRouteDel><twTotDel>4.351</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>23.6</twPctLog><twPctRoute>76.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_22 (SLICE_X82Y89.CE), 2 paths
</twPathRptBanner><twPathRpt anchorID="47"><twConstPath anchorID="48" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>3.674</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/AckI_d3_2</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_22</twDest><twTotPathDel>4.410</twTotPathDel><twClkSkew dest = "0.855" src = "1.069">0.214</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/AckI_d3_2</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_22</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X54Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X54Y101.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/AckI_d3_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X71Y99.A4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.569</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X71Y99.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;3&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/NewAckI_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X82Y89.CE</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">1.817</twDelInfo><twComp>i_Core/i_Slv2SerWB/NewAckI_a</twComp></twPathDel><twPathDel><twSite>SLICE_X82Y89.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.289</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;23&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_22</twBEL></twPathDel><twLogDel>1.024</twLogDel><twRouteDel>3.386</twRouteDel><twTotDel>4.410</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>23.2</twPctLog><twPctRoute>76.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="49"><twConstPath anchorID="50" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>3.735</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/AckI_d3_1</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_22</twDest><twTotPathDel>4.349</twTotPathDel><twClkSkew dest = "0.855" src = "1.069">0.214</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/AckI_d3_1</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_22</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X54Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X54Y101.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/AckI_d3_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X71Y99.A5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.508</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X71Y99.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;3&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/NewAckI_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X82Y89.CE</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">1.817</twDelInfo><twComp>i_Core/i_Slv2SerWB/NewAckI_a</twComp></twPathDel><twPathDel><twSite>SLICE_X82Y89.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.289</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;23&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_22</twBEL></twPathDel><twLogDel>1.024</twLogDel><twRouteDel>3.325</twRouteDel><twTotDel>4.349</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>23.5</twPctLog><twPctRoute>76.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_14 (SLICE_X78Y92.CX), 1 path
</twPathRptBanner><twPathRpt anchorID="51"><twConstPath anchorID="52" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.439</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/DatInShReg_b32_14</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_14</twDest><twTotPathDel>0.440</twTotPathDel><twClkSkew dest = "0.041" src = "0.040">-0.001</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/DatInShReg_b32_14</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_14</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X79Y93.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X79Y93.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>i_Core/i_Slv2SerWB/DatInShReg_b32&lt;15&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/DatInShReg_b32_14</twBEL></twPathDel><twPathDel><twSite>SLICE_X78Y92.CX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.194</twDelInfo><twComp>i_Core/i_Slv2SerWB/DatInShReg_b32&lt;14&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X78Y92.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.048</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;15&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_14</twBEL></twPathDel><twLogDel>0.246</twLogDel><twRouteDel>0.194</twRouteDel><twTotDel>0.440</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>55.9</twPctLog><twPctRoute>44.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_10 (SLICE_X78Y97.CX), 1 path
</twPathRptBanner><twPathRpt anchorID="53"><twConstPath anchorID="54" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.441</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/DatInShReg_b32_10</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_10</twDest><twTotPathDel>0.442</twTotPathDel><twClkSkew dest = "0.043" src = "0.042">-0.001</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/DatInShReg_b32_10</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_10</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X78Y96.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X78Y96.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>i_Core/i_Slv2SerWB/DatInShReg_b32&lt;11&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/DatInShReg_b32_10</twBEL></twPathDel><twPathDel><twSite>SLICE_X78Y97.CX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.194</twDelInfo><twComp>i_Core/i_Slv2SerWB/DatInShReg_b32&lt;10&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X78Y97.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.048</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;11&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_10</twBEL></twPathDel><twLogDel>0.248</twLogDel><twRouteDel>0.194</twRouteDel><twTotDel>0.442</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>56.1</twPctLog><twPctRoute>43.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_11 (SLICE_X78Y97.DX), 1 path
</twPathRptBanner><twPathRpt anchorID="55"><twConstPath anchorID="56" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.441</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/DatInShReg_b32_11</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_11</twDest><twTotPathDel>0.442</twTotPathDel><twClkSkew dest = "0.043" src = "0.042">-0.001</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/DatInShReg_b32_11</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_11</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X78Y96.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X78Y96.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>i_Core/i_Slv2SerWB/DatInShReg_b32&lt;11&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/DatInShReg_b32_11</twBEL></twPathDel><twPathDel><twSite>SLICE_X78Y97.DX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.194</twDelInfo><twComp>i_Core/i_Slv2SerWB/DatInShReg_b32&lt;11&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X78Y97.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.048</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;11&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_11</twBEL></twPathDel><twLogDel>0.248</twLogDel><twRouteDel>0.194</twRouteDel><twTotDel>0.442</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>56.1</twPctLog><twPctRoute>43.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="57"><twPinLimitBanner>Component Switching Limit Checks: TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="58" type="MINPERIOD" name="Tbcper_I" slack="5.833" period="8.333" constraintValue="8.333" deviceLimit="2.500" freqLimit="400.000" physResource="SysAppClk_ik_BUFGP/BUFG/I0" logResource="SysAppClk_ik_BUFGP/BUFG/I0" locationPin="BUFGMUX_X3Y14.I0" clockNet="SysAppClk_ik_BUFGP/IBUFG"/><twPinLimit anchorID="59" type="MINPERIOD" name="Tcp" slack="7.853" period="8.333" constraintValue="8.333" deviceLimit="0.480" freqLimit="2083.333" physResource="i_Core/i_Slv2SerWB/DatInShReg_b32&lt;31&gt;/CLK" logResource="i_Core/i_Slv2SerWB/DatInShReg_b32_28/CK" locationPin="SLICE_X56Y84.CLK" clockNet="SysAppClk_ik_BUFGP"/><twPinLimit anchorID="60" type="MINPERIOD" name="Tcp" slack="7.853" period="8.333" constraintValue="8.333" deviceLimit="0.480" freqLimit="2083.333" physResource="i_Core/i_Slv2SerWB/DatInShReg_b32&lt;31&gt;/CLK" logResource="i_Core/i_Slv2SerWB/DatInShReg_b32_29/CK" locationPin="SLICE_X56Y84.CLK" clockNet="SysAppClk_ik_BUFGP"/></twPinLimitRpt></twConst><twUnmetConstCnt anchorID="61">0</twUnmetConstCnt><twDataSheet anchorID="62" twNameLen="15"><twClk2SUList anchorID="63" twDestWidth="9"><twDest>Si57x_ik</twDest><twClk2SU><twSrc>Si57x_ik</twSrc><twRiseRise>2.181</twRiseRise></twClk2SU><twClk2SU><twSrc>Si57x_ikn</twSrc><twRiseRise>2.181</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="64" twDestWidth="9"><twDest>Si57x_ikn</twDest><twClk2SU><twSrc>Si57x_ik</twSrc><twRiseRise>2.181</twRiseRise></twClk2SU><twClk2SU><twSrc>Si57x_ikn</twSrc><twRiseRise>2.181</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="65" twDestWidth="12"><twDest>SysAppClk_ik</twDest><twClk2SU><twSrc>SysAppClk_ik</twSrc><twRiseRise>4.684</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="66"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>429</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>127</twConnCnt></twConstCov><twStats anchorID="67"><twMinPer>4.684</twMinPer><twFootnote number="1" /><twMaxFreq>213.493</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Fri Jan 28 11:55:25 2011 </twTimestamp></twFoot><twClientInfo anchorID="68"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
</twPathRptBanner><twPathRpt anchorID="32"><twConstPath anchorID="33" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.505</twSlack><twSrc BELType="FF">i_Core/Si57xDivider_c_5</twSrc><twDest BELType="FF">i_Core/Si57xDivider_c_5</twDest><twTotPathDel>0.505</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>i_Core/Si57xDivider_c_5</twSrc><twDest BELType='FF'>i_Core/Si57xDivider_c_5</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X58Y100.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Si57x_BUFG</twSrcClk><twPathDel><twSite>SLICE_X58Y100.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;7&gt;</twComp><twBEL>i_Core/Si57xDivider_c_5</twBEL></twPathDel><twPathDel><twSite>SLICE_X58Y100.B5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.071</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;5&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X58Y100.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.234</twDelInfo><twComp>i_Core/Si57xDivider_c&lt;7&gt;</twComp><twBEL>i_Core/Si57xDivider_c&lt;5&gt;_rt</twBEL><twBEL>i_Core/Mcount_Si57xDivider_c_cy&lt;7&gt;</twBEL><twBEL>i_Core/Si57xDivider_c_5</twBEL></twPathDel><twLogDel>0.434</twLogDel><twRouteDel>0.071</twRouteDel><twTotDel>0.505</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">Si57x_BUFG</twDestClk><twPctLog>85.9</twPctLog><twPctRoute>14.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="34"><twPinLimitBanner>Component Switching Limit Checks: TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 120 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="35" type="MINPERIOD" name="Tbcper_I" slack="5.833" period="8.333" constraintValue="8.333" deviceLimit="2.500" freqLimit="400.000" physResource="Si57x_BUFG/I0" logResource="Si57x_BUFG/I0" locationPin="BUFGMUX_X2Y4.I0" clockNet="Si57x"/><twPinLimit anchorID="36" type="MINPERIOD" name="Tcp" slack="7.858" period="8.333" constraintValue="8.333" deviceLimit="0.475" freqLimit="2105.263" physResource="i_Core/Si57xDivider_c&lt;3&gt;/CLK" logResource="i_Core/Si57xDivider_c_0/CK" locationPin="SLICE_X58Y99.CLK" clockNet="Si57x_BUFG"/><twPinLimit anchorID="37" type="MINPERIOD" name="Tcp" slack="7.858" period="8.333" constraintValue="8.333" deviceLimit="0.475" freqLimit="2105.263" physResource="i_Core/Si57xDivider_c&lt;3&gt;/CLK" logResource="i_Core/Si57xDivider_c_1/CK" locationPin="SLICE_X58Y99.CLK" clockNet="Si57x_BUFG"/></twPinLimitRpt></twConst><twConst anchorID="38" twConstType="PERIOD" ><twConstHead uID="3"><twConstName UCFConstName="TIMESPEC TS_SysAppClk_ik = PERIOD &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%;" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%;</twConstName><twItemCnt>129</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>97</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>4.929</twMinPer></twConstHead><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_28 (SLICE_X64Y84.CE), 2 paths
</twPathRptBanner><twPathRpt anchorID="39"><twConstPath anchorID="40" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>3.404</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/AckI_d3_2</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_28</twDest><twTotPathDel>4.865</twTotPathDel><twClkSkew dest = "1.040" src = "1.069">0.029</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/AckI_d3_2</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_28</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X54Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X54Y101.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/AckI_d3_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X71Y99.A4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.569</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X71Y99.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;3&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/NewAckI_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y84.CE</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">2.248</twDelInfo><twComp>i_Core/i_Slv2SerWB/NewAckI_a</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y84.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.313</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;31&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_28</twBEL></twPathDel><twLogDel>1.048</twLogDel><twRouteDel>3.817</twRouteDel><twTotDel>4.865</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>21.5</twPctLog><twPctRoute>78.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="41"><twConstPath anchorID="42" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>3.465</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/AckI_d3_1</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_28</twDest><twTotPathDel>4.804</twTotPathDel><twClkSkew dest = "1.040" src = "1.069">0.029</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/AckI_d3_1</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_28</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X54Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X54Y101.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/AckI_d3_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X71Y99.A5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.508</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X71Y99.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;3&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/NewAckI_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y84.CE</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">2.248</twDelInfo><twComp>i_Core/i_Slv2SerWB/NewAckI_a</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y84.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.313</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;31&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_28</twBEL></twPathDel><twLogDel>1.048</twLogDel><twRouteDel>3.756</twRouteDel><twTotDel>4.804</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>21.8</twPctLog><twPctRoute>78.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_30 (SLICE_X64Y84.CE), 2 paths
</twPathRptBanner><twPathRpt anchorID="43"><twConstPath anchorID="44" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>3.448</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/AckI_d3_2</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_30</twDest><twTotPathDel>4.821</twTotPathDel><twClkSkew dest = "1.040" src = "1.069">0.029</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/AckI_d3_2</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_30</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X54Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X54Y101.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/AckI_d3_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X71Y99.A4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.569</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X71Y99.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;3&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/NewAckI_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y84.CE</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">2.248</twDelInfo><twComp>i_Core/i_Slv2SerWB/NewAckI_a</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y84.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.269</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;31&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_30</twBEL></twPathDel><twLogDel>1.004</twLogDel><twRouteDel>3.817</twRouteDel><twTotDel>4.821</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>20.8</twPctLog><twPctRoute>79.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="45"><twConstPath anchorID="46" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>3.509</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/AckI_d3_1</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_30</twDest><twTotPathDel>4.760</twTotPathDel><twClkSkew dest = "1.040" src = "1.069">0.029</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/AckI_d3_1</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_30</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X54Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X54Y101.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/AckI_d3_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X71Y99.A5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.508</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X71Y99.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;3&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/NewAckI_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y84.CE</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">2.248</twDelInfo><twComp>i_Core/i_Slv2SerWB/NewAckI_a</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y84.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.269</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;31&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_30</twBEL></twPathDel><twLogDel>1.004</twLogDel><twRouteDel>3.756</twRouteDel><twTotDel>4.760</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>21.1</twPctLog><twPctRoute>78.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="2" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_31 (SLICE_X64Y84.CE), 2 paths
</twPathRptBanner><twPathRpt anchorID="47"><twConstPath anchorID="48" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>3.451</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/AckI_d3_2</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_31</twDest><twTotPathDel>4.818</twTotPathDel><twClkSkew dest = "1.040" src = "1.069">0.029</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/AckI_d3_2</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_31</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X54Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X54Y101.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/AckI_d3_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X71Y99.A4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.569</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X71Y99.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;3&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/NewAckI_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y84.CE</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">2.248</twDelInfo><twComp>i_Core/i_Slv2SerWB/NewAckI_a</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y84.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.266</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;31&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_31</twBEL></twPathDel><twLogDel>1.001</twLogDel><twRouteDel>3.817</twRouteDel><twTotDel>4.818</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>20.8</twPctLog><twPctRoute>79.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="49"><twConstPath anchorID="50" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>3.512</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/AckI_d3_1</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_31</twDest><twTotPathDel>4.757</twTotPathDel><twClkSkew dest = "1.040" src = "1.069">0.029</twClkSkew><twDelConst>8.333</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/AckI_d3_1</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_31</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X54Y101.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X54Y101.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;2&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/AckI_d3_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X71Y99.A5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.508</twDelInfo><twComp>i_Core/i_Slv2SerWB/AckI_d3&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X71Y99.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;3&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/NewAckI_a&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X64Y84.CE</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">2.248</twDelInfo><twComp>i_Core/i_Slv2SerWB/NewAckI_a</twComp></twPathDel><twPathDel><twSite>SLICE_X64Y84.CLK</twSite><twDelType>Tceck</twDelType><twDelInfo twEdge="twRising">0.266</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;31&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_31</twBEL></twPathDel><twLogDel>1.001</twLogDel><twRouteDel>3.756</twRouteDel><twTotDel>4.757</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>21.0</twPctLog><twPctRoute>79.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_10 (SLICE_X78Y97.CX), 1 path
</twPathRptBanner><twPathRpt anchorID="51"><twConstPath anchorID="52" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.439</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/DatInShReg_b32_10</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_10</twDest><twTotPathDel>0.440</twTotPathDel><twClkSkew dest = "0.043" src = "0.042">-0.001</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/DatInShReg_b32_10</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_10</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X79Y96.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X79Y96.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>i_Core/i_Slv2SerWB/DatInShReg_b32&lt;11&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/DatInShReg_b32_10</twBEL></twPathDel><twPathDel><twSite>SLICE_X78Y97.CX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.194</twDelInfo><twComp>i_Core/i_Slv2SerWB/DatInShReg_b32&lt;10&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X78Y97.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.048</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;11&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_10</twBEL></twPathDel><twLogDel>0.246</twLogDel><twRouteDel>0.194</twRouteDel><twTotDel>0.440</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>55.9</twPctLog><twPctRoute>44.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_11 (SLICE_X78Y97.DX), 1 path
</twPathRptBanner><twPathRpt anchorID="53"><twConstPath anchorID="54" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.439</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/DatInShReg_b32_11</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_11</twDest><twTotPathDel>0.440</twTotPathDel><twClkSkew dest = "0.043" src = "0.042">-0.001</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/DatInShReg_b32_11</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_11</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X79Y96.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X79Y96.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>i_Core/i_Slv2SerWB/DatInShReg_b32&lt;11&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/DatInShReg_b32_11</twBEL></twPathDel><twPathDel><twSite>SLICE_X78Y97.DX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.194</twDelInfo><twComp>i_Core/i_Slv2SerWB/DatInShReg_b32&lt;11&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X78Y97.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.048</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;11&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_11</twBEL></twPathDel><twLogDel>0.246</twLogDel><twRouteDel>0.194</twRouteDel><twTotDel>0.440</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>55.9</twPctLog><twPctRoute>44.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_9 (SLICE_X78Y97.BX), 1 path
</twPathRptBanner><twPathRpt anchorID="55"><twConstPath anchorID="56" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.448</twSlack><twSrc BELType="FF">i_Core/i_Slv2SerWB/DatInShReg_b32_9</twSrc><twDest BELType="FF">i_Core/i_Slv2SerWB/Dat_xb32_9</twDest><twTotPathDel>0.449</twTotPathDel><twClkSkew dest = "0.043" src = "0.042">-0.001</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>i_Core/i_Slv2SerWB/DatInShReg_b32_9</twSrc><twDest BELType='FF'>i_Core/i_Slv2SerWB/Dat_xb32_9</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X79Y96.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">SysAppClk_ik_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X79Y96.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>i_Core/i_Slv2SerWB/DatInShReg_b32&lt;11&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/DatInShReg_b32_9</twBEL></twPathDel><twPathDel><twSite>SLICE_X78Y97.BX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.203</twDelInfo><twComp>i_Core/i_Slv2SerWB/DatInShReg_b32&lt;9&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X78Y97.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.048</twDelInfo><twComp>i_Core/i_Slv2SerWB/Dat_xb32&lt;11&gt;</twComp><twBEL>i_Core/i_Slv2SerWB/Dat_xb32_9</twBEL></twPathDel><twLogDel>0.246</twLogDel><twRouteDel>0.203</twRouteDel><twTotDel>0.449</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="8.333">SysAppClk_ik_BUFGP</twDestClk><twPctLog>54.8</twPctLog><twPctRoute>45.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="57"><twPinLimitBanner>Component Switching Limit Checks: TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="58" type="MINPERIOD" name="Tbcper_I" slack="5.833" period="8.333" constraintValue="8.333" deviceLimit="2.500" freqLimit="400.000" physResource="SysAppClk_ik_BUFGP/BUFG/I0" logResource="SysAppClk_ik_BUFGP/BUFG/I0" locationPin="BUFGMUX_X3Y14.I0" clockNet="SysAppClk_ik_BUFGP/IBUFG"/><twPinLimit anchorID="59" type="MINPERIOD" name="Tcp" slack="7.853" period="8.333" constraintValue="8.333" deviceLimit="0.480" freqLimit="2083.333" physResource="i_Core/i_Slv2SerWB/Dat_xb32&lt;31&gt;/CLK" logResource="i_Core/i_Slv2SerWB/Dat_xb32_28/CK" locationPin="SLICE_X64Y84.CLK" clockNet="SysAppClk_ik_BUFGP"/><twPinLimit anchorID="60" type="MINPERIOD" name="Tcp" slack="7.853" period="8.333" constraintValue="8.333" deviceLimit="0.480" freqLimit="2083.333" physResource="i_Core/i_Slv2SerWB/Dat_xb32&lt;31&gt;/CLK" logResource="i_Core/i_Slv2SerWB/Dat_xb32_29/CK" locationPin="SLICE_X64Y84.CLK" clockNet="SysAppClk_ik_BUFGP"/></twPinLimitRpt></twConst><twUnmetConstCnt anchorID="61">0</twUnmetConstCnt><twDataSheet anchorID="62" twNameLen="15"><twClk2SUList anchorID="63" twDestWidth="9"><twDest>Si57x_ik</twDest><twClk2SU><twSrc>Si57x_ik</twSrc><twRiseRise>2.181</twRiseRise></twClk2SU><twClk2SU><twSrc>Si57x_ikn</twSrc><twRiseRise>2.181</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="64" twDestWidth="9"><twDest>Si57x_ikn</twDest><twClk2SU><twSrc>Si57x_ik</twSrc><twRiseRise>2.181</twRiseRise></twClk2SU><twClk2SU><twSrc>Si57x_ikn</twSrc><twRiseRise>2.181</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="65" twDestWidth="12"><twDest>SysAppClk_ik</twDest><twClk2SU><twSrc>SysAppClk_ik</twSrc><twRiseRise>4.929</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="66"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>429</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>127</twConnCnt></twConstCov><twStats anchorID="67"><twMinPer>4.929</twMinPer><twFootnote number="1" /><twMaxFreq>202.881</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Fri Jan 28 15:08:44 2011 </twTimestamp></twFoot><twClientInfo anchorID="68"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 268 MB
Peak Memory Usage: 390 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
trunk/firmware/XilinxISE/SystemFpga/SFpga.unroutes
View file @ 777894d8
Release 12.3 - par M.70d (nt)
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Jan 28 11:55:02 2011
Fri Jan 28 15:08:33 2011
All signals are completely routed.
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_envsettings.html
View file @ 777894d8
......@@ -15,17 +15,17 @@
</tr>
<tr>
<td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
</tr>
<tr>
<td>Path</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
</tr>
<tr>
<td>XILINX</td>
......@@ -35,13 +35,6 @@
<td>C:\Xilinx\12.3\ISE_DS\ISE\</td>
</tr>
<tr>
<td>XILINXD_LICENSE_FILE</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td>
......@@ -515,31 +508,31 @@
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
</tr>
<tr>
<td>Host</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>PCBE13225</td>
<td>PCBE13225</td>
<td>PCBE13225</td>
<td>PCBE13225</td>
</tr>
<tr>
<td>OS Name</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft </td>
<td>Microsoft </td>
<td>Microsoft </td>
<td>Microsoft </td>
</tr>
<tr>
<td>OS Release</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>major release (build 7600)</td>
<td>major release (build 7600)</td>
<td>major release (build 7600)</td>
<td>major release (build 7600)</td>
</tr>
</TABLE>
</BODY> </HTML>
\ No newline at end of file
trunk/firmware/XilinxISE/SystemFpga/SFpga_guide.ncd
View file @ 777894d8
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.map
View file @ 777894d8
Release 12.3 Map M.70d (nt)
Release 12.3 Map M.70d (nt64)
Xilinx Map Application Log File for Design 'SFpga'
Design Information
......@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Jan 28 11:48:01 2011
Mapped Date : Fri Jan 28 15:05:14 2011
Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
......@@ -87,58 +87,58 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 25 secs
Total CPU time at the beginning of Placer: 24 secs
Total REAL time at the beginning of Placer: 12 secs
Total CPU time at the beginning of Placer: 11 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:cc31257e) REAL time: 32 secs
Phase 1.1 Initial Placement Analysis (Checksum:cc31257e) REAL time: 16 secs
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 331 IOs, 329 are locked
and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:cc31257e) REAL time: 33 secs
Phase 2.7 Design Feasibility Check (Checksum:cc31257e) REAL time: 17 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:cc31257e) REAL time: 33 secs
Phase 3.31 Local Placement Optimization (Checksum:cc31257e) REAL time: 17 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:aaca966e) REAL time: 40 secs
(Checksum:aaca966e) REAL time: 21 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:aaca966e) REAL time: 40 secs
Phase 5.36 Local Placement Optimization (Checksum:aaca966e) REAL time: 21 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:aaca966e) REAL time: 40 secs
Phase 6.30 Global Clock Region Assignment (Checksum:aaca966e) REAL time: 21 secs
Phase 7.3 Local Placement Optimization
...
Phase 7.3 Local Placement Optimization (Checksum:98519d88) REAL time: 41 secs
Phase 7.3 Local Placement Optimization (Checksum:98519d88) REAL time: 22 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:aaea37e3) REAL time: 41 secs
Phase 8.5 Local Placement Optimization (Checksum:aaea37e3) REAL time: 22 secs
Phase 9.8 Global Placement
....
....................
Phase 9.8 Global Placement (Checksum:f9eafb45) REAL time: 44 secs
.........
..........................................
Phase 9.8 Global Placement (Checksum:de2814d1) REAL time: 24 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:f9eafb45) REAL time: 44 secs
Phase 10.5 Local Placement Optimization (Checksum:de2814d1) REAL time: 24 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:af7d4423) REAL time: 45 secs
Phase 11.18 Placement Optimization (Checksum:b777ab7) REAL time: 25 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:af7d4423) REAL time: 45 secs
Phase 12.5 Local Placement Optimization (Checksum:b777ab7) REAL time: 25 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:1a6c36bd) REAL time: 46 secs
Phase 13.34 Placement Validation (Checksum:f00dac81) REAL time: 25 secs
Total REAL time to Placer completion: 55 secs
Total CPU time to Placer completion: 55 secs
Total REAL time to Placer completion: 30 secs
Total CPU time to Placer completion: 29 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
......@@ -253,7 +253,7 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 851 out of 92,152 1%
Number of Slice LUTs: 849 out of 92,152 1%
Number used as logic: 823 out of 92,152 1%
Number using O6 output only: 616
Number using O5 output only: 83
......@@ -269,17 +269,17 @@ Slice Logic Utilization:
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 2
Number used exclusively as route-thrus: 14
Number with same-slice register load: 9
Number used exclusively as route-thrus: 12
Number with same-slice register load: 7
Number with same-slice carry load: 5
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 392 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,060
Number with an unused Flip Flop: 372 out of 1,060 35%
Number with an unused LUT: 209 out of 1,060 19%
Number of fully used LUT-FF pairs: 479 out of 1,060 45%
Number of occupied Slices: 386 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,046
Number with an unused Flip Flop: 356 out of 1,046 34%
Number with an unused LUT: 197 out of 1,046 18%
Number of fully used LUT-FF pairs: 493 out of 1,046 47%
Number of unique control sets: 27
Number of slice register sites lost
to control set restrictions: 71 out of 184,304 1%
......@@ -325,9 +325,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.41
Peak Memory Usage: 396 MB
Total REAL time to MAP completion: 58 secs
Total CPU time to MAP completion: 58 secs
Peak Memory Usage: 618 MB
Total REAL time to MAP completion: 32 secs
Total CPU time to MAP completion: 31 secs
Mapping completed.
See MAP report file "SFpga_map.mrp" for details.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.mrp
View file @ 777894d8
Release 12.3 Map M.70d (nt)
Release 12.3 Map M.70d (nt64)
Xilinx Mapping Report File for Design 'SFpga'
Design Information
......@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Jan 28 11:48:01 2011
Mapped Date : Fri Jan 28 15:05:14 2011
Design Summary
--------------
......@@ -22,7 +22,7 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 851 out of 92,152 1%
Number of Slice LUTs: 849 out of 92,152 1%
Number used as logic: 823 out of 92,152 1%
Number using O6 output only: 616
Number using O5 output only: 83
......@@ -38,17 +38,17 @@ Slice Logic Utilization:
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 2
Number used exclusively as route-thrus: 14
Number with same-slice register load: 9
Number used exclusively as route-thrus: 12
Number with same-slice register load: 7
Number with same-slice carry load: 5
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 392 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,060
Number with an unused Flip Flop: 372 out of 1,060 35%
Number with an unused LUT: 209 out of 1,060 19%
Number of fully used LUT-FF pairs: 479 out of 1,060 45%
Number of occupied Slices: 386 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,046
Number with an unused Flip Flop: 356 out of 1,046 34%
Number with an unused LUT: 197 out of 1,046 18%
Number of fully used LUT-FF pairs: 493 out of 1,046 47%
Number of unique control sets: 27
Number of slice register sites lost
to control set restrictions: 71 out of 184,304 1%
......@@ -94,9 +94,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.41
Peak Memory Usage: 396 MB
Total REAL time to MAP completion: 58 secs
Total CPU time to MAP completion: 58 secs
Peak Memory Usage: 618 MB
Total REAL time to MAP completion: 32 secs
Total CPU time to MAP completion: 31 secs
Table of Contents
-----------------
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.ncd
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This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.ngm
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This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.xrpt
View file @ 777894d8
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3">
<document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Fri Jan 28 11:49:00 2011">
<application stringID="Map" timeStamp="Fri Jan 28 15:05:47 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="6">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item>
<item stringID="User_EnvHost" value="bqplv2"/>
<item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
</row>
</table>
</section>
......@@ -120,9 +116,9 @@
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="83"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="405884"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="58 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="58 secs "/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="632572"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="32 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="31 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="765">
......@@ -131,7 +127,7 @@
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="851">
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="849">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="83"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="616"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="124"/>
......@@ -148,21 +144,21 @@
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="4"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="2"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="5"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="9"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="7"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="9"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="7"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="5"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="392">
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="386">
<item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="51"/>
<item AVAILABLE="5420" dataType="int" stringID="MAP_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="337"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="331"/>
</item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1060">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="372"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="209"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="479"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1046">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="356"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="197"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="493"/>
</item>
</section>
<section stringID="MAP_IOB_REPORTING">
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_ngdbuild.xrpt
View file @ 777894d8
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3">
<document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Fri Jan 28 11:47:59 2011">
<application stringID="NgdBuild" timeStamp="Fri Jan 28 15:05:13 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="6">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item>
<item stringID="User_EnvHost" value="bqplv2"/>
<item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
</row>
</table>
</section>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.csv
View file @ 777894d8
#Release 12.3 - par M.70d (nt)
#Release 12.3 - par M.70d (nt64)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Fri Jan 28 11:55:00 2011
#Fri Jan 28 15:08:32 2011
#
## NOTE: This file is designed to be imported into a spreadsheet program
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.txt
View file @ 777894d8
Release 12.3 - par M.70d (nt)
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Jan 28 11:55:01 2011
Fri Jan 28 15:08:32 2011
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_par.xrpt
View file @ 777894d8
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3">
<document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Fri Jan 28 11:49:22 2011">
<application stringID="par" timeStamp="Fri Jan 28 15:05:58 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="6">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item>
<item stringID="User_EnvHost" value="bqplv2"/>
<item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
</row>
</table>
</section>
......@@ -63,12 +59,12 @@
</task>
<task stringID="PAR_PAR">
<section stringID="PAR_DESIGN_SUMMARY">
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="5 mins 56 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="5 mins 54 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="2 mins 41 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="2 mins 40 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="5 mins 59 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="5 mins 58 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="2 mins 43 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="2 mins 42 secs "/>
</section>
</task>
<task stringID="PAR_par">
......@@ -87,7 +83,7 @@
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y16"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="203.000000"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="204.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.325000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.693000"/>
</row>
......@@ -106,8 +102,8 @@
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y14"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="16.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.189000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.692000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.190000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.693000"/>
</row>
<row stringID="row" value="4">
<item label="Clock Net" stringID="CLOCK_NET" value="i_Core/i_VmeInterface/Stb_oq"/>
......@@ -115,7 +111,7 @@
<item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="17.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="2.404000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="2.145000"/>
</row>
</table>
</section>
......@@ -6274,51 +6270,47 @@
</task>
</application>
<application stringID="Par" timeStamp="Fri Jan 28 11:49:22 2011">
<application stringID="Par" timeStamp="Fri Jan 28 15:05:58 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="6">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item>
<item stringID="User_EnvHost" value="bqplv2"/>
<item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
</row>
</table>
</section>
......@@ -6330,7 +6322,7 @@
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="851">
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="849">
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="83"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="616"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="124"/>
......@@ -6347,21 +6339,21 @@
<item dataType="int" stringID="PAR_NUM_SRL_O6ONLY" value="4"/>
<item dataType="int" stringID="PAR_NUM_SRL_O5ANDO6" value="2"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO6" value="5"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="9"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="7"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="9"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="7"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="5"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="23038" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="392">
<item AVAILABLE="23038" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="386">
<item AVAILABLE="6099" dataType="int" stringID="PAR_NUM_SLICEL" value="51"/>
<item AVAILABLE="5420" dataType="int" stringID="PAR_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="PAR_NUM_SLICEX" value="337"/>
<item AVAILABLE="11519" dataType="int" stringID="PAR_NUM_SLICEX" value="331"/>
</item>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="1060">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="372"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="209"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="479"/>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="1046">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="356"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="197"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="493"/>
</item>
</section>
<section stringID="PAR_IOB_REPORTING">
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.html
View file @ 777894d8
......@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>SFpga Project Status (01/28/2011 - 11:56:25)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>SFpga Project Status (01/28/2011 - 15:09:29)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>SystemFpga.xise</TD>
......@@ -90,7 +90,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>851</TD>
<TD ALIGN=RIGHT>849</TD>
<TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -186,13 +186,13 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
<TD ALIGN=RIGHT>14</TD>
<TD ALIGN=RIGHT>12</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
<TD ALIGN=RIGHT>9</TD>
<TD ALIGN=RIGHT>7</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -210,33 +210,33 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>392</TD>
<TD ALIGN=RIGHT>386</TD>
<TD ALIGN=RIGHT>23,038</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>1,060</TD>
<TD ALIGN=RIGHT>1,046</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>372</TD>
<TD ALIGN=RIGHT>1,060</TD>
<TD ALIGN=RIGHT>35%</TD>
<TD ALIGN=RIGHT>356</TD>
<TD ALIGN=RIGHT>1,046</TD>
<TD ALIGN=RIGHT>34%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>209</TD>
<TD ALIGN=RIGHT>1,060</TD>
<TD ALIGN=RIGHT>19%</TD>
<TD ALIGN=RIGHT>197</TD>
<TD ALIGN=RIGHT>1,046</TD>
<TD ALIGN=RIGHT>18%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>479</TD>
<TD ALIGN=RIGHT>1,060</TD>
<TD ALIGN=RIGHT>45%</TD>
<TD ALIGN=RIGHT>493</TD>
<TD ALIGN=RIGHT>1,046</TD>
<TD ALIGN=RIGHT>47%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
......@@ -463,23 +463,23 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Jan 28 11:47:53 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>129 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Info'>17 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Jan 28 11:47:59 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>16 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri Jan 28 11:49:00 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Warning'>83 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri Jan 28 11:55:02 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/par.xmsgs?&DataKey=Warning'>51 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri 28. Jan 15:05:08 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>129 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Info'>17 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri 28. Jan 15:05:13 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>16 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri 28. Jan 15:05:47 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Warning'>83 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri 28. Jan 15:08:33 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/par.xmsgs?&DataKey=Warning'>51 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Fri Jan 28 11:55:25 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/trce.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Fri Jan 28 11:56:19 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>50 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Fri 28. Jan 15:08:44 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/trce.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Fri 28. Jan 15:09:13 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>50 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Mon Dec 20 10:20:47 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.ibs'>IBIS Model</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Mon Dec 20 10:20:47 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri Jan 28 11:56:20 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri Jan 28 11:56:25 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri 28. Jan 14:59:17 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.ibs'>IBIS Model</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri 28. Jan 14:59:17 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri 28. Jan 15:09:13 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri 28. Jan 15:09:29 2011</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 01/28/2011 - 11:56:26</center>
<br><center><b>Date Generated:</b> 01/28/2011 - 15:09:29</center>
</BODY></HTML>
\ No newline at end of file
trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.xml
View file @ 777894d8
......@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="59">
<DesignSummary rev="61">
<CmdHistory>
</CmdHistory>
</DesignSummary>
trunk/firmware/XilinxISE/SystemFpga/SFpga_usage.xml
View file @ 777894d8
......@@ -4,810 +4,810 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="59">
<DesignStatistics TimeStamp="Fri Jan 28 11:56:18 2011"><group name="NetStatistics">
<item name="NumNets_Active" rev="59">
<DeviceUsageSummary rev="61">
<DesignStatistics TimeStamp="Fri Jan 28 15:09:13 2011"><group name="NetStatistics">
<item name="NumNets_Active" rev="61">
<attrib name="value" value="1735"/></item>
<item name="NumNets_Gnd" rev="59">
<item name="NumNets_Gnd" rev="61">
<attrib name="value" value="1"/></item>
<item name="NumNets_Vcc" rev="59">
<item name="NumNets_Vcc" rev="61">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="59">
<attrib name="value" value="10"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="59">
<attrib name="value" value="200"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="59">
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="61">
<attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="61">
<attrib name="value" value="211"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="61">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="59">
<attrib name="value" value="20"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="59">
<attrib name="value" value="226"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="59">
<attrib name="value" value="20"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="59">
<attrib name="value" value="253"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="59">
<attrib name="value" value="2317"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="59">
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="61">
<attrib name="value" value="21"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="61">
<attrib name="value" value="227"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="61">
<attrib name="value" value="21"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="61">
<attrib name="value" value="256"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="61">
<attrib name="value" value="2187"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="61">
<attrib name="value" value="354"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="59">
<attrib name="value" value="185"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="59">
<item name="NumNodesOfType_Active_GLOBAL" rev="61">
<attrib name="value" value="180"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="61">
<attrib name="value" value="33"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="59">
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="61">
<attrib name="value" value="242"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="59">
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="61">
<attrib name="value" value="242"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="59">
<attrib name="value" value="3401"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="59">
<attrib name="value" value="1440"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="59">
<attrib name="value" value="1281"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="59">
<item name="NumNodesOfType_Active_LUTINPUT" rev="61">
<attrib name="value" value="3398"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="61">
<attrib name="value" value="1442"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="61">
<attrib name="value" value="1292"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="61">
<attrib name="value" value="135"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="59">
<item name="NumNodesOfType_Active_PADOUTPUT" rev="61">
<attrib name="value" value="115"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="59">
<attrib name="value" value="697"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="59">
<item name="NumNodesOfType_Active_PINBOUNCE" rev="61">
<attrib name="value" value="729"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="61">
<attrib name="value" value="3910"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="59">
<attrib name="value" value="5368"/></item>
<item name="NumNodesOfType_Active_REGINPUT" rev="59">
<attrib name="value" value="308"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="59">
<attrib name="value" value="2239"/></item>
<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="59">
<item name="NumNodesOfType_Active_QUAD" rev="61">
<attrib name="value" value="5288"/></item>
<item name="NumNodesOfType_Active_REGINPUT" rev="61">
<attrib name="value" value="311"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="61">
<attrib name="value" value="2284"/></item>
<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="61">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_GENERIC" rev="59">
<item name="NumNodesOfType_Vcc_GENERIC" rev="61">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="59">
<attrib name="value" value="102"/></item>
<item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="59">
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="61">
<attrib name="value" value="101"/></item>
<item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="61">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_IOBOUTPUT" rev="59">
<item name="NumNodesOfType_Vcc_IOBOUTPUT" rev="61">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_KVCCOUT" rev="59">
<item name="NumNodesOfType_Vcc_KVCCOUT" rev="61">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="59">
<attrib name="value" value="238"/></item>
<item name="NumNodesOfType_Vcc_PADINPUT" rev="59">
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="61">
<attrib name="value" value="237"/></item>
<item name="NumNodesOfType_Vcc_PADINPUT" rev="61">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_PINBOUNCE" rev="59">
<item name="NumNodesOfType_Vcc_PINBOUNCE" rev="61">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="59">
<attrib name="value" value="251"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="61">
<attrib name="value" value="250"/></item>
</group>
<group name="SiteStatistics">
<item name="BUFG-BUFGMUX" rev="61">
<attrib name="value" value="3"/></item>
<item name="IOB-IOBM" rev="61">
<attrib name="value" value="162"/></item>
<item name="IOB-IOBS" rev="61">
<attrib name="value" value="165"/></item>
<item name="SLICEL-SLICEM" rev="61">
<attrib name="value" value="14"/></item>
<item name="SLICEX-SLICEL" rev="61">
<attrib name="value" value="78"/></item>
<item name="SLICEX-SLICEM" rev="61">
<attrib name="value" value="81"/></item>
</group>
<group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="58">
<item name="AGG_BONDED_IO" rev="60">
<attrib name="value" value="331"/></item>
<item name="AGG_IO" rev="58">
<item name="AGG_IO" rev="60">
<attrib name="value" value="331"/></item>
<item name="AGG_LOCED_IO" rev="58">
<item name="AGG_LOCED_IO" rev="60">
<attrib name="value" value="329"/></item>
<item name="AGG_SLICE" rev="58">
<attrib name="value" value="392"/></item>
<item name="NUM_BONDED_IOB" rev="58">
<item name="AGG_SLICE" rev="60">
<attrib name="value" value="386"/></item>
<item name="NUM_BONDED_IOB" rev="60">
<attrib name="value" value="327"/></item>
<item name="NUM_BONDED_IOBM" rev="58">
<item name="NUM_BONDED_IOBM" rev="60">
<attrib name="value" value="2"/></item>
<item name="NUM_BONDED_IOBS" rev="58">
<item name="NUM_BONDED_IOBS" rev="60">
<attrib name="value" value="2"/></item>
<item name="NUM_BSFULL" rev="58">
<attrib name="value" value="479"/></item>
<item name="NUM_BSLUTONLY" rev="58">
<attrib name="value" value="372"/></item>
<item name="NUM_BSREGONLY" rev="58">
<attrib name="value" value="209"/></item>
<item name="NUM_BSUSED" rev="58">
<attrib name="value" value="1060"/></item>
<item name="NUM_BUFG" rev="58">
<item name="NUM_BSFULL" rev="60">
<attrib name="value" value="493"/></item>
<item name="NUM_BSLUTONLY" rev="60">
<attrib name="value" value="356"/></item>
<item name="NUM_BSREGONLY" rev="60">
<attrib name="value" value="197"/></item>
<item name="NUM_BSUSED" rev="60">
<attrib name="value" value="1046"/></item>
<item name="NUM_BUFG" rev="60">
<attrib name="value" value="3"/></item>
<item name="NUM_DPRAM_O5ANDO6" rev="58">
<item name="NUM_DPRAM_O5ANDO6" rev="60">
<attrib name="value" value="4"/></item>
<item name="NUM_DPRAM_O6ONLY" rev="58">
<item name="NUM_DPRAM_O6ONLY" rev="60">
<attrib name="value" value="4"/></item>
<item name="NUM_LOCED_IOB" rev="58">
<item name="NUM_LOCED_IOB" rev="60">
<attrib name="value" value="325"/></item>
<item name="NUM_LOCED_IOBM" rev="58">
<item name="NUM_LOCED_IOBM" rev="60">
<attrib name="value" value="2"/></item>
<item name="NUM_LOCED_IOBS" rev="58">
<item name="NUM_LOCED_IOBS" rev="60">
<attrib name="value" value="2"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="58">
<item name="NUM_LOGIC_O5ANDO6" rev="60">
<attrib name="value" value="124"/></item>
<item name="NUM_LOGIC_O5ONLY" rev="58">
<item name="NUM_LOGIC_O5ONLY" rev="60">
<attrib name="value" value="83"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="58">
<item name="NUM_LOGIC_O6ONLY" rev="60">
<attrib name="value" value="616"/></item>
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="58">
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="60">
<attrib name="value" value="5"/></item>
<item name="NUM_LUT_RT_DRIVES_FLOP" rev="58">
<attrib name="value" value="9"/></item>
<item name="NUM_LUT_RT_EXO5" rev="58">
<attrib name="value" value="9"/></item>
<item name="NUM_LUT_RT_EXO6" rev="58">
<attrib name="value" value="5"/></item>
<item name="NUM_LUT_RT_O5" rev="58">
<item name="NUM_LUT_RT_DRIVES_FLOP" rev="60">
<attrib name="value" value="7"/></item>
<item name="NUM_LUT_RT_EXO5" rev="60">
<attrib name="value" value="7"/></item>
<item name="NUM_LUT_RT_O6" rev="58">
<item name="NUM_LUT_RT_EXO6" rev="60">
<attrib name="value" value="5"/></item>
<item name="NUM_LUT_RT_O5" rev="60">
<attrib name="value" value="6"/></item>
<item name="NUM_LUT_RT_O6" rev="60">
<attrib name="value" value="83"/></item>
<item name="NUM_SLICEL" rev="58">
<item name="NUM_SLICEL" rev="60">
<attrib name="value" value="51"/></item>
<item name="NUM_SLICEM" rev="58">
<item name="NUM_SLICEM" rev="60">
<attrib name="value" value="4"/></item>
<item name="NUM_SLICEX" rev="58">
<attrib name="value" value="337"/></item>
<item name="NUM_SLICE_CARRY4" rev="58">
<item name="NUM_SLICEX" rev="60">
<attrib name="value" value="331"/></item>
<item name="NUM_SLICE_CARRY4" rev="60">
<attrib name="value" value="29"/></item>
<item name="NUM_SLICE_CONTROLSET" rev="58">
<item name="NUM_SLICE_CONTROLSET" rev="60">
<attrib name="value" value="27"/></item>
<item name="NUM_SLICE_CYINIT" rev="58">
<attrib name="value" value="1078"/></item>
<item name="NUM_SLICE_F7MUX" rev="58">
<item name="NUM_SLICE_CYINIT" rev="60">
<attrib name="value" value="1075"/></item>
<item name="NUM_SLICE_F7MUX" rev="60">
<attrib name="value" value="22"/></item>
<item name="NUM_SLICE_FF" rev="58">
<item name="NUM_SLICE_FF" rev="60">
<attrib name="value" value="765"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="58">
<attrib name="value" value="166"/></item>
<item name="NUM_SRL_O5ANDO6" rev="58">
<item name="NUM_SLICE_UNUSEDCTRL" rev="60">
<attrib name="value" value="159"/></item>
<item name="NUM_SRL_O5ANDO6" rev="60">
<attrib name="value" value="2"/></item>
<item name="NUM_SRL_O6ONLY" rev="58">
<item name="NUM_SRL_O6ONLY" rev="60">
<attrib name="value" value="4"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="58">
<item name="NUM_UNUSABLE_FF_BELS" rev="60">
<attrib name="value" value="71"/></item>
</group>
<group name="SiteStatistics">
<item name="BUFG-BUFGMUX" rev="59">
<attrib name="value" value="3"/></item>
<item name="IOB-IOBM" rev="59">
<attrib name="value" value="162"/></item>
<item name="IOB-IOBS" rev="59">
<attrib name="value" value="165"/></item>
<item name="SLICEL-SLICEM" rev="59">
<attrib name="value" value="24"/></item>
<item name="SLICEX-SLICEL" rev="59">
<attrib name="value" value="87"/></item>
<item name="SLICEX-SLICEM" rev="59">
<attrib name="value" value="77"/></item>
</group>
</DesignStatistics>
<DeviceUsage TimeStamp="Fri Jan 28 11:56:18 2011"><group name="SiteSummary">
<item name="BUFG" rev="59">
<DeviceUsage TimeStamp="Fri Jan 28 15:09:13 2011"><group name="SiteSummary">
<item name="BUFG" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="BUFG_BUFG" rev="59">
<item name="BUFG_BUFG" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="CARRY4" rev="59">
<item name="CARRY4" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="29"/></item>
<item name="FF_SR" rev="59">
<attrib name="total" value="1000000"/><attrib name="used" value="87"/></item>
<item name="HARD0" rev="59">
<item name="FF_SR" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="85"/></item>
<item name="HARD0" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="5"/></item>
<item name="HARD1" rev="59">
<item name="HARD1" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOB" rev="59">
<item name="IOB" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="327"/></item>
<item name="IOBM" rev="59">
<item name="IOBM" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOBM_OUTBUF" rev="59">
<item name="IOBM_OUTBUF" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOBS" rev="59">
<item name="IOBS" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOB_IMUX" rev="59">
<item name="IOB_IMUX" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="160"/></item>
<item name="IOB_INBUF" rev="59">
<item name="IOB_INBUF" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="160"/></item>
<item name="IOB_OUTBUF" rev="59">
<item name="IOB_OUTBUF" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="198"/></item>
<item name="LUT5" rev="59">
<attrib name="total" value="1000000"/><attrib name="used" value="223"/></item>
<item name="LUT6" rev="59">
<item name="LUT5" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="220"/></item>
<item name="LUT6" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="828"/></item>
<item name="LUT_OR_MEM5" rev="59">
<item name="LUT_OR_MEM5" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="6"/></item>
<item name="LUT_OR_MEM6" rev="59">
<item name="LUT_OR_MEM6" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="14"/></item>
<item name="NULLMUX" rev="59">
<item name="NULLMUX" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="PAD" rev="59">
<item name="PAD" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="331"/></item>
<item name="REG_SR" rev="59">
<attrib name="total" value="1000000"/><attrib name="used" value="678"/></item>
<item name="SELMUX2_1" rev="59">
<item name="REG_SR" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="680"/></item>
<item name="SELMUX2_1" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="22"/></item>
<item name="SLICEL" rev="59">
<item name="SLICEL" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="51"/></item>
<item name="SLICEM" rev="59">
<item name="SLICEM" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="SLICEX" rev="59">
<attrib name="total" value="1000000"/><attrib name="used" value="337"/></item>
<item name="SLICEX" rev="61">
<attrib name="total" value="1000000"/><attrib name="used" value="331"/></item>
</group>
</DeviceUsage>
<ReportConfigData TimeStamp="Fri Jan 28 11:56:18 2011"><group name="REG_SR">
<item name="CK" rev="59">
<attrib name="CK" value="678"/><attrib name="CK_INV" value="0"/></item>
<item name="LATCH_OR_FF" rev="59">
<attrib name="FF" value="678"/></item>
<item name="SRINIT" rev="59">
<attrib name="SRINIT0" value="651"/><attrib name="SRINIT1" value="27"/></item>
<item name="SYNC_ATTR" rev="59">
<attrib name="ASYNC" value="222"/><attrib name="SYNC" value="456"/></item>
<ReportConfigData TimeStamp="Fri Jan 28 15:09:13 2011"><group name="REG_SR">
<item name="CK" rev="61">
<attrib name="CK" value="680"/><attrib name="CK_INV" value="0"/></item>
<item name="LATCH_OR_FF" rev="61">
<attrib name="FF" value="680"/></item>
<item name="SRINIT" rev="61">
<attrib name="SRINIT0" value="653"/><attrib name="SRINIT1" value="27"/></item>
<item name="SYNC_ATTR" rev="61">
<attrib name="ASYNC" value="222"/><attrib name="SYNC" value="458"/></item>
</group>
<group name="LUT_OR_MEM5">
<item name="CLK" rev="59">
<item name="CLK" rev="61">
<attrib name="CLK" value="6"/><attrib name="CLK_INV" value="0"/></item>
<item name="LUT_OR_MEM" rev="59">
<item name="LUT_OR_MEM" rev="61">
<attrib name="RAM" value="6"/></item>
<item name="RAMMODE" rev="59">
<item name="RAMMODE" rev="61">
<attrib name="SRL16" value="2"/><attrib name="DPRAM32" value="4"/></item>
</group>
<group name="LUT_OR_MEM6">
<item name="CLK" rev="59">
<item name="CLK" rev="61">
<attrib name="CLK" value="14"/><attrib name="CLK_INV" value="0"/></item>
<item name="LUT_OR_MEM" rev="59">
<item name="LUT_OR_MEM" rev="61">
<attrib name="RAM" value="14"/></item>
<item name="RAMMODE" rev="59">
<item name="RAMMODE" rev="61">
<attrib name="SRL16" value="6"/><attrib name="DPRAM32" value="4"/><attrib name="DPRAM64" value="4"/></item>
</group>
<group name="IOBM_OUTBUF">
<item name="SUSPEND" rev="59">
<item name="SUSPEND" rev="61">
<attrib name="3STATE" value="2"/></item>
</group>
<group name="SLICEL">
<item name="CLK" rev="59">
<attrib name="CLK" value="25"/><attrib name="CLK_INV" value="0"/></item>
<item name="CLK" rev="61">
<attrib name="CLK" value="24"/><attrib name="CLK_INV" value="0"/></item>
</group>
<group name="SLICEM">
<item name="CLK" rev="59">
<item name="CLK" rev="61">
<attrib name="CLK" value="4"/><attrib name="CLK_INV" value="0"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="DRIVEATTRBOX" rev="59">
<item name="DRIVEATTRBOX" rev="61">
<attrib name="12" value="167"/></item>
<item name="SLEW" rev="59">
<item name="SLEW" rev="61">
<attrib name="SLOW" value="167"/></item>
<item name="SUSPEND" rev="59">
<item name="SUSPEND" rev="61">
<attrib name="3STATE" value="198"/></item>
</group>
<group name="SLICEX">
<item name="CLK" rev="59">
<attrib name="CLK" value="197"/><attrib name="CLK_INV" value="0"/></item>
<item name="CLK" rev="61">
<attrib name="CLK" value="199"/><attrib name="CLK_INV" value="0"/></item>
</group>
<group name="IOB_INBUF">
<item name="DIFF_TERM" rev="59">
<item name="DIFF_TERM" rev="61">
<attrib name="TRUE" value="1"/></item>
</group>
<group name="FF_SR">
<item name="CK" rev="59">
<attrib name="CK" value="87"/><attrib name="CK_INV" value="0"/></item>
<item name="SRINIT" rev="59">
<attrib name="SRINIT0" value="76"/><attrib name="SRINIT1" value="11"/></item>
<item name="SYNC_ATTR" rev="59">
<attrib name="ASYNC" value="49"/><attrib name="SYNC" value="38"/></item>
<item name="CK" rev="61">
<attrib name="CK" value="85"/><attrib name="CK_INV" value="0"/></item>
<item name="SRINIT" rev="61">
<attrib name="SRINIT0" value="74"/><attrib name="SRINIT1" value="11"/></item>
<item name="SYNC_ATTR" rev="61">
<attrib name="ASYNC" value="49"/><attrib name="SYNC" value="36"/></item>
</group>
</ReportConfigData>
<ReportPinData TimeStamp="Fri Jan 28 11:56:18 2011"><group name="NULLMUX">
<item name="0" rev="59">
<ReportPinData TimeStamp="Fri Jan 28 15:09:13 2011"><group name="NULLMUX">
<item name="0" rev="61">
<attrib name="value" value="3"/></item>
<item name="OUT" rev="59">
<item name="OUT" rev="61">
<attrib name="value" value="3"/></item>
</group>
<group name="REG_SR">
<item name="CE" rev="59">
<attrib name="value" value="375"/></item>
<item name="CK" rev="59">
<attrib name="value" value="678"/></item>
<item name="D" rev="59">
<attrib name="value" value="678"/></item>
<item name="Q" rev="59">
<attrib name="value" value="678"/></item>
<item name="SR" rev="59">
<attrib name="value" value="457"/></item>
<item name="CE" rev="61">
<attrib name="value" value="376"/></item>
<item name="CK" rev="61">
<attrib name="value" value="680"/></item>
<item name="D" rev="61">
<attrib name="value" value="680"/></item>
<item name="Q" rev="61">
<attrib name="value" value="680"/></item>
<item name="SR" rev="61">
<attrib name="value" value="459"/></item>
</group>
<group name="LUT_OR_MEM5">
<item name="A1" rev="59">
<item name="A1" rev="61">
<attrib name="value" value="6"/></item>
<item name="A2" rev="59">
<item name="A2" rev="61">
<attrib name="value" value="6"/></item>
<item name="A3" rev="59">
<item name="A3" rev="61">
<attrib name="value" value="6"/></item>
<item name="A4" rev="59">
<item name="A4" rev="61">
<attrib name="value" value="6"/></item>
<item name="A5" rev="59">
<item name="A5" rev="61">
<attrib name="value" value="6"/></item>
<item name="CLK" rev="59">
<item name="CLK" rev="61">
<attrib name="value" value="6"/></item>
<item name="DI1" rev="59">
<item name="DI1" rev="61">
<attrib name="value" value="6"/></item>
<item name="O5" rev="59">
<item name="O5" rev="61">
<attrib name="value" value="6"/></item>
<item name="WA1" rev="59">
<item name="WA1" rev="61">
<attrib name="value" value="4"/></item>
<item name="WA2" rev="59">
<item name="WA2" rev="61">
<attrib name="value" value="4"/></item>
<item name="WA3" rev="59">
<item name="WA3" rev="61">
<attrib name="value" value="4"/></item>
<item name="WA4" rev="59">
<item name="WA4" rev="61">
<attrib name="value" value="4"/></item>
<item name="WA5" rev="59">
<item name="WA5" rev="61">
<attrib name="value" value="4"/></item>
<item name="WE" rev="59">
<item name="WE" rev="61">
<attrib name="value" value="6"/></item>
</group>
<group name="LUT_OR_MEM6">
<item name="A1" rev="59">
<item name="A1" rev="61">
<attrib name="value" value="14"/></item>
<item name="A2" rev="59">
<item name="A2" rev="61">
<attrib name="value" value="14"/></item>
<item name="A3" rev="59">
<item name="A3" rev="61">
<attrib name="value" value="14"/></item>
<item name="A4" rev="59">
<item name="A4" rev="61">
<attrib name="value" value="14"/></item>
<item name="A5" rev="59">
<item name="A5" rev="61">
<attrib name="value" value="14"/></item>
<item name="A6" rev="59">
<item name="A6" rev="61">
<attrib name="value" value="14"/></item>
<item name="CLK" rev="59">
<item name="CLK" rev="61">
<attrib name="value" value="14"/></item>
<item name="DI1" rev="59">
<item name="DI1" rev="61">
<attrib name="value" value="4"/></item>
<item name="DI2" rev="59">
<item name="DI2" rev="61">
<attrib name="value" value="10"/></item>
<item name="O6" rev="59">
<item name="O6" rev="61">
<attrib name="value" value="11"/></item>
<item name="WA1" rev="59">
<item name="WA1" rev="61">
<attrib name="value" value="8"/></item>
<item name="WA2" rev="59">
<item name="WA2" rev="61">
<attrib name="value" value="8"/></item>
<item name="WA3" rev="59">
<item name="WA3" rev="61">
<attrib name="value" value="8"/></item>
<item name="WA4" rev="59">
<item name="WA4" rev="61">
<attrib name="value" value="8"/></item>
<item name="WA5" rev="59">
<item name="WA5" rev="61">
<attrib name="value" value="8"/></item>
<item name="WA6" rev="59">
<item name="WA6" rev="61">
<attrib name="value" value="8"/></item>
<item name="WE" rev="59">
<item name="WE" rev="61">
<attrib name="value" value="14"/></item>
</group>
<group name="IOBM_OUTBUF">
<item name="IN" rev="59">
<item name="IN" rev="61">
<attrib name="value" value="2"/></item>
<item name="OUT" rev="59">
<item name="OUT" rev="61">
<attrib name="value" value="2"/></item>
<item name="OUTN" rev="59">
<item name="OUTN" rev="61">
<attrib name="value" value="2"/></item>
</group>
<group name="SLICEL">
<item name="A" rev="59">
<attrib name="value" value="11"/></item>
<item name="A1" rev="59">
<item name="A" rev="61">
<attrib name="value" value="5"/></item>
<item name="A1" rev="61">
<attrib name="value" value="4"/></item>
<item name="A2" rev="61">
<attrib name="value" value="7"/></item>
<item name="A2" rev="59">
<attrib name="value" value="12"/></item>
<item name="A3" rev="59">
<attrib name="value" value="16"/></item>
<item name="A4" rev="59">
<attrib name="value" value="32"/></item>
<item name="A5" rev="59">
<attrib name="value" value="25"/></item>
<item name="A6" rev="59">
<attrib name="value" value="41"/></item>
<item name="AMUX" rev="59">
<item name="A3" rev="61">
<attrib name="value" value="10"/></item>
<item name="AQ" rev="59">
<item name="A4" rev="61">
<attrib name="value" value="26"/></item>
<item name="A5" rev="61">
<attrib name="value" value="19"/></item>
<item name="A6" rev="61">
<attrib name="value" value="35"/></item>
<item name="AMUX" rev="61">
<attrib name="value" value="9"/></item>
<item name="AQ" rev="61">
<attrib name="value" value="23"/></item>
<item name="AX" rev="59">
<item name="AX" rev="61">
<attrib name="value" value="7"/></item>
<item name="B" rev="59">
<attrib name="value" value="8"/></item>
<item name="B1" rev="59">
<item name="B" rev="61">
<attrib name="value" value="6"/></item>
<item name="B2" rev="59">
<attrib name="value" value="9"/></item>
<item name="B3" rev="59">
<attrib name="value" value="12"/></item>
<item name="B4" rev="59">
<attrib name="value" value="31"/></item>
<item name="B5" rev="59">
<attrib name="value" value="22"/></item>
<item name="B6" rev="59">
<attrib name="value" value="38"/></item>
<item name="BMUX" rev="59">
<attrib name="value" value="12"/></item>
<item name="BQ" rev="59">
<item name="B1" rev="61">
<attrib name="value" value="6"/></item>
<item name="B2" rev="61">
<attrib name="value" value="8"/></item>
<item name="B3" rev="61">
<attrib name="value" value="11"/></item>
<item name="B4" rev="61">
<attrib name="value" value="29"/></item>
<item name="B5" rev="61">
<attrib name="value" value="20"/></item>
<item name="B6" rev="61">
<attrib name="value" value="36"/></item>
<item name="BMUX" rev="61">
<attrib name="value" value="11"/></item>
<item name="BQ" rev="61">
<attrib name="value" value="23"/></item>
<item name="BX" rev="59">
<item name="BX" rev="61">
<attrib name="value" value="6"/></item>
<item name="C1" rev="59">
<attrib name="value" value="10"/></item>
<item name="C2" rev="59">
<attrib name="value" value="14"/></item>
<item name="C3" rev="59">
<item name="C1" rev="61">
<attrib name="value" value="9"/></item>
<item name="C2" rev="61">
<attrib name="value" value="13"/></item>
<item name="C3" rev="61">
<attrib name="value" value="25"/></item>
<item name="C4" rev="59">
<item name="C4" rev="61">
<attrib name="value" value="41"/></item>
<item name="C5" rev="59">
<item name="C5" rev="61">
<attrib name="value" value="34"/></item>
<item name="C6" rev="59">
<item name="C6" rev="61">
<attrib name="value" value="49"/></item>
<item name="CE" rev="59">
<attrib name="value" value="10"/></item>
<item name="CIN" rev="59">
<item name="CE" rev="61">
<attrib name="value" value="11"/></item>
<item name="CIN" rev="61">
<attrib name="value" value="21"/></item>
<item name="CLK" rev="59">
<attrib name="value" value="25"/></item>
<item name="CMUX" rev="59">
<item name="CLK" rev="61">
<attrib name="value" value="24"/></item>
<item name="CMUX" rev="61">
<attrib name="value" value="29"/></item>
<item name="COUT" rev="59">
<item name="COUT" rev="61">
<attrib name="value" value="21"/></item>
<item name="CQ" rev="59">
<item name="CQ" rev="61">
<attrib name="value" value="23"/></item>
<item name="CX" rev="59">
<attrib name="value" value="25"/></item>
<item name="D" rev="59">
<item name="CX" rev="61">
<attrib name="value" value="26"/></item>
<item name="D" rev="61">
<attrib name="value" value="2"/></item>
<item name="D1" rev="59">
<item name="D1" rev="61">
<attrib name="value" value="13"/></item>
<item name="D2" rev="59">
<item name="D2" rev="61">
<attrib name="value" value="25"/></item>
<item name="D3" rev="59">
<item name="D3" rev="61">
<attrib name="value" value="26"/></item>
<item name="D4" rev="59">
<item name="D4" rev="61">
<attrib name="value" value="42"/></item>
<item name="D5" rev="59">
<item name="D5" rev="61">
<attrib name="value" value="32"/></item>
<item name="D6" rev="59">
<item name="D6" rev="61">
<attrib name="value" value="47"/></item>
<item name="DMUX" rev="59">
<item name="DMUX" rev="61">
<attrib name="value" value="7"/></item>
<item name="DQ" rev="59">
<item name="DQ" rev="61">
<attrib name="value" value="21"/></item>
<item name="DX" rev="59">
<item name="DX" rev="61">
<attrib name="value" value="6"/></item>
<item name="SR" rev="59">
<attrib name="value" value="16"/></item>
<item name="SR" rev="61">
<attrib name="value" value="17"/></item>
</group>
<group name="SLICEM">
<item name="A" rev="59">
<item name="A" rev="61">
<attrib name="value" value="2"/></item>
<item name="A1" rev="59">
<item name="A1" rev="61">
<attrib name="value" value="3"/></item>
<item name="A2" rev="59">
<item name="A2" rev="61">
<attrib name="value" value="3"/></item>
<item name="A3" rev="59">
<item name="A3" rev="61">
<attrib name="value" value="3"/></item>
<item name="A4" rev="59">
<item name="A4" rev="61">
<attrib name="value" value="3"/></item>
<item name="A5" rev="59">
<item name="A5" rev="61">
<attrib name="value" value="3"/></item>
<item name="A6" rev="59">
<item name="A6" rev="61">
<attrib name="value" value="3"/></item>
<item name="AI" rev="59">
<item name="AI" rev="61">
<attrib name="value" value="2"/></item>
<item name="AMUX" rev="59">
<item name="AMUX" rev="61">
<attrib name="value" value="2"/></item>
<item name="AQ" rev="59">
<item name="AQ" rev="61">
<attrib name="value" value="1"/></item>
<item name="AX" rev="59">
<item name="AX" rev="61">
<attrib name="value" value="3"/></item>
<item name="B" rev="59">
<item name="B" rev="61">
<attrib name="value" value="2"/></item>
<item name="B1" rev="59">
<item name="B1" rev="61">
<attrib name="value" value="3"/></item>
<item name="B2" rev="59">
<item name="B2" rev="61">
<attrib name="value" value="3"/></item>
<item name="B3" rev="59">
<item name="B3" rev="61">
<attrib name="value" value="3"/></item>
<item name="B4" rev="59">
<item name="B4" rev="61">
<attrib name="value" value="3"/></item>
<item name="B5" rev="59">
<item name="B5" rev="61">
<attrib name="value" value="3"/></item>
<item name="B6" rev="59">
<item name="B6" rev="61">
<attrib name="value" value="3"/></item>
<item name="BI" rev="59">
<item name="BI" rev="61">
<attrib name="value" value="2"/></item>
<item name="BMUX" rev="59">
<item name="BMUX" rev="61">
<attrib name="value" value="2"/></item>
<item name="BQ" rev="59">
<item name="BQ" rev="61">
<attrib name="value" value="1"/></item>
<item name="BX" rev="59">
<item name="BX" rev="61">
<attrib name="value" value="2"/></item>
<item name="C" rev="59">
<item name="C" rev="61">
<attrib name="value" value="1"/></item>
<item name="C1" rev="59">
<item name="C1" rev="61">
<attrib name="value" value="4"/></item>
<item name="C2" rev="59">
<item name="C2" rev="61">
<attrib name="value" value="4"/></item>
<item name="C3" rev="59">
<item name="C3" rev="61">
<attrib name="value" value="4"/></item>
<item name="C4" rev="59">
<item name="C4" rev="61">
<attrib name="value" value="4"/></item>
<item name="C5" rev="59">
<item name="C5" rev="61">
<attrib name="value" value="4"/></item>
<item name="C6" rev="59">
<item name="C6" rev="61">
<attrib name="value" value="4"/></item>
<item name="CE" rev="59">
<item name="CE" rev="61">
<attrib name="value" value="4"/></item>
<item name="CI" rev="59">
<item name="CI" rev="61">
<attrib name="value" value="3"/></item>
<item name="CLK" rev="59">
<item name="CLK" rev="61">
<attrib name="value" value="4"/></item>
<item name="CMUX" rev="59">
<item name="CMUX" rev="61">
<attrib name="value" value="1"/></item>
<item name="CQ" rev="59">
<item name="CQ" rev="61">
<attrib name="value" value="2"/></item>
<item name="CX" rev="59">
<item name="CX" rev="61">
<attrib name="value" value="2"/></item>
<item name="D1" rev="59">
<item name="D1" rev="61">
<attrib name="value" value="4"/></item>
<item name="D2" rev="59">
<item name="D2" rev="61">
<attrib name="value" value="4"/></item>
<item name="D3" rev="59">
<item name="D3" rev="61">
<attrib name="value" value="4"/></item>
<item name="D4" rev="59">
<item name="D4" rev="61">
<attrib name="value" value="4"/></item>
<item name="D5" rev="59">
<item name="D5" rev="61">
<attrib name="value" value="4"/></item>
<item name="D6" rev="59">
<item name="D6" rev="61">
<attrib name="value" value="4"/></item>
<item name="DI" rev="59">
<item name="DI" rev="61">
<attrib name="value" value="3"/></item>
<item name="DMUX" rev="59">
<item name="DMUX" rev="61">
<attrib name="value" value="1"/></item>
<item name="DQ" rev="59">
<item name="DQ" rev="61">
<attrib name="value" value="2"/></item>
<item name="DX" rev="59">
<item name="DX" rev="61">
<attrib name="value" value="2"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="IN" rev="59">
<item name="IN" rev="61">
<attrib name="value" value="198"/></item>
<item name="OUT" rev="59">
<item name="OUT" rev="61">
<attrib name="value" value="198"/></item>
<item name="TRI" rev="59">
<item name="TRI" rev="61">
<attrib name="value" value="42"/></item>
</group>
<group name="SLICEX">
<item name="A" rev="59">
<attrib name="value" value="144"/></item>
<item name="A1" rev="59">
<attrib name="value" value="99"/></item>
<item name="A2" rev="59">
<attrib name="value" value="135"/></item>
<item name="A3" rev="59">
<attrib name="value" value="175"/></item>
<item name="A4" rev="59">
<attrib name="value" value="193"/></item>
<item name="A5" rev="59">
<attrib name="value" value="211"/></item>
<item name="A6" rev="59">
<attrib name="value" value="216"/></item>
<item name="AMUX" rev="59">
<attrib name="value" value="38"/></item>
<item name="AQ" rev="59">
<attrib name="value" value="149"/></item>
<item name="AX" rev="59">
<attrib name="value" value="73"/></item>
<item name="B" rev="59">
<attrib name="value" value="56"/></item>
<item name="B1" rev="59">
<attrib name="value" value="55"/></item>
<item name="B2" rev="59">
<attrib name="value" value="76"/></item>
<item name="B3" rev="59">
<attrib name="value" value="108"/></item>
<item name="B4" rev="59">
<attrib name="value" value="128"/></item>
<item name="B5" rev="59">
<attrib name="value" value="146"/></item>
<item name="B6" rev="59">
<attrib name="value" value="144"/></item>
<item name="BMUX" rev="59">
<attrib name="value" value="29"/></item>
<item name="BQ" rev="59">
<item name="A" rev="61">
<attrib name="value" value="139"/></item>
<item name="A1" rev="61">
<attrib name="value" value="90"/></item>
<item name="A2" rev="61">
<attrib name="value" value="131"/></item>
<item name="A3" rev="61">
<attrib name="value" value="170"/></item>
<item name="A4" rev="61">
<attrib name="value" value="191"/></item>
<item name="A5" rev="61">
<attrib name="value" value="205"/></item>
<item name="A6" rev="61">
<attrib name="value" value="212"/></item>
<item name="AMUX" rev="61">
<attrib name="value" value="36"/></item>
<item name="AQ" rev="61">
<attrib name="value" value="154"/></item>
<item name="BX" rev="59">
<attrib name="value" value="66"/></item>
<item name="C" rev="59">
<attrib name="value" value="60"/></item>
<item name="C1" rev="59">
<item name="AX" rev="61">
<attrib name="value" value="78"/></item>
<item name="B" rev="61">
<attrib name="value" value="55"/></item>
<item name="C2" rev="59">
<attrib name="value" value="70"/></item>
<item name="C3" rev="59">
<attrib name="value" value="93"/></item>
<item name="C4" rev="59">
<attrib name="value" value="111"/></item>
<item name="C5" rev="59">
<attrib name="value" value="126"/></item>
<item name="C6" rev="59">
<attrib name="value" value="126"/></item>
<item name="CE" rev="59">
<item name="B1" rev="61">
<attrib name="value" value="52"/></item>
<item name="B2" rev="61">
<attrib name="value" value="72"/></item>
<item name="B3" rev="61">
<attrib name="value" value="103"/></item>
<item name="B4" rev="61">
<attrib name="value" value="124"/></item>
<item name="B5" rev="61">
<attrib name="value" value="143"/></item>
<item name="B6" rev="61">
<attrib name="value" value="142"/></item>
<item name="BMUX" rev="61">
<attrib name="value" value="25"/></item>
<item name="BQ" rev="61">
<attrib name="value" value="152"/></item>
<item name="BX" rev="61">
<attrib name="value" value="65"/></item>
<item name="C" rev="61">
<attrib name="value" value="62"/></item>
<item name="C1" rev="61">
<attrib name="value" value="63"/></item>
<item name="C2" rev="61">
<attrib name="value" value="75"/></item>
<item name="C3" rev="61">
<attrib name="value" value="98"/></item>
<item name="C4" rev="61">
<attrib name="value" value="117"/></item>
<item name="C5" rev="61">
<attrib name="value" value="130"/></item>
<item name="C6" rev="61">
<attrib name="value" value="128"/></item>
<item name="CE" rev="61">
<attrib name="value" value="93"/></item>
<item name="CLK" rev="59">
<attrib name="value" value="197"/></item>
<item name="CMUX" rev="59">
<attrib name="value" value="23"/></item>
<item name="CQ" rev="59">
<attrib name="value" value="129"/></item>
<item name="CX" rev="59">
<item name="CLK" rev="61">
<attrib name="value" value="199"/></item>
<item name="CMUX" rev="61">
<attrib name="value" value="22"/></item>
<item name="CQ" rev="61">
<attrib name="value" value="131"/></item>
<item name="CX" rev="61">
<attrib name="value" value="63"/></item>
<item name="D" rev="59">
<attrib name="value" value="73"/></item>
<item name="D1" rev="59">
<attrib name="value" value="61"/></item>
<item name="D2" rev="59">
<attrib name="value" value="84"/></item>
<item name="D3" rev="59">
<attrib name="value" value="114"/></item>
<item name="D4" rev="59">
<attrib name="value" value="138"/></item>
<item name="D5" rev="59">
<attrib name="value" value="158"/></item>
<item name="D6" rev="59">
<attrib name="value" value="160"/></item>
<item name="DMUX" rev="59">
<attrib name="value" value="26"/></item>
<item name="DQ" rev="59">
<attrib name="value" value="150"/></item>
<item name="DX" rev="59">
<attrib name="value" value="62"/></item>
<item name="SR" rev="59">
<attrib name="value" value="132"/></item>
<item name="D" rev="61">
<attrib name="value" value="85"/></item>
<item name="D1" rev="61">
<attrib name="value" value="68"/></item>
<item name="D2" rev="61">
<attrib name="value" value="93"/></item>
<item name="D3" rev="61">
<attrib name="value" value="126"/></item>
<item name="D4" rev="61">
<attrib name="value" value="146"/></item>
<item name="D5" rev="61">
<attrib name="value" value="169"/></item>
<item name="D6" rev="61">
<attrib name="value" value="172"/></item>
<item name="DMUX" rev="61">
<attrib name="value" value="33"/></item>
<item name="DQ" rev="61">
<attrib name="value" value="147"/></item>
<item name="DX" rev="61">
<attrib name="value" value="60"/></item>
<item name="SR" rev="61">
<attrib name="value" value="133"/></item>
</group>
<group name="BUFG_BUFG">
<item name="I0" rev="59">
<item name="I0" rev="61">
<attrib name="value" value="3"/></item>
<item name="O" rev="59">
<item name="O" rev="61">
<attrib name="value" value="3"/></item>
</group>
<group name="PAD">
<item name="PAD" rev="59">
<item name="PAD" rev="61">
<attrib name="value" value="331"/></item>
</group>
<group name="IOB_INBUF">
<item name="DIFFI_IN" rev="59">
<item name="DIFFI_IN" rev="61">
<attrib name="value" value="1"/></item>
<item name="OUT" rev="59">
<item name="OUT" rev="61">
<attrib name="value" value="160"/></item>
<item name="PAD" rev="59">
<item name="PAD" rev="61">
<attrib name="value" value="160"/></item>
</group>
<group name="IOBM">
<item name="DIFFO_OUT" rev="59">
<item name="DIFFO_OUT" rev="61">
<attrib name="value" value="2"/></item>
<item name="O" rev="59">
<item name="O" rev="61">
<attrib name="value" value="2"/></item>
<item name="PAD" rev="59">
<item name="PAD" rev="61">
<attrib name="value" value="2"/></item>
</group>
<group name="CARRY4">
<item name="CIN" rev="59">
<item name="CIN" rev="61">
<attrib name="value" value="21"/></item>
<item name="CO1" rev="59">
<item name="CO1" rev="61">
<attrib name="value" value="2"/></item>
<item name="CO2" rev="59">
<item name="CO2" rev="61">
<attrib name="value" value="1"/></item>
<item name="CO3" rev="59">
<item name="CO3" rev="61">
<attrib name="value" value="21"/></item>
<item name="CYINIT" rev="59">
<item name="CYINIT" rev="61">
<attrib name="value" value="8"/></item>
<item name="DI0" rev="59">
<item name="DI0" rev="61">
<attrib name="value" value="29"/></item>
<item name="DI1" rev="59">
<item name="DI1" rev="61">
<attrib name="value" value="29"/></item>
<item name="DI2" rev="59">
<item name="DI2" rev="61">
<attrib name="value" value="27"/></item>
<item name="DI3" rev="59">
<item name="DI3" rev="61">
<attrib name="value" value="21"/></item>
<item name="O0" rev="59">
<item name="O0" rev="61">
<attrib name="value" value="25"/></item>
<item name="O1" rev="59">
<item name="O1" rev="61">
<attrib name="value" value="25"/></item>
<item name="O2" rev="59">
<item name="O2" rev="61">
<attrib name="value" value="25"/></item>
<item name="O3" rev="59">
<item name="O3" rev="61">
<attrib name="value" value="24"/></item>
<item name="S0" rev="59">
<item name="S0" rev="61">
<attrib name="value" value="29"/></item>
<item name="S1" rev="59">
<item name="S1" rev="61">
<attrib name="value" value="29"/></item>
<item name="S2" rev="59">
<item name="S2" rev="61">
<attrib name="value" value="28"/></item>
<item name="S3" rev="59">
<item name="S3" rev="61">
<attrib name="value" value="26"/></item>
</group>
<group name="IOBS">
<item name="DIFFO_IN" rev="59">
<item name="DIFFO_IN" rev="61">
<attrib name="value" value="2"/></item>
<item name="PAD" rev="59">
<item name="PAD" rev="61">
<attrib name="value" value="2"/></item>
</group>
<group name="LUT5">
<item name="A1" rev="59">
<attrib name="value" value="26"/></item>
<item name="A2" rev="59">
<item name="A1" rev="61">
<attrib name="value" value="25"/></item>
<item name="A2" rev="61">
<attrib name="value" value="27"/></item>
<item name="A3" rev="59">
<item name="A3" rev="61">
<attrib name="value" value="96"/></item>
<item name="A4" rev="59">
<item name="A4" rev="61">
<attrib name="value" value="102"/></item>
<item name="A5" rev="59">
<attrib name="value" value="56"/></item>
<item name="O5" rev="59">
<attrib name="value" value="223"/></item>
<item name="A5" rev="61">
<attrib name="value" value="54"/></item>
<item name="O5" rev="61">
<attrib name="value" value="220"/></item>
</group>
<group name="LUT6">
<item name="A1" rev="59">
<item name="A1" rev="61">
<attrib name="value" value="281"/></item>
<item name="A2" rev="59">
<attrib name="value" value="405"/></item>
<item name="A3" rev="59">
<item name="A2" rev="61">
<attrib name="value" value="404"/></item>
<item name="A3" rev="61">
<attrib name="value" value="497"/></item>
<item name="A4" rev="59">
<item name="A4" rev="61">
<attrib name="value" value="716"/></item>
<item name="A5" rev="59">
<item name="A5" rev="61">
<attrib name="value" value="745"/></item>
<item name="A6" rev="59">
<item name="A6" rev="61">
<attrib name="value" value="821"/></item>
<item name="O6" rev="59">
<item name="O6" rev="61">
<attrib name="value" value="828"/></item>
</group>
<group name="SELMUX2_1">
<item name="0" rev="59">
<item name="0" rev="61">
<attrib name="value" value="22"/></item>
<item name="1" rev="59">
<item name="1" rev="61">
<attrib name="value" value="22"/></item>
<item name="OUT" rev="59">
<item name="OUT" rev="61">
<attrib name="value" value="22"/></item>
<item name="S0" rev="59">
<item name="S0" rev="61">
<attrib name="value" value="22"/></item>
</group>
<group name="IOB_IMUX">
<item name="I" rev="59">
<item name="I" rev="61">
<attrib name="value" value="160"/></item>
<item name="OUT" rev="59">
<item name="OUT" rev="61">
<attrib name="value" value="160"/></item>
</group>
<group name="IOB">
<item name="DIFFI_IN" rev="59">
<item name="DIFFI_IN" rev="61">
<attrib name="value" value="1"/></item>
<item name="I" rev="59">
<item name="I" rev="61">
<attrib name="value" value="160"/></item>
<item name="O" rev="59">
<item name="O" rev="61">
<attrib name="value" value="198"/></item>
<item name="PAD" rev="59">
<item name="PAD" rev="61">
<attrib name="value" value="327"/></item>
<item name="PADOUT" rev="59">
<item name="PADOUT" rev="61">
<attrib name="value" value="1"/></item>
<item name="T" rev="59">
<item name="T" rev="61">
<attrib name="value" value="42"/></item>
</group>
<group name="HARD0">
<item name="0" rev="59">
<item name="0" rev="61">
<attrib name="value" value="5"/></item>
</group>
<group name="HARD1">
<item name="1" rev="59">
<item name="1" rev="61">
<attrib name="value" value="2"/></item>
</group>
<group name="FF_SR">
<item name="CE" rev="59">
<attrib name="value" value="41"/></item>
<item name="CK" rev="59">
<attrib name="value" value="87"/></item>
<item name="D" rev="59">
<attrib name="value" value="87"/></item>
<item name="Q" rev="59">
<attrib name="value" value="87"/></item>
<item name="SR" rev="59">
<attrib name="value" value="38"/></item>
<item name="CE" rev="61">
<attrib name="value" value="40"/></item>
<item name="CK" rev="61">
<attrib name="value" value="85"/></item>
<item name="D" rev="61">
<attrib name="value" value="85"/></item>
<item name="Q" rev="61">
<attrib name="value" value="85"/></item>
<item name="SR" rev="61">
<attrib name="value" value="36"/></item>
</group>
<group name="BUFG">
<item name="I0" rev="59">
<item name="I0" rev="61">
<attrib name="value" value="3"/></item>
<item name="O" rev="59">
<item name="O" rev="61">
<attrib name="value" value="3"/></item>
</group>
</ReportPinData>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_xst.xrpt
View file @ 777894d8
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3">
<document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Fri Jan 28 11:47:26 2011">
<application stringID="Xst" timeStamp="Fri Jan 28 15:04:51 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="6">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item>
<item stringID="User_EnvHost" value="bqplv2"/>
<item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
</row>
</table>
</section>
......
trunk/firmware/XilinxISE/SystemFpga/SystemFpga.gise
View file @ 777894d8
......@@ -111,7 +111,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1296211673" xil_pn:in_ck="-394197636941444327" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1296211644">
<transform xil_pn:end_ts="1296223509" xil_pn:in_ck="-394197636941444327" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1296223489">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -133,7 +133,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1296211680" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1296211673">
<transform xil_pn:end_ts="1296223514" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1296223509">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -143,10 +143,12 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1296211741" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1296211680">
<transform xil_pn:end_ts="1296223548" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1296223514">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="SFpga.pcf"/>
<outfile xil_pn:name="SFpga_map.map"/>
<outfile xil_pn:name="SFpga_map.mrp"/>
......@@ -157,7 +159,7 @@
<outfile xil_pn:name="SFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1296212125" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1296211741">
<transform xil_pn:end_ts="1296223725" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1296223548">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -172,7 +174,7 @@
<outfile xil_pn:name="SFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1296212185" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-774614059244361160" xil_pn:start_ts="1296212125">
<transform xil_pn:end_ts="1296223769" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-774614059244361160" xil_pn:start_ts="1296223725">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -188,13 +190,9 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1294318860" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1294318858">
<transform xil_pn:end_ts="1296223783" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1296223781">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="sfpga.isc"/>
</transform>
<transform xil_pn:end_ts="1294819273" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1294819271">
......@@ -219,7 +217,7 @@
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1296212125" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1296212103">
<transform xil_pn:end_ts="1296223725" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1296223714">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="SFpga.twr"/>
......
trunk/firmware/XilinxISE/SystemFpga/_ngo/netlist.lst
View file @ 777894d8
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1296211672
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1296223508
OK
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/pn_parser.xmsgs
View file @ 777894d8
......@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/VmeToWishBone.v\&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/InterruptManagerWB.v\&quot; into library work</arg>
</msg>
</messages>
......
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport
View file @ 777894d8
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2011-01-28T11:09:00</DateModified>
<DateModified>2011-01-28T15:02:31</DateModified>
<ModuleName>SFpga</ModuleName>
<SummaryTimeStamp>2010-12-20T13:49:08</SummaryTimeStamp>
<SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath>
......
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SystemFpga.projectmgr
View file @ 777894d8
......@@ -36,12 +36,14 @@
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems/>
<SelectedItems>
<SelectedItem>VmeToWishBone.v</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000001a2000000040101000100000000000000000000000064ffffffff000000810000000000000004000000ac00000001000000000000002400000001000000000000006600000001000000000000006c0000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000019a000000040101000100000000000000000000000064ffffffff000000810000000000000004000000ac0000000100000000000000240000000100000000000000660000000100000000000000640000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>AddrDecoderWBSys.v</CurrentItem>
<CurrentItem>VmeToWishBone.v</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
......@@ -50,7 +52,7 @@
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000001a2000000010001000100000000000000000000000064ffffffff000000810000000000000001000001a20000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
......@@ -64,13 +66,13 @@
<ClosedNode>Implement Design/Translate</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Design Summary/Reports</SelectedItem>
<SelectedItem>Configure Target Device</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >20</ScrollbarPosition>
<ScrollbarPosition orientation="vertical" >22</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000191000000010000000100000000000000000000000064ffffffff000000810000000000000001000001910000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000189000000010000000100000000000000000000000064ffffffff000000810000000000000001000001890000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Design Summary/Reports</CurrentItem>
<CurrentItem>Configure Target Device</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes>
......
trunk/firmware/XilinxISE/SystemFpga/par_usage_statistics.html
View file @ 777894d8
......@@ -2,30 +2,30 @@
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1355</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4356</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4356</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4360</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4360</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>127</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>23.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>29.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>339.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>351.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>354.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>354.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>354.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>354.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>354.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>354.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>11.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>14.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>153.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>158.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>160.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>160.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>160.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>160.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>160.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>160.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>14.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>11.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>5.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>22.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>14.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>10.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>6.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>4.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>22.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>14.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>11.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>7.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0615</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0635</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
trunk/firmware/XilinxISE/SystemFpga/sfpga.bgn
View file @ 777894d8
Release 12.3 - Bitgen M.70d (nt)
Release 12.3 - Bitgen M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx150t.nph' in environment
C:\Xilinx\12.3\ISE_DS\ISE\.
"SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
Opened constraints file SFpga.pcf.
Fri Jan 28 11:55:36 2011
Fri Jan 28 15:08:51 2011
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:yes -b -g IEEE1532:Yes -g CRC:Enable -g Reset_on_err:No -g ConfigRate:26 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:yes -b -g IEEE1532:Yes -g CRC:Enable -g Reset_on_err:No -g ConfigRate:26 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd
WARNING:Bitgen:244 - A StartupClk setting other than JtagClk is being used to
generate a bitstream in IEEE1532 format. The IEEE1532 option implies that
......
trunk/firmware/XilinxISE/SystemFpga/sfpga.drc
View file @ 777894d8
Release 12.3 Drc M.70d (nt)
Release 12.3 Drc M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Jan 28 11:55:36 2011
Fri Jan 28 15:08:51 2011
drc -z SFpga.ncd SFpga.pcf
......
trunk/firmware/XilinxISE/SystemFpga/sfpga.isc
View file @ 777894d8
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/sfpga.rbt
View file @ 777894d8
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html
View file @ 777894d8
......@@ -11,13 +11,13 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>OS Platform:</B></TD>
<TD><xtag-property name="OSPlatform">NT</xtag-property></TD>
<TD><xtag-property name="OSPlatform">NT64</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD><xtag-property name="TargetDevice">xc6slx150t</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">d36a4175861f4f48ac5a6ada421762f9</xtag-property>.<xtag-property name="ProjectID">F6031676C5FE434A8E9F8A1057A8E48F</xtag-property>.<xtag-property name="ProjectIteration">28</xtag-property></TD>
<TD><xtag-property name="RandomID">effa8437e76f45ca9db699794ac1987e</xtag-property>.<xtag-property name="ProjectID">F6031676C5FE434A8E9F8A1057A8E48F</xtag-property>.<xtag-property name="ProjectIteration">29</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">fgg676</xtag-property></TD>
</TR>
......@@ -29,7 +29,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2011-01-28T11:56:19</xtag-property></TD>
<TD><xtag-property name="Date Generated">2011-01-28T15:09:13</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD>
</TR>
......@@ -39,27 +39,27 @@
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>User Environment</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft Windows XP Professional</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft </xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>Service Pack 3 (build 2600)</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>major release (build 7600)</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value> Intel(R) Pentium(R) D CPU 3.40GHz</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3389 MHz</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3158 MHz</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft Windows XP Professional</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft </xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>Service Pack 3 (build 2600)</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>major release (build 7600)</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value> Intel(R) Pentium(R) D CPU 3.40GHz</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3389 MHz</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3158 MHz</xtag-env-param-value></xtag-property></TD>
</TR>
</xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
......@@ -134,14 +134,14 @@
<LI><xtag-item1>AGG_BONDED_IO=331</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=331</xtag-item1></LI>
<LI><xtag-item1>AGG_LOCED_IO=329</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=392</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=386</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=327</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOBM=2</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOBS=2</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=479</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=372</xtag-item1></LI>
<LI><xtag-item1>NUM_BSREGONLY=209</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=1060</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=493</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=356</xtag-item1></LI>
<LI><xtag-item1>NUM_BSREGONLY=197</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=1046</xtag-item1></LI>
<LI><xtag-item1>NUM_BUFG=3</xtag-item1></LI>
<LI><xtag-item1>NUM_DPRAM_O5ANDO6=4</xtag-item1></LI>
<LI><xtag-item1>NUM_DPRAM_O6ONLY=4</xtag-item1></LI>
......@@ -152,20 +152,20 @@
<LI><xtag-item1>NUM_LOGIC_O5ONLY=83</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=616</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=5</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=9</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO5=9</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=7</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO5=7</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO6=5</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O5=7</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O5=6</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O6=83</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=51</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEM=4</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=337</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=331</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=29</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CONTROLSET=27</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=1078</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=1075</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_F7MUX=22</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=765</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=166</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=159</xtag-item1></LI>
<LI><xtag-item1>NUM_SRL_O5ANDO6=2</xtag-item1></LI>
<LI><xtag-item1>NUM_SRL_O6ONLY=4</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=71</xtag-item1></LI>
......@@ -178,39 +178,39 @@
<LI><xtag-item1>NumNets_Active=1735</xtag-item1></LI>
<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI>
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=10</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=200</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=12</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=211</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=3</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=20</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=226</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=20</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=253</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=2317</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=21</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=227</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=21</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=256</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=2187</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=354</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=185</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=180</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=33</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=242</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=242</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=3401</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=1440</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=1281</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=3398</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=1442</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=1292</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=135</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=115</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=697</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=729</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=3910</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=5368</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=308</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=2239</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=5288</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=311</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=2284</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_GENERIC=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=102</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=101</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBIN2OUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBOUTPUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_KVCCOUT=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=238</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=237</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PADINPUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINBOUNCE=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=251</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=250</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name>
......@@ -218,9 +218,9 @@
<LI><xtag-item1>BUFG-BUFGMUX=3</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBM=162</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBS=165</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=24</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=87</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=77</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=14</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=78</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=81</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
......@@ -232,7 +232,7 @@
<LI><xtag-item2>BUFG=3</xtag-item2></LI>
<LI><xtag-item2>BUFG_BUFG=3</xtag-item2></LI>
<LI><xtag-item2>CARRY4=29</xtag-item2></LI>
<LI><xtag-item2>FF_SR=87</xtag-item2></LI>
<LI><xtag-item2>FF_SR=85</xtag-item2></LI>
<LI><xtag-item2>HARD0=5</xtag-item2></LI>
<LI><xtag-item2>HARD1=2</xtag-item2></LI>
<LI><xtag-item2>IOB=327</xtag-item2></LI>
......@@ -242,17 +242,17 @@
<LI><xtag-item2>IOB_IMUX=160</xtag-item2></LI>
<LI><xtag-item2>IOB_INBUF=160</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=198</xtag-item2></LI>
<LI><xtag-item2>LUT5=223</xtag-item2></LI>
<LI><xtag-item2>LUT5=220</xtag-item2></LI>
<LI><xtag-item2>LUT6=828</xtag-item2></LI>
<LI><xtag-item2>LUT_OR_MEM5=6</xtag-item2></LI>
<LI><xtag-item2>LUT_OR_MEM6=14</xtag-item2></LI>
<LI><xtag-item2>NULLMUX=3</xtag-item2></LI>
<LI><xtag-item2>PAD=331</xtag-item2></LI>
<LI><xtag-item2>REG_SR=678</xtag-item2></LI>
<LI><xtag-item2>REG_SR=680</xtag-item2></LI>
<LI><xtag-item2>SELMUX2_1=22</xtag-item2></LI>
<LI><xtag-item2>SLICEL=51</xtag-item2></LI>
<LI><xtag-item2>SLICEM=4</xtag-item2></LI>
<LI><xtag-item2>SLICEX=337</xtag-item2></LI>
<LI><xtag-item2>SLICEX=331</xtag-item2></LI>
</UL>
</xtag-group>
</TD>
......@@ -264,9 +264,9 @@
<TD>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:87] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:76] [SRINIT1:11]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:49] [SYNC:38]</xtag-item3></LI>
<LI><xtag-item3>CK=[CK:85] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:74] [SRINIT1:11]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:49] [SYNC:36]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="IOBM_OUTBUF">IOBM_OUTBUF</xtag-group-name>
......@@ -306,17 +306,17 @@
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item3>CK=[CK:678] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:678]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:651] [SRINIT1:27]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:222] [SYNC:456]</xtag-item3></LI>
<LI><xtag-item3>CK=[CK:680] [CK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>LATCH_OR_FF=[FF:680]</xtag-item3></LI>
<LI><xtag-item3>SRINIT=[SRINIT0:653] [SRINIT1:27]</xtag-item3></LI>
<LI><xtag-item3>SYNC_ATTR=[ASYNC:222] [SYNC:458]</xtag-item3></LI>
</UL>
</TD>
<TD>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:25] [CLK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CLK=[CLK:24] [CLK_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name>
......@@ -326,7 +326,7 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:197] [CLK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CLK=[CLK:199] [CLK_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
</TD>
......@@ -371,11 +371,11 @@
</xtag-group>
<xtag-group><xtag-group-name name="FF_SR">FF_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CE=41</xtag-item1></LI>
<LI><xtag-item1>CK=87</xtag-item1></LI>
<LI><xtag-item1>D=87</xtag-item1></LI>
<LI><xtag-item1>Q=87</xtag-item1></LI>
<LI><xtag-item1>SR=38</xtag-item1></LI>
<LI><xtag-item1>CE=40</xtag-item1></LI>
<LI><xtag-item1>CK=85</xtag-item1></LI>
<LI><xtag-item1>D=85</xtag-item1></LI>
<LI><xtag-item1>Q=85</xtag-item1></LI>
<LI><xtag-item1>SR=36</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="HARD0">HARD0</xtag-group-name>
......@@ -440,18 +440,18 @@
</xtag-group>
<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name>
<UL>
<LI><xtag-item1>A1=26</xtag-item1></LI>
<LI><xtag-item1>A1=25</xtag-item1></LI>
<LI><xtag-item1>A2=27</xtag-item1></LI>
<LI><xtag-item1>A3=96</xtag-item1></LI>
<LI><xtag-item1>A4=102</xtag-item1></LI>
<LI><xtag-item1>A5=56</xtag-item1></LI>
<LI><xtag-item1>O5=223</xtag-item1></LI>
<LI><xtag-item1>A5=54</xtag-item1></LI>
<LI><xtag-item1>O5=220</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name>
<UL>
<LI><xtag-item1>A1=281</xtag-item1></LI>
<LI><xtag-item1>A2=405</xtag-item1></LI>
<LI><xtag-item1>A2=404</xtag-item1></LI>
<LI><xtag-item1>A3=497</xtag-item1></LI>
<LI><xtag-item1>A4=716</xtag-item1></LI>
<LI><xtag-item1>A5=745</xtag-item1></LI>
......@@ -513,11 +513,11 @@
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
<UL>
<LI><xtag-item1>CE=375</xtag-item1></LI>
<LI><xtag-item1>CK=678</xtag-item1></LI>
<LI><xtag-item1>D=678</xtag-item1></LI>
<LI><xtag-item1>Q=678</xtag-item1></LI>
<LI><xtag-item1>SR=457</xtag-item1></LI>
<LI><xtag-item1>CE=376</xtag-item1></LI>
<LI><xtag-item1>CK=680</xtag-item1></LI>
<LI><xtag-item1>D=680</xtag-item1></LI>
<LI><xtag-item1>Q=680</xtag-item1></LI>
<LI><xtag-item1>SR=459</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SELMUX2_1">SELMUX2_1</xtag-group-name>
......@@ -530,39 +530,39 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item1>A=11</xtag-item1></LI>
<LI><xtag-item1>A1=7</xtag-item1></LI>
<LI><xtag-item1>A2=12</xtag-item1></LI>
<LI><xtag-item1>A3=16</xtag-item1></LI>
<LI><xtag-item1>A4=32</xtag-item1></LI>
<LI><xtag-item1>A5=25</xtag-item1></LI>
<LI><xtag-item1>A6=41</xtag-item1></LI>
<LI><xtag-item1>AMUX=10</xtag-item1></LI>
<LI><xtag-item1>A=5</xtag-item1></LI>
<LI><xtag-item1>A1=4</xtag-item1></LI>
<LI><xtag-item1>A2=7</xtag-item1></LI>
<LI><xtag-item1>A3=10</xtag-item1></LI>
<LI><xtag-item1>A4=26</xtag-item1></LI>
<LI><xtag-item1>A5=19</xtag-item1></LI>
<LI><xtag-item1>A6=35</xtag-item1></LI>
<LI><xtag-item1>AMUX=9</xtag-item1></LI>
<LI><xtag-item1>AQ=23</xtag-item1></LI>
<LI><xtag-item1>AX=7</xtag-item1></LI>
<LI><xtag-item1>B=8</xtag-item1></LI>
<LI><xtag-item1>B=6</xtag-item1></LI>
<LI><xtag-item1>B1=6</xtag-item1></LI>
<LI><xtag-item1>B2=9</xtag-item1></LI>
<LI><xtag-item1>B3=12</xtag-item1></LI>
<LI><xtag-item1>B4=31</xtag-item1></LI>
<LI><xtag-item1>B5=22</xtag-item1></LI>
<LI><xtag-item1>B6=38</xtag-item1></LI>
<LI><xtag-item1>BMUX=12</xtag-item1></LI>
<LI><xtag-item1>B2=8</xtag-item1></LI>
<LI><xtag-item1>B3=11</xtag-item1></LI>
<LI><xtag-item1>B4=29</xtag-item1></LI>
<LI><xtag-item1>B5=20</xtag-item1></LI>
<LI><xtag-item1>B6=36</xtag-item1></LI>
<LI><xtag-item1>BMUX=11</xtag-item1></LI>
<LI><xtag-item1>BQ=23</xtag-item1></LI>
<LI><xtag-item1>BX=6</xtag-item1></LI>
<LI><xtag-item1>C1=10</xtag-item1></LI>
<LI><xtag-item1>C2=14</xtag-item1></LI>
<LI><xtag-item1>C1=9</xtag-item1></LI>
<LI><xtag-item1>C2=13</xtag-item1></LI>
<LI><xtag-item1>C3=25</xtag-item1></LI>
<LI><xtag-item1>C4=41</xtag-item1></LI>
<LI><xtag-item1>C5=34</xtag-item1></LI>
<LI><xtag-item1>C6=49</xtag-item1></LI>
<LI><xtag-item1>CE=10</xtag-item1></LI>
<LI><xtag-item1>CE=11</xtag-item1></LI>
<LI><xtag-item1>CIN=21</xtag-item1></LI>
<LI><xtag-item1>CLK=25</xtag-item1></LI>
<LI><xtag-item1>CLK=24</xtag-item1></LI>
<LI><xtag-item1>CMUX=29</xtag-item1></LI>
<LI><xtag-item1>COUT=21</xtag-item1></LI>
<LI><xtag-item1>CQ=23</xtag-item1></LI>
<LI><xtag-item1>CX=25</xtag-item1></LI>
<LI><xtag-item1>CX=26</xtag-item1></LI>
<LI><xtag-item1>D=2</xtag-item1></LI>
<LI><xtag-item1>D1=13</xtag-item1></LI>
<LI><xtag-item1>D2=25</xtag-item1></LI>
......@@ -573,7 +573,7 @@
<LI><xtag-item1>DMUX=7</xtag-item1></LI>
<LI><xtag-item1>DQ=21</xtag-item1></LI>
<LI><xtag-item1>DX=6</xtag-item1></LI>
<LI><xtag-item1>SR=16</xtag-item1></LI>
<LI><xtag-item1>SR=17</xtag-item1></LI>
</UL>
</TD>
<TD>
......@@ -629,49 +629,49 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item1>A=144</xtag-item1></LI>
<LI><xtag-item1>A1=99</xtag-item1></LI>
<LI><xtag-item1>A2=135</xtag-item1></LI>
<LI><xtag-item1>A3=175</xtag-item1></LI>
<LI><xtag-item1>A4=193</xtag-item1></LI>
<LI><xtag-item1>A5=211</xtag-item1></LI>
<LI><xtag-item1>A6=216</xtag-item1></LI>
<LI><xtag-item1>AMUX=38</xtag-item1></LI>
<LI><xtag-item1>AQ=149</xtag-item1></LI>
<LI><xtag-item1>AX=73</xtag-item1></LI>
<LI><xtag-item1>B=56</xtag-item1></LI>
<LI><xtag-item1>B1=55</xtag-item1></LI>
<LI><xtag-item1>B2=76</xtag-item1></LI>
<LI><xtag-item1>B3=108</xtag-item1></LI>
<LI><xtag-item1>B4=128</xtag-item1></LI>
<LI><xtag-item1>B5=146</xtag-item1></LI>
<LI><xtag-item1>B6=144</xtag-item1></LI>
<LI><xtag-item1>BMUX=29</xtag-item1></LI>
<LI><xtag-item1>BQ=154</xtag-item1></LI>
<LI><xtag-item1>BX=66</xtag-item1></LI>
<LI><xtag-item1>C=60</xtag-item1></LI>
<LI><xtag-item1>C1=55</xtag-item1></LI>
<LI><xtag-item1>C2=70</xtag-item1></LI>
<LI><xtag-item1>C3=93</xtag-item1></LI>
<LI><xtag-item1>C4=111</xtag-item1></LI>
<LI><xtag-item1>C5=126</xtag-item1></LI>
<LI><xtag-item1>C6=126</xtag-item1></LI>
<LI><xtag-item1>A=139</xtag-item1></LI>
<LI><xtag-item1>A1=90</xtag-item1></LI>
<LI><xtag-item1>A2=131</xtag-item1></LI>
<LI><xtag-item1>A3=170</xtag-item1></LI>
<LI><xtag-item1>A4=191</xtag-item1></LI>
<LI><xtag-item1>A5=205</xtag-item1></LI>
<LI><xtag-item1>A6=212</xtag-item1></LI>
<LI><xtag-item1>AMUX=36</xtag-item1></LI>
<LI><xtag-item1>AQ=154</xtag-item1></LI>
<LI><xtag-item1>AX=78</xtag-item1></LI>
<LI><xtag-item1>B=55</xtag-item1></LI>
<LI><xtag-item1>B1=52</xtag-item1></LI>
<LI><xtag-item1>B2=72</xtag-item1></LI>
<LI><xtag-item1>B3=103</xtag-item1></LI>
<LI><xtag-item1>B4=124</xtag-item1></LI>
<LI><xtag-item1>B5=143</xtag-item1></LI>
<LI><xtag-item1>B6=142</xtag-item1></LI>
<LI><xtag-item1>BMUX=25</xtag-item1></LI>
<LI><xtag-item1>BQ=152</xtag-item1></LI>
<LI><xtag-item1>BX=65</xtag-item1></LI>
<LI><xtag-item1>C=62</xtag-item1></LI>
<LI><xtag-item1>C1=63</xtag-item1></LI>
<LI><xtag-item1>C2=75</xtag-item1></LI>
<LI><xtag-item1>C3=98</xtag-item1></LI>
<LI><xtag-item1>C4=117</xtag-item1></LI>
<LI><xtag-item1>C5=130</xtag-item1></LI>
<LI><xtag-item1>C6=128</xtag-item1></LI>
<LI><xtag-item1>CE=93</xtag-item1></LI>
<LI><xtag-item1>CLK=197</xtag-item1></LI>
<LI><xtag-item1>CMUX=23</xtag-item1></LI>
<LI><xtag-item1>CQ=129</xtag-item1></LI>
<LI><xtag-item1>CLK=199</xtag-item1></LI>
<LI><xtag-item1>CMUX=22</xtag-item1></LI>
<LI><xtag-item1>CQ=131</xtag-item1></LI>
<LI><xtag-item1>CX=63</xtag-item1></LI>
<LI><xtag-item1>D=73</xtag-item1></LI>
<LI><xtag-item1>D1=61</xtag-item1></LI>
<LI><xtag-item1>D2=84</xtag-item1></LI>
<LI><xtag-item1>D3=114</xtag-item1></LI>
<LI><xtag-item1>D4=138</xtag-item1></LI>
<LI><xtag-item1>D5=158</xtag-item1></LI>
<LI><xtag-item1>D6=160</xtag-item1></LI>
<LI><xtag-item1>DMUX=26</xtag-item1></LI>
<LI><xtag-item1>DQ=150</xtag-item1></LI>
<LI><xtag-item1>DX=62</xtag-item1></LI>
<LI><xtag-item1>SR=132</xtag-item1></LI>
<LI><xtag-item1>D=85</xtag-item1></LI>
<LI><xtag-item1>D1=68</xtag-item1></LI>
<LI><xtag-item1>D2=93</xtag-item1></LI>
<LI><xtag-item1>D3=126</xtag-item1></LI>
<LI><xtag-item1>D4=146</xtag-item1></LI>
<LI><xtag-item1>D5=169</xtag-item1></LI>
<LI><xtag-item1>D6=172</xtag-item1></LI>
<LI><xtag-item1>DMUX=33</xtag-item1></LI>
<LI><xtag-item1>DQ=147</xtag-item1></LI>
<LI><xtag-item1>DX=60</xtag-item1></LI>
<LI><xtag-item1>SR=133</xtag-item1></LI>
</UL>
</TD>
<TD>
......@@ -894,13 +894,19 @@
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
</xtag-section></UL></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR>
<tr>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>10</xtag-total-run-started></td>
<td><xtag-total-run-finished>10</xtag-total-run-finished></td>
<td><xtag-program-name>_impact</xtag-program-name></td>
<td><xtag-total-run-started>41</xtag-total-run-started></td>
<td><xtag-total-run-finished>29</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -908,19 +914,9 @@
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>edif2ngd</xtag-program-name></td>
<td><xtag-total-run-started>5</xtag-total-run-started></td>
<td><xtag-total-run-finished>5</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>ibiswriter</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>37</xtag-total-run-started></td>
<td><xtag-total-run-finished>37</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -929,8 +925,8 @@
</tr>
<tr>
<td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>25</xtag-total-run-started></td>
<td><xtag-total-run-finished>15</xtag-total-run-finished></td>
<td><xtag-total-run-started>36</xtag-total-run-started></td>
<td><xtag-total-run-finished>36</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -939,8 +935,8 @@
</tr>
<tr>
<td><xtag-program-name>ngc2edif</xtag-program-name></td>
<td><xtag-total-run-started>14</xtag-total-run-started></td>
<td><xtag-total-run-finished>14</xtag-total-run-finished></td>
<td><xtag-total-run-started>5</xtag-total-run-started></td>
<td><xtag-total-run-finished>5</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -949,8 +945,8 @@
</tr>
<tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
<td><xtag-total-run-started>31</xtag-total-run-started></td>
<td><xtag-total-run-finished>31</xtag-total-run-finished></td>
<td><xtag-total-run-started>37</xtag-total-run-started></td>
<td><xtag-total-run-finished>37</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -959,8 +955,8 @@
</tr>
<tr>
<td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>15</xtag-total-run-started></td>
<td><xtag-total-run-finished>15</xtag-total-run-finished></td>
<td><xtag-total-run-started>36</xtag-total-run-started></td>
<td><xtag-total-run-finished>36</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -969,8 +965,8 @@
</tr>
<tr>
<td><xtag-program-name>trce</xtag-program-name></td>
<td><xtag-total-run-started>16</xtag-total-run-started></td>
<td><xtag-total-run-finished>16</xtag-total-run-finished></td>
<td><xtag-total-run-started>36</xtag-total-run-started></td>
<td><xtag-total-run-finished>36</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -979,8 +975,8 @@
</tr>
<tr>
<td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>39</xtag-total-run-started></td>
<td><xtag-total-run-finished>39</xtag-total-run-finished></td>
<td><xtag-total-run-started>38</xtag-total-run-started></td>
<td><xtag-total-run-finished>38</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -988,35 +984,7 @@
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
</xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ISEHelpViewerData">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=2><B>Help Statistics</B></TD></TR>
<TR ALIGN=LEFT><TD COLSPAN=2><xtag-group><B><xtag-group-name name="SearchFoundList">
Search words with results</xtag-group-name></B></TD></TR>
<TR><TD><xtag-search-item>input standard </xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>lvds </xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>verilog </xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR></xtag-group><TR VALIGN=TOP><TD COLSPAN=2><xtag-group><B><xtag-group-name name="OpenedHelpFiles">
Help files</xtag-group-name></B></TD></TR>
<TR><TD><xtag-search-item>/doc/usenglish/isehelp/cgn_c_df_verilog_flow.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/cgn_c_df_verilog_instantiation_example.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/cgn_p_add_ip_com_flow.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/dsm_c_design_summary_overview.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/gls_r_glossary.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/ise_c_constraints_entry_methods.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/ise_c_pin_assignment_pace.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/ism_r_verlang_expressions.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/pn_db_npw_project_summary.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/pp_db_hdl_options_syn.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/pp_p_process_io_pin_planning_pre_syn.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/sse_p_adding_attr.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR></xtag-group></xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="Project Statistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=2><B>Project Statistics</B></TD></TR>
......@@ -1040,7 +1008,7 @@ Help files</xtag-group-name></B></TD></TR>
<TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2010-12-15T15:02:16</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>F6031676C5FE434A8E9F8A1057A8E48F</xtag-design-property-value></TD>
<TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>28</xtag-process-property-value></TD>
<TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>29</xtag-process-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD>
......
trunk/firmware/XilinxISE/SystemFpga/webtalk.log
View file @ 777894d8
......@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
ProjectID=F6031676C5FE434A8E9F8A1057A8E48F
ProjectIteration=28
ProjectIteration=29
WebTalk Summary
----------------
......@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2011-01-28T11:56:25. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2011-01-28T15:09:29. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
trunk/firmware/XilinxISE/SystemFpga/webtalk_pn.xml
View file @ 777894d8
......@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Fri Jan 28 11:55:26 2011">
<application name="pn" timeStamp="Fri Jan 28 15:08:46 2011">
<section name="Project Information" visible="false">
<property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/>
<property name="ProjectIteration" value="28" type="project"/>
<property name="ProjectIteration" value="29" type="project"/>
<property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/>
</section>
......@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/>
<property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/>
<property name="PROP_intWbtProjectIteration" value="28" type="process"/>
<property name="PROP_intWbtProjectIteration" value="29" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
......
trunk/hdl/design/InterruptManagerWB.v
View file @ 777894d8
......@@ -157,8 +157,8 @@ wire [7:0] fpga_revision;
wire [15:0] date;
assign fpga_version = 8'h00;
assign fpga_revision = 8'h01;
assign date = {8'd6, 4'd10,4'd10};
assign fpga_revision = 8'h02;
assign date = {8'd27, 4'd1,4'd11};
assign Ack_oa = Stb_i&&Cyc_i;
......
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