Commit 936d57a5 authored by Andrea Boccardi's avatar Andrea Boccardi

Added ApplicationFpga Xilinx project

parent 6ee3e428
Release 12.3 ngdbuild M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3
ApplicationFpga.ngc ApplicationFpga.ngd
Reading NGO file
"C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.ngc" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "ApplicationFpga.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking expanded design ...
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<3>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<2>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgClk_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgCsi_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgRdWr_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgInit_io' has no legal driver
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 11
Total memory usage is 83940 kilobytes
Writing NGD file "ApplicationFpga.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "ApplicationFpga.bld"...
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd ApplicationFpga.pcf
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
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Release 12.3 par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
BQPLV2:: Mon Dec 20 10:59:47 2010
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd
ApplicationFpga.ncd ApplicationFpga.pcf
Constraints file: ApplicationFpga.pcf.
Loading device for application Rf_Device from file '6slx150t.nph' in environment C:\Xilinx\12.3\ISE_DS\ISE\.
"ApplicationFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.12c 2010-09-15".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 330 out of 184,304 1%
Number used as Flip Flops: 330
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 257 out of 92,152 1%
Number used as logic: 233 out of 92,152 1%
Number using O6 output only: 217
Number using O5 output only: 14
Number using O5 and O6: 2
Number used as ROM: 0
Number used as Memory: 5 out of 21,680 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 5
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 19
Number with same-slice register load: 18
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 108 out of 23,038 1%
Number of LUT Flip Flop pairs used: 355
Number with an unused Flip Flop: 44 out of 355 12%
Number with an unused LUT: 98 out of 355 27%
Number of fully used LUT-FF pairs: 213 out of 355 60%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 23 out of 396 5%
Number of LOCed IOBs: 23 out of 23 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 268 0%
Number of RAMB8BWERs: 0 out of 536 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 1 out of 16 6%
Number used as BUFGs: 1
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 0 out of 586 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
Number of OLOGIC2/OSERDES2s: 0 out of 586 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 180 0%
Number of GTPA1_DUALs: 0 out of 4 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 6 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 20 secs
Finished initial Timing Analysis. REAL time: 20 secs
WARNING:Par:288 - The signal AFpgaProgClk_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgRdWr_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<6>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgCsi_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgInit_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgM_iob2<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgM_iob2<1>_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 1668 unrouted; REAL time: 23 secs
Phase 2 : 1536 unrouted; REAL time: 29 secs
Phase 3 : 731 unrouted; REAL time: 32 secs
Phase 4 : 731 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 43 secs
Updating file: ApplicationFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs
Total REAL time to Router completion: 45 secs
Total CPU time to Router completion: 45 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|FpGpIo_iob4_2_OBUF_B | | | | | |
| UFG | BUFGMUX_X2Y1| No | 85 | 0.144 | 1.648 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 1.090ns| 7.243ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.264ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 11 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 48 secs
Total CPU time to PAR completion: 48 secs
Peak Memory Usage: 353 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 13
Number of info messages: 0
Writing design to file ApplicationFpga.ncd
PAR done!
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verilog work "../../../hdl/design/Ser2MstWB.v"
verilog work "../../../hdl/design/Generic4OutputRegs.v"
verilog work "../../../hdl/design/Debouncer.v"
verilog work "../../../hdl/design/AddrDecoderWBApp.v"
verilog work "../../../hdl/design/ApplicationFpga.v"
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#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/20
NET "SysAppClk_ik" TNM_NET = "SysAppClk_ik";
TIMESPEC TS_SysAppClk_ik = PERIOD "SysAppClk_ik" 120 MHz HIGH 50 %;
# PlanAhead Generated physical constraints
NET "AFpgaProgClk_io" LOC = AE24;
NET "AFpgaProgCsi_io" LOC = AF23;
NET "AFpgaProgD_iob8[0]" LOC = AD23;
NET "AFpgaProgD_iob8[1]" LOC = V18;
NET "AFpgaProgD_iob8[2]" LOC = W19;
NET "AFpgaProgD_iob8[3]" LOC = AD6;
NET "AFpgaProgD_iob8[4]" LOC = AF6;
NET "AFpgaProgD_iob8[5]" LOC = W8;
NET "AFpgaProgD_iob8[6]" LOC = W7;
NET "AFpgaProgD_iob8[7]" LOC = AA10;
NET "AFpgaProgInit_io" LOC = AE3;
NET "AFpgaProgM_iob2[0]" LOC = AF24;
NET "AFpgaProgM_iob2[1]" LOC = AD22;
NET "AFpgaProgRdWr_io" LOC = AB11;
NET "FpGpIo_iob4[1]" LOC = G3;
NET "FpGpIo_iob4[2]" LOC = G4;
NET "FpGpIo_iob4[3]" LOC = F1;
NET "FpGpIo_iob4[4]" LOC = F3;
NET "PushButton_ion" LOC = H20;
NET "SysAppClk_ik" LOC = U23;
NET "SysAppClk_ok" LOC = U24;
NET "SysAppSlow_iob2[1]" LOC = AF22;
NET "SysAppSlow_iob2[2]" LOC = AF3;
Release 12.3 - par M.70d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 11:00:36 2010
All signals are completely routed.
WARNING:ParHelpers:361 - There are 11 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
AFpgaProgClk_io_IBUF
AFpgaProgCsi_io_IBUF
AFpgaProgD_iob8<0>_IBUF
AFpgaProgD_iob8<1>_IBUF
AFpgaProgD_iob8<2>_IBUF
AFpgaProgD_iob8<3>_IBUF
AFpgaProgD_iob8<6>_IBUF
AFpgaProgInit_io_IBUF
AFpgaProgM_iob2<0>_IBUF
AFpgaProgM_iob2<1>_IBUF
AFpgaProgRdWr_io_IBUF
-w
-g DebugBitstream:No
-g Binary:yes
-b
-g IEEE1532:Yes
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:2
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g ExtMasterCclk_en:No
-g SPI_buswidth:1
-g TIMER_CFG:0xFFFF
-g multipin_wakeup:No
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g Encrypt:No
-g en_sw_gsr:No
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4
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PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=YES
set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn ApplicationFpga.prj
-ifmt mixed
-ofn ApplicationFpga
-ofmt NGC
-p xc6slx150t-3-fgg676
-top ApplicationFpga
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
INTSTYLE=ise
INFILE=C:\VFC_SVN\firmware\XilinxISE\ApplicationFpga\ApplicationFpga.ncd
OUTFILE=C:\VFC_SVN\firmware\XilinxISE\ApplicationFpga\ApplicationFpga.bit
FAMILY=Spartan6
PART=xc6slx150t-3fgg676
WORKINGDIR=C:\VFC_SVN\firmware\XilinxISE\ApplicationFpga
LICENSE=ISE
USER_INFO=174122088_179509804_641
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Release 12.3 Map M.70d (nt)
Xilinx Map Application Log File for Design 'ApplicationFpga'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr
off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd
ApplicationFpga.pcf
Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Mon Dec 20 10:58:56 2010
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 26 secs
Total CPU time at the beginning of Placer: 22 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:22fc166f) REAL time: 34 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:22fc166f) REAL time: 34 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:22fc166f) REAL time: 34 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:92c41d7) REAL time: 41 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:92c41d7) REAL time: 41 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:92c41d7) REAL time: 41 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:92c41d7) REAL time: 42 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:92c41d7) REAL time: 42 secs
Phase 9.8 Global Placement
........................
.....
Phase 9.8 Global Placement (Checksum:3716193a) REAL time: 44 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:3716193a) REAL time: 44 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:5ae609a5) REAL time: 44 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:5ae609a5) REAL time: 44 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:d17f7f67) REAL time: 44 secs
Total REAL time to Placer completion: 47 secs
Total CPU time to Placer completion: 42 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal <AFpgaProgClk_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<2>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<3>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 11
Slice Logic Utilization:
Number of Slice Registers: 330 out of 184,304 1%
Number used as Flip Flops: 330
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 257 out of 92,152 1%
Number used as logic: 233 out of 92,152 1%
Number using O6 output only: 217
Number using O5 output only: 14
Number using O5 and O6: 2
Number used as ROM: 0
Number used as Memory: 5 out of 21,680 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 5
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 19
Number with same-slice register load: 18
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 108 out of 23,038 1%
Number of LUT Flip Flop pairs used: 355
Number with an unused Flip Flop: 44 out of 355 12%
Number with an unused LUT: 98 out of 355 27%
Number of fully used LUT-FF pairs: 213 out of 355 60%
Number of unique control sets: 10
Number of slice register sites lost
to control set restrictions: 25 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 23 out of 396 5%
Number of LOCed IOBs: 23 out of 23 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 268 0%
Number of RAMB8BWERs: 0 out of 536 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 1 out of 16 6%
Number used as BUFGs: 1
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 0 out of 586 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
Number of OLOGIC2/OSERDES2s: 0 out of 586 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 180 0%
Number of GTPA1_DUALs: 0 out of 4 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 6 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.47
Peak Memory Usage: 380 MB
Total REAL time to MAP completion: 49 secs
Total CPU time to MAP completion: 43 secs
Mapping completed.
See MAP report file "ApplicationFpga_map.mrp" for details.
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Mon Dec 20 10:58:52 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="6">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>