Commit b46b223e authored by Andrea Boccardi's avatar Andrea Boccardi

updates in the fw

parent 0fd775fd
`timescale 1ns/1ns
module MAX5483 (
input SPIUD_iq,
input CS_iqn,
input SclkInc_iqk,
input DinUD_iq);
parameter dly = 1;
initial begin
ParallelData_q = 24'b0;
Latch10Bits_m = 10'b0;
NVRegister_m = 10'b0;
Latch10BitsSPI_m = 10'b0;
NVRegisterSPI_m = 10'b0;
Latch10BitsUD_m = 10'b0;
NVRegisterUD_m = 10'b0;
end
reg [23:0] ParallelData_q;
reg [9:0] Latch10Bits_m, Latch10BitsSPI_m, Latch10BitsUD_m;
reg [9:0] NVRegister_m, NVRegisterSPI_m, NVRegisterUD_m;
always @(posedge SclkInc_iqk)
if (~CS_iqn) ParallelData_q <= #dly {ParallelData_q[22:0], DinUD_iq};
always @(posedge CS_iqn) begin
if (SPIUD_iq) begin
case (ParallelData_q[21:20])
2'b00: Latch10BitsSPI_m = ParallelData_q[15:6];
2'b10: NVRegisterSPI_m = Latch10BitsSPI_m;
2'b11: Latch10BitsSPI_m = NVRegisterSPI_m;
default: Latch10BitsSPI_m = 10'b1010101010;
endcase
end
end
always @(negedge SclkInc_iqk) begin
if (~SPIUD_iq && ~CS_iqn) begin
if (DinUD_iq) Latch10BitsUD_m <= #dly Latch10BitsUD_m + 1'b1;
else if (~DinUD_iq) Latch10BitsUD_m <= #dly Latch10BitsUD_m - 1'b1;
end
end
always @(posedge CS_iqn) if (SclkInc_iqk) NVRegisterUD_m <= #dly Latch10BitsUD_m;
always @* begin
if (SPIUD_iq) begin
Latch10Bits_m <= #dly Latch10BitsSPI_m;
NVRegister_m <= #dly NVRegisterSPI_m;
end
else if (~SPIUD_iq) begin
Latch10Bits_m <= #dly Latch10BitsUD_m;
NVRegister_m <= #dly NVRegisterUD_m;
end
end
endmodule
......@@ -8,9 +8,13 @@ module AddressDecoderWBSys(
input AckIntMAnager_i,
output reg StbIntManager_o,
input [31:0] DatDebugRegs_ib32,
input AckDebugRegs_i,
output reg StbDebugRegs_o,
input [31:0] DatGenericOutputRegs_ib32,
input AckGenericOutputRegs_i,
output reg StbGenericOutputRegs_o,
input [31:0] DatGenericInputRegs_ib32,
input AckGenericInputRegs_i,
output reg StbGenericInputRegs_o,
input [31:0] DatSlv2SerWB_ib32,
input AckSlv2SerWB_i,
......@@ -21,24 +25,28 @@ module AddressDecoderWBSys(
output reg StbSpiMaster_o
);
assign Ack_o = AckIntMAnager_i || AckDebugRegs_i || AckSlv2SerWB_i || AckSpiMaster_i;
assign Ack_o = AckIntMAnager_i || AckGenericOutputRegs_i || AckGenericOutputRegs_i || AckSlv2SerWB_i || AckSpiMaster_i;
always @* begin
Dat_ob32 = 32'h0;
StbIntManager_o = 1'b0;
StbDebugRegs_o = 1'b0;
StbGenericOutputRegs_o = 1'b0;
StbGenericInputRegs_o = 1'b0;
StbSlv2SerWB_o = 1'b0;
StbSpiMaster_o = 1'b0;
if (Adr_ib22[21:2]==20'h0) begin // FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs (16B)
if (Adr_ib22[21:2]==20'h0) begin // FROM 00_0000 TO 00_0003 (WB) == FROM 00_0000 TO 00_000C (VME) <- 4 regs (16B)
StbIntManager_o = Stb_i;
Dat_ob32 = DatIntManager_ib32;
end else if (Adr_ib22[21:2]==20'h1) begin // FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs (16B)
StbDebugRegs_o = Stb_i;
Dat_ob32 = DatDebugRegs_ib32;
end else if (Adr_ib22[21:3]==19'h1) begin // FROM 00_0008 TO 00_000F (WB) == FROM 00_0020 TO 00_003C (VME) <- 8 regs (32B)
end else if (Adr_ib22[21:2]==20'h1) begin // FROM 00_0004 TO 00_0007 (WB) == FROM 00_0010 TO 00_001C (VME) <- 4 regs (16B)
StbGenericOutputRegs_o = Stb_i;
Dat_ob32 = DatGenericOutputRegs_ib32;
end else if (Adr_ib22[21:2]==20'h2) begin // FROM 00_0008 TO 00_000B (WB) == FROM 00_0020 TO 00_002C (VME) <- 4 regs (16B)
StbGenericInputRegs_o = Stb_i;
Dat_ob32 = DatGenericInputRegs_ib32;
end else if (Adr_ib22[21:3]==19'h2) begin // FROM 00_0010 TO 00_0017 (WB) == FROM 00_0040 TO 00_005C (VME) <- 8 regs (32B)
StbSpiMaster_o = Stb_i;
Dat_ob32 = DatSpiMaster_ib32;
end else if (Adr_ib22[21]==1'b1) begin // FROM 20_0000 TO 3F_FFFF (WB) == FROM 80_0000 TO FF_FFFC (VME) <- 2M regs (8MB)
end else if (Adr_ib22[21]==1'b1) begin // FROM 20_0000 TO 3F_FFFF (WB) == FROM 80_0000 TO FF_FFFC (VME) <- 2M regs (8MB)
StbSlv2SerWB_o = Stb_i;
Dat_ob32 = DatSlv2SerWB_ib32;
end
......
......@@ -93,7 +93,7 @@ wire [31:0] DebugReg0, DebugReg1, DebugReg2, DebugReg3;
wire [31:0] DatDebugRegsrO_b32;
wire StbDebugRegs, AckDebugRegs;
Generic4RegsWB i_DebugRegs(
Generic4OutputRegs i_DebugRegs(
.Rst_irq(Rst_rq),
.Clk_ik(Clk_k),
.Cyc_i(Cyc),
......
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module Generic4InputRegs (
input Rst_irq,
input Clk_ik,
input Cyc_i,
input Stb_i,
input We_i,
input [1:0] Adr_ib2,
output reg [31:0] Dat_oab32,
output Ack_oa,
input [31:0] Reg0Value_ib32,
input [31:0] Reg1Value_ib32,
input [31:0] Reg2Value_ib32,
input [31:0] Reg3Value_ib32);
assign Ack_oa = Stb_i&&Cyc_i;
always @* case (Adr_ib2)
2'b00: Dat_oab32 = Reg0Value_ib32;
2'b01: Dat_oab32 = Reg1Value_ib32;
2'b10: Dat_oab32 = Reg2Value_ib32;
2'b11: Dat_oab32 = Reg3Value_ib32;
default: Dat_oab32 = Reg0Value_ib32;
endcase
endmodule
module Generic4OutputRegs
#( parameter
Reg0Default = 32'h0,
Reg1Default = 32'h0,
Reg2Default = 32'h0,
Reg3Default = 32'h0)
( input Rst_irq,
input Clk_ik,
input Cyc_i,
input Stb_i,
input We_i,
input [1:0] Adr_ib2,
input [31:0] Dat_ib32,
output reg [31:0] Dat_oab32,
output Ack_oa,
output reg [31:0] Reg0Value_ob32,
output reg [31:0] Reg1Value_ob32,
output reg [31:0] Reg2Value_ob32,
output reg [31:0] Reg3Value_ob32);
always @(posedge Clk_ik)
if (Rst_irq) Reg0Value_ob32 <= #1 Reg0Default;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b00) Reg0Value_ob32 <= Dat_ib32;
always @(posedge Clk_ik)
if (Rst_irq) Reg1Value_ob32 <= #1 Reg1Default;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b01) Reg1Value_ob32 <= Dat_ib32;
always @(posedge Clk_ik)
if (Rst_irq) Reg2Value_ob32 <= #1 Reg2Default;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b10) Reg2Value_ob32 <= Dat_ib32;
always @(posedge Clk_ik)
if (Rst_irq) Reg3Value_ob32 <= #1 Reg3Default;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==(2'b11)) Reg3Value_ob32 <= Dat_ib32;
assign Ack_oa = Stb_i&&Cyc_i;
always @* case (Adr_ib2)
2'b00: Dat_oab32 = Reg0Value_ob32;
2'b01: Dat_oab32 = Reg1Value_ob32;
2'b10: Dat_oab32 = Reg2Value_ob32;
2'b11: Dat_oab32 = Reg3Value_ob32;
default: Dat_oab32 = Reg0Value_ob32;
endcase
endmodule
......@@ -23,6 +23,9 @@
output reg [31:0] Dat_oab32,
output reg Ack_oa,
output reg WaitingNewData_o,
output reg ModuleIdle_o,
output reg SClk_o,
output MoSi_o,
input [31:0] MiSo_ib32,
......@@ -88,7 +91,9 @@ reg WriteAck_q, StartTx_q;
assign MoSi_o = a_Lsb1St ? ShiftOut_qb32[0] : ShiftOut_qb32[31];
always @(posedge Clk_ik) begin
WriteAck_q <= WriteAck_q && Stb_i; // Default clear condition valid for all the states
WriteAck_q <= WriteAck_q && Stb_i; // Default clear condition valid for all the states
ModuleIdle_o <= 'h0;
WaitingNewData_o <= 'h0;
if (Rst_irq) begin
StartTx_q <= 'b0;
WriteAck_q <= 'b0;
......@@ -100,12 +105,15 @@ always @(posedge Clk_ik) begin
Config2_qb32 <= 'h0;
ShiftOut_qb32 <= 'h0;
ShiftIn_qb32 <= 'h0;
ModuleIdle_o <= 'h0;
WaitingNewData_o <= 'h0;
end else case (State_q)
`s_Idle: begin
SClk_o <= a_CPol;
SS_onb32 <= 32'h_FFFF_FFFF;
TimeCounter_cb16 <= 'h0;
TxCounter_cb12 <= 'h0;
ModuleIdle_o <= State_a==`s_Idle;
if (Cyc_i && We_i && Stb_i && Adr_ib3==`c_AddrShiftOut) begin
ShiftOut_qb32 <= Dat_ib32;
ShiftIn_qb32 <= 'h0;
......@@ -145,6 +153,7 @@ always @(posedge Clk_ik) begin
end
end
`s_TxPause: begin
WaitingNewData_o <= State_a==`s_TxPause;
if (Cyc_i && We_i && Stb_i && Adr_ib3==`c_AddrShiftOut) begin
ShiftOut_qb32 <= Dat_ib32;
ShiftIn_qb32 <= 'h0;
......@@ -167,6 +176,8 @@ always @(posedge Clk_ik) begin
Config2_qb32 <= 'h0;
ShiftOut_qb32 <= 'h0;
ShiftIn_qb32 <= 'h0;
ModuleIdle_o <= 'h0;
WaitingNewData_o <= 'h0;
end
endcase
end
......
This diff is collapsed.
......@@ -409,12 +409,96 @@ SystemFpga i_SystemFpga(
.AFpgaProgM_iob2(AFpgaProgM_b2),
.AFpgaProgCsi_io(AFpgaProgCsi),
.AFpgaProgRdWr_io(AFpgaProgRdWr),
.AFpgaProgInit_io(AFpgaProgInit)
.AFpgaProgInit_io(AFpgaProgInit),
.FlashSFpgaD_o(),
.FlashSFpgaClk_ok(),
.FlashSFpgaCs_on(),
.FlashSFpgaQ_i(),
.FlashAFpgaD_o(),
.FlashAFpgaClk_ok(),
.FlashAFpgaCs_on(),
.FlashAFpgaQ_i(),
.VAdcSClk_ok(),
.VAdcDout_i(),
.VAdcDin_o(),
.VAdcCs_on(),
.VAdjCs_on(VAdjCs),
.VAdjSClk_ok(VAdjSClk_k),
.VAdjDin_o(VAdjDin),
.VAdjInhibit_ozn(),
.VAdjSpi_o(VAdjSpi),
.PllFmc1Ld_i(),
.PllFmc1Status_i(),
.PllFmc1RefMon_i(),
.PllFmc1RefSel_o(),
.PllFmc1Ref1_ok(),
.PllFmc1Pd_on(),
.PllFmc1Synch_on(),
.PllFmc1Reset_orn(),
.PllFmc1SClk_ok(),
.PllFmc1SDio_io(),
.PllFmc1Sdo_i(),
.PllFmc1Cs_on(),
.PllFmc12SFpgaP_ik(),
.PllFmc2Ld_i(),
.PllFmc2Status_i(),
.PllFmc2RefMon_i(),
.PllFmc2RefSel_o(),
.PllFmc2Ref1_ok(),
.PllFmc2Pd_on(),
.PllFmc2Synch_on(),
.PllFmc2Reset_orn(),
.PllFmc2SClk_ok(),
.PllFmc2SDio_io(),
.PllFmc2Sdo_i(),
.PllFmc2Cs_on(),
.PllFmc22SFpgaP_ik(),
.PllSysLd_i(),
.PllSysStatus_i(),
.PllSysRefMon_i(),
.PllSysRefSel_o(),
.PllSysRef12_ok(),
.PllSysPd_on(),
.PllSysSynch_on(),
.PllSysReset_orn(),
.PllSysSClk_ok(),
.PllSysSDio_io(),
.PllSysSdo_i(),
.PllSysCs_on(),
.PllSys2SFpgaP_ik(),
.PllDdsLd_i(),
.PllDdsStatus_i(),
.PllDdsRefMon_i(),
.PllDdsRefSel_o(),
.PllDdsPd_on(),
.PllDdsSynch_on(),
.PllDdsReset_orn(),
.PllDdsClk_ok(),
.PllDdsSClk_ok(),
.PllDdsSDio_io(),
.PllDdsSdo_i(),
.PllDdsCs_on(),
.PllDds2SFpgaP_ik(),
.PllDacSClk_ok(),
.PllDacSynch_on(),
.PllDacDin_o(),
.PllDacDout_i(),
.PllDacClrn_orn(),
.PllDacLDac_on()
);
//##############################################################
// APPLICATIO FPGA
// APPLICATION FPGA
//##############################################################
ApplicationFpga i_ApplicationFpga(
......@@ -433,5 +517,18 @@ ApplicationFpga i_ApplicationFpga(
.PushButton_ion(a_PushButton_n),
.FpGpIo_iob4(FpGpIo_b4)
);
);
//##############################################################
// Power Supplies
//##############################################################
wire VAdjSpi, VAdjSClk_k, VAdjDin, VAdjCs;
MAX5483 ic44(
.SPIUD_iq(VAdjSpi),
.CS_iqn(VAdjCs),
.SclkInc_iqk(VAdjSClk_k),
.DinUD_iq(VAdjDin));
endmodule
......@@ -5,7 +5,12 @@
//implemented for each module.
//The same is true for U.D. pins on P2 and all the P0 connections.
module VmeMaster (
module VmeMaster
#(
parameter gfd_FileOutput = 32'h8000_0001, //default is standard out
g_VerboseAccesses = 1'b1 //write access results to standard out
)
(
output reg Trst_o,
output reg Tck_o,
input Tdo_i,
......@@ -35,20 +40,14 @@ initial begin
SysReset_o = 1'b1;
end
parameter [31:0] gfd_FileOutput = 32'h8000_0001; //default is standard out
parameter g_FileOutput_e = 1'b0; //default disabled
parameter g_VerboseAccesses = 1'b1; //write access results to standard out
reg [31:0] a_D = 32'hz;
reg [31:1] a_A = 31'hz;
reg a_LWord = 1'bz;
integer fd_Output;
reg FileOutput_e;
reg fd_FileOutput;
reg VerboseAccesses;
initial FileOutput_e = g_FileOutput_e;
initial fd_FileOutput = gfd_FileOutput;
initial VerboseAccesses= g_VerboseAccesses;
......@@ -79,7 +78,7 @@ begin
i=0;
while (DtAck_i && Retry_i && Berr_i && ~(i==1000)) #10 i=i+1;
if (~Berr_i) begin
if (VerboseAccesses) $display("Bus Error asserted");
if (VerboseAccesses) $display(fd_FileOutput,"Bus Error asserted");
ExitCode = 8'h2;
As_o = 1'b1;
Ds1_o = 1'b1;
......@@ -87,7 +86,7 @@ begin
a_D = 32'hz;
a_A = 31'hz;
end else if (~Retry_i) begin
if (VerboseAccesses) $display("Slave asserted retry request");
if (VerboseAccesses) $display(fd_FileOutput,"Slave asserted retry request");
ExitCode = 8'h3;
As_o = 1'b1;
Ds1_o = 1'b1;
......@@ -95,7 +94,7 @@ begin
a_D = 32'hz;
a_A = 31'hz;
end else if (DtAck_i) begin
if (VerboseAccesses) $display("No module response to the vme write request: time out");
if (VerboseAccesses) $display(fd_FileOutput,"No module response to the vme write request: time out");
ExitCode = 8'h1;
As_o = 1'b1;
Ds1_o = 1'b1;
......@@ -112,14 +111,13 @@ begin
i=0;
while (~DtAck_i && ~(i==1000)) #10 i=i+1;
if (~DtAck_i) begin
if (VerboseAccesses) $display("Unable to close the vme write in a usefull time: time out");
if (VerboseAccesses) $display(fd_FileOutput,"Unable to close the vme write in a usefull time: time out");
ExitCode = 8'h1;
end else begin
ExitCode =8'h0;
if (VerboseAccesses) $display ("VME write cycle: d = %h at address %h address at %t",Data ,Address, $time);
if (VerboseAccesses) $display(fd_FileOutput,"VME write cycle: d = %h at address %h address at %t",Data ,Address, $time);
end
end
if (FileOutput_e) $fdisplay(fd_Output, "%d", ExitCode);
a_A = 31'bz;
a_LWord = 1'bz;
a_D = 32'bz;
......@@ -150,7 +148,7 @@ begin
i=0;
while (DtAck_i && ~(i==1000)) #10 i=i+1;
if (DtAck_i) begin
if (VerboseAccesses) $display("No module response to the vme read request @ 32'h%h : time out", Address);
if (VerboseAccesses) $display(fd_FileOutput,"No module response to the vme read request @ 32'h%h : time out", Address);
ExitCode = 8'd1;
As_o = 1'b1;
Ds1_o = 1'b1;
......@@ -164,10 +162,10 @@ begin
i=0;
while (~DtAck_i && ~(i==1000)) #10 i=i+1;
if (~DtAck_i) begin
if (VerboseAccesses) $display("Unable to close the vme read in a usefull time: time out");
if (VerboseAccesses) $display(fd_FileOutput,"Unable to close the vme read in a usefull time: time out");
ExitCode = 8'd2;
end else begin
if (VerboseAccesses) $display ("VME read cycle: d = %h at address %h of A32 address space at %t", DataRead, Address,$time);
if (VerboseAccesses) $display(fd_FileOutput,"VME read cycle: d = %h at address %h of A32 address space at %t", DataRead, Address,$time);
ExitCode = 8'd0;
end
end
......@@ -187,13 +185,13 @@ task AcknowledgeInterrupt;
output ExitCode; // 0=Interrupt received, 1=Time out, 2=Bus Error during the acknowledge
integer i;
begin
$display("Waiting for interrupt.....");
if (VerboseAccesses) $display(fd_FileOutput,"Waiting for interrupt.....");
InterruptLevel = 'h0;
a_D = 32'bz;
i = 0;
while (&Irq_i && ~(i==150)) #100 i=i+1;
if (&Irq_i) begin
$display("No interrupt received: time out");
if (VerboseAccesses) $display(fd_FileOutput,"No interrupt received: time out");
interrupt_vector = 32'hx;
ExitCode = 'd1;
end else begin
......@@ -201,17 +199,17 @@ begin
a_A[3:1] = ~Irq_i[7] ? 3'h7 : (~Irq_i[6] ? 3'h6 : (~Irq_i[5] ? 3'h5 : (~Irq_i[4] ? 3'h4 : (~Irq_i[3] ? 3'h3 : (~Irq_i[2] ? 3'h2 : ~Irq_i[1] ? 3'h1 : 3'hx)))));
#10 As_o = 1'b0;
InterruptLevel = a_A[3:1];
$display("Received interrupt reqest of priority level %d", InterruptLevel);
if (VerboseAccesses) $display(fd_FileOutput,"Received interrupt reqest of priority level %d", InterruptLevel);
Ds1_o = 1'b0;
Write_o = 1'b1;
i = 0;
while (DtAck_i && ~(i==1000)) #1 i=i+1;
if (DtAck_i) begin
$display("No module responded to the interrupt acknoledge in a usefull time");
if (VerboseAccesses) $display(fd_FileOutput,"No module responded to the interrupt acknoledge in a usefull time");
ExitCode = 'd2;
end else begin
interrupt_vector = D_b ;
$display("Received interrupt vector: %h", interrupt_vector);
if (VerboseAccesses) $display(fd_FileOutput,"Received interrupt vector: %h", interrupt_vector);
ExitCode = 'd0;
end
#10;
......@@ -221,7 +219,7 @@ begin
i=0;
while (~DtAck_i && ~(i==10)) #1000 i=i+1;
if (~DtAck_i) begin
$display("Unable to close the vme interrupt acknoledge in a usefull time: time out");
if (VerboseAccesses) $display(fd_FileOutput,"Unable to close the vme interrupt acknoledge in a usefull time: time out");
ExitCode = 'd2;
end
end
......@@ -259,7 +257,7 @@ begin
$dumpfile("simout.vcd");
$dumpvars(0, tb_VFC);
end else if (command=="I" || command=="i") begin
// $display("Which level of interrupt(1 to 7)? 0x");
// $display(fd_FileOutput,"Which level of interrupt(1 to 7)? 0x");
AcknowledgeInterrupt(IntLevel3, data32, command);
fd_MyFifoOut = $fopen("V2Py.fifo", "w");
$fwrite(fd_MyFifoOut, "%x\n", command);
......@@ -267,7 +265,7 @@ begin
$fwrite(fd_MyFifoOut, "%x\n", data32);
$fclose(fd_MyFifoOut);
end else if (command=="A" || command=="a") begin
// $display("For how long do you want to wait? ");
// $display(fd_FileOutput,"For how long do you want to wait? ");
// outcode=$fscanf(32'h8000_0000, "%d", data32);
// outcode=$fgetc(32'h8000_0000); //just to get rid of the nl
outcode=$fscanf(fd_MyFifoIn, "%d", data32);
......@@ -279,35 +277,35 @@ begin
SysReset_o = 1'b1;
#200;
end else if (command=="W" || command=="w") begin
// $display("At which address you want to write?");
// $display(fd_FileOutput,"At which address you want to write?");
// outcode=$fscanf(32'h8000_0000, "%h", address32);
// outcode=$fgetc(32'h8000_0000); //just to get rid of the nl
outcode=$fscanf(fd_MyFifoIn, "%h", address32);
outcode=$fgetc(fd_MyFifoIn); //just to get rid of the nl
// $display("What do you want to write?");
// $display(fd_FileOutput,"What do you want to write?");
// outcode=$fscanf(32'h8000_0000, "%h", data32);
// outcode=$fgetc(32'h8000_0000); //just to get rid of the nl
outcode=$fscanf(fd_MyFifoIn, "%h", data32);
outcode=$fgetc(fd_MyFifoIn); //just to get rid of the nl
SimpleWrite(address32, 6'h09, data32, command);
// $display("Executed with exit code %d", command);
// $display(fd_FileOutput,"Executed with exit code %d", command);
fd_MyFifoOut = $fopen("V2Py.fifo", "w");
$fwrite(fd_MyFifoOut, "%x\n", command);
$fclose(fd_MyFifoOut);
end else if (command=="R" || command=="r") begin
// $display("At which address you want to read?");
// $display(fd_FileOutput,"At which address you want to read?");
// outcode=$fscanf(32'h8000_0000, "%h", address32);
// outcode=$fgetc(32'h8000_0000); //just to get rid of the nl
outcode=$fscanf(fd_MyFifoIn, "%h", address32);
outcode=$fgetc(fd_MyFifoIn); //just to get rid of the nl
SimpleRead(address32, 6'h09, data32, command);
// $display("Executed with exit code %d", command);
// $display("Read %x", data32);
// $display(fd_FileOutput,"Executed with exit code %d", command);
// $display(fd_FileOutput,"Read %x", data32);
fd_MyFifoOut = $fopen("V2Py.fifo", "w");
$fwrite(fd_MyFifoOut, "%x\n", command);
$fwrite(fd_MyFifoOut, "%x\n", data32);
$fclose(fd_MyFifoOut);
end else $display("%tns: %c is an UNKNOWN COMMAND (hex is %x)", $time, command, command);
end else $display(fd_FileOutput,"%tns: %c is an UNKNOWN COMMAND (hex is %x)", $time, command, command);
end
end
endtask
......
......@@ -42,7 +42,7 @@ pullup i_Irq0(VmeIrq_b7[0]);
// VME master
//####################################
VmeMaster i_VmeMaster(
VmeMaster #(.g_VerboseAccesses(1'b0)) i_VmeMaster(
.Trst_o(VmeTrst),
.Tck_o(VmeTck),
.Tdo_i(VmeTdo),
......
......@@ -4,12 +4,14 @@ VerilogFiles=
# Components' models
VerilogFiles+= ../hdl/components/ivt3205c25mhz.v
VerilogFiles+= ../hdl/components/sn74vmeh22501.v
VerilogFiles+= ../hdl/components/MAX5483.v
# Components with missing models
VerilogFiles+= ../hdl/components/blackboxes/si57x.v
# System FPGA's modules
VerilogFiles+= ../hdl/design/SystemFpga.v
VerilogFiles+= ../hdl/design/AddrDecoderWBSys.v
VerilogFiles+= ../hdl/design/Generic4RegsWB.v
VerilogFiles+= ../hdl/design/Generic4OutputRegs.v
VerilogFiles+= ../hdl/design/Generic4InputRegs.v
VerilogFiles+= ../hdl/design/Monostable.v
VerilogFiles+= ../hdl/design/Debouncer.v
VerilogFiles+= ../hdl/design/InterruptManagerWB.v
......@@ -55,6 +57,6 @@ simplesim.o: $(VerilogFiles)
%.fifo:
@mkfifo $@
simout.vcd: simplesim.o $(PythonFiles)
simout.vcd: simplesim.o $(PythonFiles) Py2V.fifo V2Py.fifo
@(cd ../software ; python mysim.py)
from VmeFunctions import *
class VfcRegisters:
###############################################################################
###############################################################################
# REGISTER SPACE
###############################################################################
###############################################################################
def __init__(self, Slot):
self.Slot = Slot
BoardBaseAddress = Slot*2**24
#@@@@@@@@@@@@@@@@@@@@@@
#System FPGA
#@@@@@@@@@@@@@@@@@@@@@@
#-----------------------
#Interrupt manager block registers
#-----------------------
self.InterruptStatus = VmeRegister(BoardBaseAddress + 0x0)
self.InterruptConfig = VmeRegister(BoardBaseAddress + 0x4)
self.ReleaseID = VmeRegister(BoardBaseAddress + 0x8)
#-----------------------
#Generic Output reg block (BA=0x10)
#-----------------------
self.InterruptLvlVect = VmeRegister(BoardBaseAddress + 0x10)
self.GenericOutputReg1 = VmeRegister(BoardBaseAddress + 0x14)
self.PllsControlBits = VmeRegister(BoardBaseAddress + 0x18)
self.GenericOutputReg3 = VmeRegister(BoardBaseAddress + 0x1C)
#-----------------------
#Generic Input reg block (BA=0x10)
#-----------------------
self.PllsStatusBits = VmeRegister(BoardBaseAddress + 0x20)
self.GenericInputReg1 = VmeRegister(BoardBaseAddress + 0x24)
self.GenericInputReg2 = VmeRegister(BoardBaseAddress + 0x28)
self.GenericInputReg3 = VmeRegister(BoardBaseAddress + 0x2C)
#-----------------------
#SPI Master (BA=0x20)
#-----------------------
self.SpiMasterStatus = VmeRegister(BoardBaseAddress + 0x40)
self.SpiMasterConfig1 = VmeRegister(BoardBaseAddress + 0x44)
self.SpiMasterConfig2 = VmeRegister(BoardBaseAddress + 0x48)
self.SpiMasterShiftOut = VmeRegister(BoardBaseAddress + 0x4C)
self.SpiMasterShiftIn = VmeRegister(BoardBaseAddress + 0x50)
#@@@@@@@@@@@@@@@@@@@@@@@
#Appliation FPGA
#@@@@@@@@@@@@@@@@@@@@@@@
AFPGABaseAddress = 0x800000
#-----------------------
#Debug reg block (BA=0x0)
#-----------------------
self.ApplDebugReg0 = VmeRegister(BoardBaseAddress + AFPGABaseAddress + 0x0)
self.ApplDebugReg1 = VmeRegister(BoardBaseAddress + AFPGABaseAddress + 0x4)
self.ApplDebugReg2 = VmeRegister(BoardBaseAddress + AFPGABaseAddress + 0x8)
self.ApplDebugReg3 = VmeRegister(BoardBaseAddress + AFPGABaseAddress + 0xC)
from VmeFunctions import *
from VfcRegistersMap import *
import numpy as np
class VmeRegister:
def __init__(self, Addr):
self.VmeAddr = Addr
def Write(self, Data):
ExitCode = VmeWrite(self.VmeAddr, Data)
return ExitCode
def Read(self):
Value = VmeRead(self.VmeAddr)
return Value
class VFCInstance:
class VFCInstance(VfcRegisters):
def __init__(self, Slot, IntLevel, IntVector):
self.Slot = Slot
VfcRegisters.__init__(self, Slot)
self.IntLevel = IntLevel
self.IntVector = IntVector
BoardBaseAddress = Slot*2**24
#@@@@@@@@@@@@@@@@@@@@@@
#System FPGA
#@@@@@@@@@@@@@@@@@@@@@@
#Interrupt manager block registers
self.InterruptStatus = VmeRegister(BoardBaseAddress + 0x0)
self.InterruptConfig = VmeRegister(BoardBaseAddress + 0x4)
self.ReleaseID = VmeRegister(BoardBaseAddress + 0x8)
#Debug reg block (BA=0x10)
self.DebugReg0 = VmeRegister(BoardBaseAddress + 0x10)
self.DebugReg1 = VmeRegister(BoardBaseAddress + 0x14)
self.DebugReg2 = VmeRegister(BoardBaseAddress + 0x18)
self.DebugReg3 = VmeRegister(BoardBaseAddress + 0x1C)
#SPI Master (BA=0x20)
self.SpiMasterStatus = VmeRegister(BoardBaseAddress + 0x20)
self.SpiMasterConfig1 = VmeRegister(BoardBaseAddress + 0x24)
self.SpiMasterConfig2 = VmeRegister(BoardBaseAddress + 0x28)
self.SpiMasterShiftOut = VmeRegister(BoardBaseAddress + 0x2C)
self.SpiMasterShiftIn = VmeRegister(BoardBaseAddress + 0x30)
#@@@@@@@@@@@@@@@@@@@@@@@
#Appliation FPGA
#@@@@@@@@@@@@@@@@@@@@@@@
AFPGABaseAddress = 0x800000
#Debug reg block (BA=0x0)
self.ApplDebugReg0 = VmeRegister(BoardBaseAddress + AFPGABaseAddress + 0x0)
self.ApplDebugReg1 = VmeRegister(BoardBaseAddress + AFPGABaseAddress + 0x4)
self.ApplDebugReg2 = VmeRegister(BoardBaseAddress + AFPGABaseAddress + 0x8)
self.ApplDebugReg3 = VmeRegister(BoardBaseAddress + AFPGABaseAddress + 0xC)
def EnableInterrupts(self, Mask):
self.DebugReg0.Write(self.IntLevel*0x10000000+self.IntVector)
self.InterruptConfig.Write(0x200 + Mask)
self.IntVector = IntVector
#-----------------------
# Interrupts
#-----------------------
def ConfigureInterrupts(self):
self.InterruptLvlVect.Write(self.IntLevel*0x10000000+self.IntVector)
def EnableSpiIdleInterrupt(self):
self.InterruptConfig.Write(self.InterruptConfig.Read()&0xFFFFFFFD)
def EnableSpiWaitingDataInterrupt(self):
self.InterruptConfig.Write(self.InterruptConfig.Read()&0xFFFFFFFE)
def EnableDebugInterrupt(self):
self.InterruptConfig.Write(self.InterruptConfig.Read()&0xFFFFFF03)
def DisableSpiIdleInterrupt(self):
self.InterruptConfig.Write(self.InterruptConfig.Read()|0x2)
def DisableSpiWaitingDataInterrupt(self):
self.InterruptConfig.Write(self.InterruptConfig.Read()|0x1)
def DisableDebugInterrupt(self):
self.InterruptConfig.Write(self.InterruptConfig.Read()|0xFC)
def GenerateDebugInterrupt(self, Status):
self.DebugReg1.Write(0x0)
self.DebugReg1.Write(Status)
self.DebugReg1.Write(0x0)
self.GenericOutputReg1.Write(0x0)
self.GenericOutputReg1.Write(Status)
self.GenericOutputReg1.Write(0x0)
def WaitInterrupt(self):
IntStatus = 'X'
[IntLevel, IntVector] = VmeWaitInterrupt()
......@@ -62,6 +36,9 @@ class VFCInstance:
else : print "Wrong Vector: expecting "+ Slot+ " received "+ IntVector
else : print "Wrong IntLevel: expecting ", self.IntLevel, " received ", IntLevel
return IntStatus
#-----------------------
# SPI
#-----------------------
def SpiAccess(self, Channel, CPol, CPha, LSB1st, Lenght, Data, HalfPeriod, WaitTime):
if Channel>=32 or Channel<0 :
print "Error: SPI Channel out of range"
......@@ -122,4 +99,43 @@ class VFCInstance:
else :
ReadValue = ReadValue*2**32+PartialShift
return ReadValue
#-----------------------
# VAdj Control
#-----------------------
def SetVadjWiper(self, Value):
Data = Value*2**6
print "Sending value ", hex(Data)
self.SpiAccess(1, 1, 1, 0, 24, Data, 32, 0)
def SaveVadjWiper(self):
self.SpiAccess(1, 1, 1, 0, 8, 0x20, 32, 0)
def LoadVadjWiper(self):
self.SpiAccess(1, 1, 1, 0, 8, 0x30, 32, 0)
#-----------------------
# PLLs Configuration registers
#-----------------------
# def ConfPllSpi(self, Pll):
#configura la comunicazione scrivendo nel registro 1
# def WritePllRegister(self, Pll, RegAddress, Value):
#scivi il valore con davanti la giusta istruzione
#leggi il valore bufferato
#se il valore bufferato e' quello che volevamo attiva
#se il valore non e' buono invia un errore (return error value)
# def ReadPllBufferedRegister(self, Pll, RegAddress):
#scivi che vuoi il valore bufferato in reg4
#leggi il valore del registo
# def ReadPllActiveRegister(self, Pll, RegAddress):
#scivi che vuoi il valore attivo in reg4
#leggi il valore del registo
# def SetPllRefSel(self, Pll, Value):
#Leggi il valore, maschera e fai un or
# def SetPllPd(self, Pll, Value):
#Leggi il valore, maschera e fai un or
# def SetPllSynch(self, Pll, Value):
#Leggi il valore, maschera e fai un or
# def SetPllReset(self, Pll, Value):
#Leggi il valore, maschera e fai un or
# def GetPllsStatus(self):
#leggi il registro
#splitta il valore con maschere per ottenere i vari status bit decodificati
class VmeRegister:
def __init__(self, Addr):
self.VmeAddr = Addr
def Write(self, Data):
VmeWrite(self.VmeAddr, Data)
def Read(self):
Value = VmeRead(self.VmeAddr)
return Value
def VmeWrite(Addr, Data):
MyString = 'W '+hex(Addr)[2:].strip('L')+' '+hex(Data)[2:].strip('L')+'\n'
fd_Out=open('../simulation/Py2V.fifo', 'w')
......
......@@ -2,16 +2,13 @@ from VmeDriver import *
from SimulationFunctions import *
import os
#os.system('mkfifo ../simulation/Py2V.fifo')
#os.system('mkfifo ../simulation/V2Py.fifo')
os.system('(cd ../simulation ; xterm make &)')
os.system('clear')
MyBoard = VFCInstance(4, 3, 4)
StartDumping()
#StartDumping()
WaitSimulation('1000')
VmeReset()
......@@ -23,17 +20,19 @@ print "Release: ", hex(MyBoard.ReleaseID.Read())
print""
print "Enabling all the interrupts"
MyBoard.EnableInterrupts(0x0)
MyBoard.ConfigureInterrupts()
print "Int Config reg: ", hex(MyBoard.InterruptConfig.Read())
print""
IntSource = 0xa
IntSource = 0xC
print "Sending a request to generate an interrupt with Satus(Source): ", hex(IntSource)
MyBoard.EnableDebugInterrupt()
MyBoard.GenerateDebugInterrupt(IntSource)
print "Waiting for interrupt"
Status = MyBoard.WaitInterrupt()
if Status==IntSource : print "Received the expected interrupt (status: ", hex(Status), " )"
else : print "Wrong Status: expecting ", MyBoard.IntVector, " received " , hex(Status)
else : print "Wrong Status: expecting ", MyBoard.IntVector, " received " , hex(Status)
MyBoard.DisableDebugInterrupt()
print""
print""
......@@ -144,71 +143,24 @@ print "Read ", hex(Value)
WaitSimulation(10000)
StopSimulation()
exit()
print""
print "Setting the VAdj wiper to 0x200"
MyBoard.SetVadjWiper(0x200)
# VMET ACCESS
import sys
def CommandPrompt() :
sys.stdout.write('Enter a command: \n')
sys.stdout.write('1: write\n')
sys.stdout.write('2: read\n')
sys.stdout.write('3: wait an interrupt\n')
MyString ="9: change base address["+hex(BaseAddress)+"]\n"
sys.stdout.write(MyString)
sys.stdout.write('e: exit\n\n')
sys.stdout.write('> ')
Command=sys.stdin.readline().strip('\n')
os.system('clear')
return Command
def BuildAddress (BaseAddress, RequestString) :
sys.stdout.write(RequestString)
return hex(BaseAddress + int(sys.stdin.readline().strip('\n'), 16)).lstrip('0x')
def SendCommand(CommandString) :
fd_Out=open('../simulation/Py2V.fifo', 'w')
fd_Out.write(CommandString)
fd_Out.close()
def ReadResult():
fd_In=open('../simulation/V2Py.fifo', 'r')
ResultString = fd_In.read()
fd_In.close()
return ResultString
Command=' '
BaseAddress=0
Command = CommandPrompt()
while (Command!='e'):
if Command=='1' :
Address =BuildAddress(BaseAddress, 'Where do you want to write? 0x')
sys.stdout.write('What do you want to write? ')
Value =sys.stdin.readline().strip('\n')
MyString = 'W '+Address+' '+Value+'\n'
SendCommand(MyString)
print ReadResult()
sys.stdin.readline()
elif Command=='2' :
Address =BuildAddress(BaseAddress,'Where do you want to read? 0x' )
MyString = 'R '+Address+'\n'
SendCommand(MyString)
print ReadResult()
sys.stdin.readline()
elif Command=='3' :
MyString = 'I \n'
SendCommand(MyString)
print ReadResult()
sys.stdin.readline()
elif Command=='9' :
sys.stdout.write('What\'s the new base address? 0x')
BaseAddress =int(sys.stdin.readline().strip('\n'), 16)
Command = CommandPrompt()
StopSimulation()
print""
print "Loading the VAdj default into the wiper"
MyBoard.LoadVadjWiper()
print""
print "Setting the VAdj wiper to 0x201"
MyBoard.SetVadjWiper(0x201)
print""
print "Saving the VAdj wiper value into the non volatile memory"
MyBoard.SaveVadjWiper()
WaitSimulation(10000)
StopSimulation()
exit()
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