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Andrea Boccardi authored
Some Verilog file had to be modified, simulation to be checked
23b1b4b5
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SystemFpga.data | ||
SystemFpga.ppr | ||
planAhead.jou | ||
planAhead.log | ||
planAhead_run.log |
Some Verilog file had to be modified, simulation to be checked
Name |
Last commit
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Last update |
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.. | ||
SystemFpga.data | Loading commit data... | |
SystemFpga.ppr | Loading commit data... | |
planAhead.jou | Loading commit data... | |
planAhead.log | Loading commit data... | |
planAhead_run.log | Loading commit data... |