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Platform-independent core collection
Commit 0ed0cf1d authored by Dimitris Lampridis's avatar Dimitris Lampridis
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crossbar: add possibility to silence info messages during simulation

parent 1fdd01db
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Showing with 17 additions and 8 deletions
modules/wishbone/wb_crossbar/xwb_crossbar.vhd
View file @ 0ed0cf1d
...@@ -55,7 +55,9 @@ entity xwb_crossbar is ...@@ -55,7 +55,9 @@ entity xwb_crossbar is
g_registered : boolean := false; g_registered : boolean := false;
-- Address of the slaves connected -- Address of the slaves connected
g_address : t_wishbone_address_array; g_address : t_wishbone_address_array;
g_mask : t_wishbone_address_array); g_mask : t_wishbone_address_array;
-- Set to false to skip "Mapping Slave" notes during simulation
g_verbose : boolean := true);
port( port(
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
...@@ -111,10 +113,12 @@ architecture rtl of xwb_crossbar is ...@@ -111,10 +113,12 @@ architecture rtl of xwb_crossbar is
severity Failure; severity Failure;
-- Working case -- Working case
report "Mapping slave #" & if g_verbose then
Integer'image(i) & "[" & f_bits2string(c_address(i)) & "/" & report "Mapping slave #" &
f_bits2string(c_mask(i)) & "]" Integer'image(i) & "[" & f_bits2string(c_address(i)) & "/" &
severity Note; f_bits2string(c_mask(i)) & "]"
severity Note;
end if;
end loop; end loop;
return true; return true;
end f_ranges_ok; end f_ranges_ok;
......
modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
View file @ 0ed0cf1d
...@@ -31,6 +31,7 @@ use work.wishbone_pkg.all; ...@@ -31,6 +31,7 @@ use work.wishbone_pkg.all;
entity xwb_sdb_crossbar is entity xwb_sdb_crossbar is
generic( generic(
g_verbose : boolean := true;
g_num_masters : natural := 1; g_num_masters : natural := 1;
g_num_slaves : natural := 1; g_num_slaves : natural := 1;
g_registered : boolean := false; g_registered : boolean := false;
...@@ -232,7 +233,8 @@ begin ...@@ -232,7 +233,8 @@ begin
g_num_slaves => g_num_slaves + 1, g_num_slaves => g_num_slaves + 1,
g_registered => g_registered, g_registered => g_registered,
g_address => c_address, g_address => c_address,
g_mask => c_mask) g_mask => c_mask,
g_verbose => g_verbose)
port map( port map(
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
...@@ -248,7 +250,8 @@ begin ...@@ -248,7 +250,8 @@ begin
g_num_slaves => g_num_masters, g_num_slaves => g_num_masters,
g_registered => g_registered, g_registered => g_registered,
g_address => c_addresses.msi_address, g_address => c_addresses.msi_address,
g_mask => c_addresses.msi_mask) g_mask => c_addresses.msi_mask,
g_verbose => g_verbose)
port map( port map(
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
......
modules/wishbone/wishbone_pkg.vhd
View file @ 0ed0cf1d
...@@ -390,7 +390,8 @@ package wishbone_pkg is ...@@ -390,7 +390,8 @@ package wishbone_pkg is
g_num_slaves : integer; g_num_slaves : integer;
g_registered : boolean; g_registered : boolean;
g_address : t_wishbone_address_array; g_address : t_wishbone_address_array;
g_mask : t_wishbone_address_array); g_mask : t_wishbone_address_array;
g_verbose : boolean := true);
port ( port (
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
...@@ -419,6 +420,7 @@ package wishbone_pkg is ...@@ -419,6 +420,7 @@ package wishbone_pkg is
component xwb_sdb_crossbar component xwb_sdb_crossbar
generic ( generic (
g_verbose : boolean := true;
g_num_masters : integer; g_num_masters : integer;
g_num_slaves : integer; g_num_slaves : integer;
g_registered : boolean := false; g_registered : boolean := false;
......
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