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Platform-independent core collection
Commit 3ca2f67c authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Merge branch '50-add-rx-tx-interrupt-enable-in-wb_uart' into 'master' 

Resolve "add rx/tx interrupt enable in wb_uart"

See merge request !58
parents 15b035cf a2546bec
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Showing with 47 additions and 7 deletions
modules/wishbone/wb_uart/simple_uart_pkg.vhd
View file @ 3ca2f67c
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : simple_uart_pkg.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Fri Dec 8 11:12:47 2023
-- Created : Fri Jan 26 16:35:06 2024
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
......@@ -70,6 +70,8 @@ package uart_wbgen2_pkg is
host_tdr_data_wr_o : std_logic;
cr_rx_fifo_purge_o : std_logic;
cr_tx_fifo_purge_o : std_logic;
cr_rx_interrupt_enable_o : std_logic;
cr_tx_interrupt_enable_o : std_logic;
end record;
constant c_uart_out_registers_init_value: t_uart_out_registers := (
......@@ -82,7 +84,9 @@ package uart_wbgen2_pkg is
host_tdr_data_o => (others => '0'),
host_tdr_data_wr_o => '0',
cr_rx_fifo_purge_o => '0',
cr_tx_fifo_purge_o => '0'
cr_tx_fifo_purge_o => '0',
cr_rx_interrupt_enable_o => '0',
cr_tx_interrupt_enable_o => '0'
);
function "or" (left, right: t_uart_in_registers) return t_uart_in_registers;
......
modules/wishbone/wb_uart/simple_uart_wb.vhd
View file @ 3ca2f67c
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : simple_uart_wb.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Fri Dec 8 11:12:47 2023
-- Created : Fri Jan 26 16:35:06 2024
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
......@@ -45,6 +45,8 @@ signal uart_cr_rx_fifo_purge_dly0 : std_logic ;
signal uart_cr_rx_fifo_purge_int : std_logic ;
signal uart_cr_tx_fifo_purge_dly0 : std_logic ;
signal uart_cr_tx_fifo_purge_int : std_logic ;
signal uart_cr_rx_interrupt_enable_int : std_logic ;
signal uart_cr_tx_interrupt_enable_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -75,6 +77,8 @@ begin
host_rack_o <= '0';
uart_cr_rx_fifo_purge_int <= '0';
uart_cr_tx_fifo_purge_int <= '0';
uart_cr_rx_interrupt_enable_int <= '0';
uart_cr_tx_interrupt_enable_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -287,19 +291,19 @@ begin
if (wb_we_i = '1') then
uart_cr_rx_fifo_purge_int <= wrdata_reg(0);
uart_cr_tx_fifo_purge_int <= wrdata_reg(1);
uart_cr_rx_interrupt_enable_int <= wrdata_reg(8);
uart_cr_tx_interrupt_enable_int <= wrdata_reg(9);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(8) <= uart_cr_rx_interrupt_enable_int;
rddata_reg(9) <= uart_cr_tx_interrupt_enable_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
......@@ -389,6 +393,10 @@ begin
end process;
-- RX Interrupt enable
regs_o.cr_rx_interrupt_enable_o <= uart_cr_rx_interrupt_enable_int;
-- TX Interrupt enable
regs_o.cr_tx_interrupt_enable_o <= uart_cr_tx_interrupt_enable_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
wb_err_o <= '0';
......
modules/wishbone/wb_uart/simple_uart_wb.wb
View file @ 3ca2f67c
......@@ -240,7 +240,25 @@ peripheral {
prefix = "TX_FIFO_PURGE";
type = MONOSTABLE;
};
field {
name = "RX Interrupt enable";
description = "RX Interrupt Enable";
prefix = "RX_INTERRUPT_ENABLE";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "TX Interrupt enable";
description = "TX Interrupt Enable";
prefix = "TX_INTERRUPT_ENABLE";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
modules/wishbone/wb_uart/wb_simple_uart.vhd
View file @ 3ca2f67c
......@@ -125,6 +125,9 @@ architecture arch of wb_simple_uart is
signal tx_fifo_state : t_tx_fifo_state;
signal rx_fifo_state : t_rx_fifo_state;
signal s_rx_interrupt: std_logic;
signal s_tx_interrupt: std_logic;
signal rx_fifo_rdata : std_logic_vector(7 downto 0);
signal rx_fifo_wdata : std_logic_vector(7 downto 0);
begin -- arch
......@@ -370,7 +373,14 @@ begin -- arch
rx_fifo_rd <= '1' when rx_fifo_state = IDLE and rx_fifo_empty = '0' else '0';
-- Handling the interrupt for UART
s_rx_interrupt <= '1' when (regs_in.sr_rx_rdy_i = '1' and regs_out.cr_rx_interrupt_enable_o = '1') else '0';
s_tx_interrupt <= '1' when (tx_fifo_full = '0' and regs_out.cr_tx_interrupt_enable_o = '1') else '0';
int_o <= s_rx_interrupt or s_tx_interrupt;
regs_in.sr_tx_busy_i <= tx_fifo_full;
end generate gen_phys_fifos;
gen_phys_nofifos : if not g_WITH_PHYSICAL_UART_FIFO generate
......
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