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Platform-independent core collection
Commits
4273aed0
Commit
4273aed0
authored
Dec 20, 2023
by
Dimitris Lampridis
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Merge branch '48-fifo-minor-clearnup' into 'master'
Resolve "fifo: minor cleanup" See merge request
!56
parents
9ef0c76a
bce76ce6
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Showing
3 changed files
with
17 additions
and
79 deletions
+17
-79
inferred_async_fifo.vhd
modules/genrams/common/inferred_async_fifo.vhd
+13
-0
generic_async_fifo.vhd
modules/genrams/generic/generic_async_fifo.vhd
+3
-44
generic_sync_fifo.vhd
modules/genrams/generic/generic_sync_fifo.vhd
+1
-35
No files found.
modules/genrams/common/inferred_async_fifo.vhd
View file @
4273aed0
...
...
@@ -152,6 +152,7 @@ architecture syn of inferred_async_fifo is
begin
-- syn
-- Protect against overflow and underflow.
rd_int
<=
rd_i
and
not
empty_int
;
we_int
<=
we_i
and
not
full_int
;
...
...
@@ -167,9 +168,15 @@ begin -- syn
p_mem_read
:
process
(
clk_rd_i
)
begin
if
rising_edge
(
clk_rd_i
)
then
-- In show ahead mode, the output is valid (unless the fifo is empty), and 'rd'
-- ack the current value.
-- In no show ahead mode, the output is not valid, and 'rd' will output the value
-- on the next cycle.
if
(
rd_int
=
'1'
and
g_show_ahead
)
then
-- Read the next value.
q_int
<=
mem
(
to_integer
(
unsigned
(
rcb
.
bin_next
(
rcb
.
bin_next
'LEFT
-1
downto
0
))));
elsif
(
rd_int
=
'1'
or
g_show_ahead
)
then
-- Read the current entry.
q_int
<=
mem
(
to_integer
(
unsigned
(
rcb
.
bin
(
rcb
.
bin
'LEFT
-1
downto
0
))));
end
if
;
end
if
;
...
...
@@ -243,6 +250,8 @@ begin -- syn
end
if
;
end
process
p_gen_empty
;
-- Note: because of the synchronizer, wr_empty may not be fully accurate,
-- but this is usually ok (the writer shouldn't care).
gen_with_wr_empty
:
if
g_with_wr_empty
=
TRUE
generate
U_Sync_Empty
:
gc_sync_ffs
generic
map
(
...
...
@@ -254,6 +263,8 @@ begin -- syn
synced_o
=>
wr_empty_x
);
end
generate
gen_with_wr_empty
;
-- Likewise, because of the synchronizer the rd_full may not be fully
-- accurate.
gen_with_rd_full
:
if
g_with_rd_full
=
TRUE
generate
U_Sync_Full
:
gc_sync_ffs
generic
map
(
...
...
@@ -272,10 +283,12 @@ begin -- syn
begin
if
((
wcb
.
bin
(
wcb
.
bin
'LEFT
-1
downto
0
)
=
rcb
.
bin_x
(
rcb
.
bin_x
'LEFT
-1
downto
0
))
and
(
wcb
.
bin
(
wcb
.
bin
'LEFT
)
/=
rcb
.
bin_x
(
rcb
.
bin_x
'LEFT
)))
then
-- It's already full!
going_full
<=
'1'
;
elsif
(
we_int
=
'1'
and
(
wcb
.
bin_next
(
wcb
.
bin
'LEFT
-1
downto
0
)
=
rcb
.
bin_x
(
rcb
.
bin_x
'LEFT
-1
downto
0
))
and
(
wcb
.
bin_next
(
wcb
.
bin
'LEFT
)
/=
rcb
.
bin_x
(
rcb
.
bin_x
'LEFT
)))
then
-- Will probably be full (useless there is a read, but we are conservative)
going_full
<=
'1'
;
else
going_full
<=
'0'
;
...
...
modules/genrams/generic/generic_async_fifo.vhd
View file @
4273aed0
...
...
@@ -52,8 +52,8 @@ entity generic_async_fifo is
g_with_wr_almost_full
:
boolean
:
=
false
;
g_with_wr_count
:
boolean
:
=
false
;
g_almost_empty_threshold
:
integer
;
-- threshold for almost empty flag
g_almost_full_threshold
:
integer
;
-- threshold for almost full flag
g_almost_empty_threshold
:
integer
:
=
0
;
-- threshold for almost empty flag
g_almost_full_threshold
:
integer
:
=
0
;
-- threshold for almost full flag
g_memory_implementation_hint
:
string
:
=
"auto"
);
...
...
@@ -89,50 +89,9 @@ end generic_async_fifo;
architecture
syn
of
generic_async_fifo
is
component
inferred_async_fifo
generic
(
g_data_width
:
natural
;
g_size
:
natural
;
g_show_ahead
:
boolean
;
g_with_rd_empty
:
boolean
;
g_with_rd_full
:
boolean
;
g_with_rd_almost_empty
:
boolean
;
g_with_rd_almost_full
:
boolean
;
g_with_rd_count
:
boolean
;
g_with_wr_empty
:
boolean
;
g_with_wr_full
:
boolean
;
g_with_wr_almost_empty
:
boolean
;
g_with_wr_almost_full
:
boolean
;
g_with_wr_count
:
boolean
;
g_almost_empty_threshold
:
integer
;
g_almost_full_threshold
:
integer
;
g_memory_implementation_hint
:
string
);
port
(
rst_n_i
:
in
std_logic
:
=
'1'
;
clk_wr_i
:
in
std_logic
;
d_i
:
in
std_logic_vector
(
g_data_width
-1
downto
0
);
we_i
:
in
std_logic
;
wr_empty_o
:
out
std_logic
;
wr_full_o
:
out
std_logic
;
wr_almost_empty_o
:
out
std_logic
;
wr_almost_full_o
:
out
std_logic
;
wr_count_o
:
out
std_logic_vector
(
f_log2_size
(
g_size
)
-1
downto
0
);
clk_rd_i
:
in
std_logic
;
q_o
:
out
std_logic_vector
(
g_data_width
-1
downto
0
);
rd_i
:
in
std_logic
;
rd_empty_o
:
out
std_logic
;
rd_full_o
:
out
std_logic
;
rd_almost_empty_o
:
out
std_logic
;
rd_almost_full_o
:
out
std_logic
;
rd_count_o
:
out
std_logic_vector
(
f_log2_size
(
g_size
)
-1
downto
0
));
end
component
;
begin
-- syn
U_Inferred_FIFO
:
inferred_async_fifo
U_Inferred_FIFO
:
entity
work
.
inferred_async_fifo
generic
map
(
g_data_width
=>
g_data_width
,
g_size
=>
g_size
,
...
...
modules/genrams/generic/generic_sync_fifo.vhd
View file @
4273aed0
...
...
@@ -77,39 +77,8 @@ entity generic_sync_fifo is
end
generic_sync_fifo
;
architecture
syn
of
generic_sync_fifo
is
component
inferred_sync_fifo
generic
(
g_data_width
:
natural
;
g_size
:
natural
;
g_show_ahead
:
boolean
;
g_show_ahead_legacy_mode
:
boolean
;
g_with_empty
:
boolean
;
g_with_full
:
boolean
;
g_with_almost_empty
:
boolean
;
g_with_almost_full
:
boolean
;
g_with_count
:
boolean
;
g_almost_empty_threshold
:
integer
;
g_almost_full_threshold
:
integer
;
g_register_flag_outputs
:
boolean
;
g_memory_implementation_hint
:
string
);
port
(
rst_n_i
:
in
std_logic
:
=
'1'
;
clk_i
:
in
std_logic
;
d_i
:
in
std_logic_vector
(
g_data_width
-1
downto
0
);
we_i
:
in
std_logic
;
q_o
:
out
std_logic_vector
(
g_data_width
-1
downto
0
);
rd_i
:
in
std_logic
;
empty_o
:
out
std_logic
;
full_o
:
out
std_logic
;
almost_empty_o
:
out
std_logic
;
almost_full_o
:
out
std_logic
;
count_o
:
out
std_logic_vector
(
f_log2_size
(
g_size
)
-1
downto
0
));
end
component
;
begin
-- syn
U_Inferred_FIFO
:
inferred_sync_fifo
U_Inferred_FIFO
:
entity
work
.
inferred_sync_fifo
generic
map
(
g_data_width
=>
g_data_width
,
g_size
=>
g_size
,
...
...
@@ -136,7 +105,4 @@ begin -- syn
almost_empty_o
=>
almost_empty_o
,
almost_full_o
=>
almost_full_o
,
count_o
=>
count_o
);
end
syn
;
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