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Platform-independent core collection
Commit 67d353ad authored by Dimitris Lampridis's avatar Dimitris Lampridis
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common: reset cleanup for gc_frequency_meter

parent 66e128d0
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Showing with 19 additions and 29 deletions
modules/common/gc_frequency_meter.vhd
View file @ 67d353ad
...@@ -39,7 +39,7 @@ entity gc_frequency_meter is ...@@ -39,7 +39,7 @@ entity gc_frequency_meter is
port( port(
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
clk_in_i : in std_logic; clk_in_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic; -- not used, kept for backward compatibility
pps_p1_i : in std_logic; pps_p1_i : in std_logic;
freq_o : out std_logic_vector(g_counter_bits-1 downto 0); freq_o : out std_logic_vector(g_counter_bits-1 downto 0);
freq_valid_o : out std_logic freq_valid_o : out std_logic
...@@ -50,11 +50,11 @@ end gc_frequency_meter; ...@@ -50,11 +50,11 @@ end gc_frequency_meter;
architecture behavioral of gc_frequency_meter is architecture behavioral of gc_frequency_meter is
signal gate_pulse, gate_pulse_synced : std_logic; signal gate_pulse, gate_pulse_synced : std_logic := '0';
signal cntr_gate : unsigned(g_counter_bits-1 downto 0); signal cntr_gate : unsigned(g_counter_bits-1 downto 0) := (others => '0');
signal cntr_meas : unsigned(g_counter_bits-1 downto 0); signal cntr_meas : unsigned(g_counter_bits-1 downto 0) := (others => '0');
signal freq_reg : std_logic_vector(g_counter_bits-1 downto 0); signal freq_reg : std_logic_vector(g_counter_bits-1 downto 0) := (others => '0');
begin begin
...@@ -63,17 +63,12 @@ begin ...@@ -63,17 +63,12 @@ begin
p_gate_counter : process(clk_sys_i) p_gate_counter : process(clk_sys_i)
begin begin
if rising_edge(clk_sys_i) then if rising_edge(clk_sys_i) then
if rst_n_i = '0' then if(cntr_gate = g_clk_sys_freq-1) then
cntr_gate <= (others => '0'); cntr_gate <= (others => '0');
gate_pulse <= '0'; gate_pulse <= '1';
else else
if(cntr_gate = g_clk_sys_freq-1) then cntr_gate <= cntr_gate + 1;
cntr_gate <= (others => '0'); gate_pulse <= '0';
gate_pulse <= '1';
else
cntr_gate <= cntr_gate + 1;
gate_pulse <= '0';
end if;
end if; end if;
end if; end if;
end process; end process;
...@@ -82,7 +77,7 @@ begin ...@@ -82,7 +77,7 @@ begin
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_in_i, clk_out_i => clk_in_i,
rst_n_i => rst_n_i, rst_n_i => '1',
d_ready_o => freq_valid_o, d_ready_o => freq_valid_o,
d_p_i => gate_pulse, d_p_i => gate_pulse,
q_p_o => gate_pulse_synced); q_p_o => gate_pulse_synced);
...@@ -95,7 +90,7 @@ begin ...@@ -95,7 +90,7 @@ begin
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_in_i, clk_out_i => clk_in_i,
rst_n_i => rst_n_i, rst_n_i => '1',
d_ready_o => freq_valid_o, d_ready_o => freq_valid_o,
d_p_i => pps_p1_i, d_p_i => pps_p1_i,
q_p_o => gate_pulse_synced); q_p_o => gate_pulse_synced);
...@@ -105,10 +100,7 @@ begin ...@@ -105,10 +100,7 @@ begin
p_freq_counter : process (clk_in_i, rst_n_i) p_freq_counter : process (clk_in_i, rst_n_i)
begin begin
if rst_n_i = '0' then -- asynchronous reset (active low) if rising_edge(clk_in_i) then
cntr_meas <= (others => '0');
freq_reg <= (others => '0');
elsif rising_edge(clk_in_i) then
if(gate_pulse_synced = '1') then if(gate_pulse_synced = '1') then
freq_reg <= std_logic_vector(cntr_meas); freq_reg <= std_logic_vector(cntr_meas);
......
modules/common/gc_pulse_synchronizer2.vhd
View file @ 67d353ad
...@@ -49,9 +49,11 @@ end gc_pulse_synchronizer2; ...@@ -49,9 +49,11 @@ end gc_pulse_synchronizer2;
architecture rtl of gc_pulse_synchronizer2 is architecture rtl of gc_pulse_synchronizer2 is
signal ready, d_p_d0 : std_logic; signal ready : std_logic := '1';
signal in_ext, out_ext : std_logic; signal d_p_d0 : std_logic := '0';
signal out_feedback : std_logic; signal in_ext : std_logic := '0';
signal out_ext : std_logic := '0';
signal out_feedback : std_logic := '0';
begin -- rtl begin -- rtl
...@@ -73,13 +75,9 @@ begin -- rtl ...@@ -73,13 +75,9 @@ begin -- rtl
npulse_o => open, npulse_o => open,
ppulse_o => open); ppulse_o => open);
p_input_ack : process(clk_in_i, rst_in_n_i) p_input_ack : process(clk_in_i)
begin begin
if rst_in_n_i = '0' then if rising_edge(clk_in_i) then
ready <= '1';
in_ext <= '0';
d_p_d0 <= '0';
elsif rising_edge(clk_in_i) then
d_p_d0 <= d_p_i; d_p_d0 <= d_p_i;
......
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