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Platform-independent core collection
Commit a67a0f49 authored by Tristan Gingold's avatar Tristan Gingold
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Merge branch '41-fine_pulse_gen-tune-clocking' into 'master' 

Resolve "fine_pulse_gen: tune clocking"

See merge request !40
parents 4ff87a03 1820413e
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Showing with 41 additions and 34 deletions
modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintex7.vhd
View file @ a67a0f49
...@@ -20,7 +20,7 @@ entity fine_pulse_gen_kintex7 is ...@@ -20,7 +20,7 @@ entity fine_pulse_gen_kintex7 is
clk_serdes_i : in std_logic; clk_serdes_i : in std_logic;
rst_serdes_i : in std_logic; rst_serdes_i : in std_logic;
rst_sys_n_i : in std_logic; rst_par_n_i : in std_logic;
cont_i : in std_logic; cont_i : in std_logic;
pol_i : in std_logic; pol_i : in std_logic;
...@@ -44,7 +44,6 @@ architecture rtl of fine_pulse_gen_kintex7 is ...@@ -44,7 +44,6 @@ architecture rtl of fine_pulse_gen_kintex7 is
signal dout_predelay, dout_prebuf, dout_nodelay : std_logic; signal dout_predelay, dout_prebuf, dout_nodelay : std_logic;
signal odelay_load : std_logic; signal odelay_load : std_logic;
signal rst : std_logic;
signal odelay_ntaps : std_logic_vector(4 downto 0); signal odelay_ntaps : std_logic_vector(4 downto 0);
...@@ -76,16 +75,12 @@ architecture rtl of fine_pulse_gen_kintex7 is ...@@ -76,16 +75,12 @@ architecture rtl of fine_pulse_gen_kintex7 is
begin begin
rst <= not rst_sys_n_i; process(clk_par_i, rst_par_n_i)
process(clk_par_i, rst_sys_n_i)
variable rv, rv2 : std_logic_vector(15 downto 0); variable rv, rv2 : std_logic_vector(15 downto 0);
begin begin
if rst_sys_n_i = '0' then if rst_par_n_i = '0' then
pulse_pending <= '0'; pulse_pending <= '0';
dly_load_d <= '0'; --dly_load_d <= '0';
ready_o <= '0'; ready_o <= '0';
elsif rising_edge(clk_par_i) then elsif rising_edge(clk_par_i) then
......
modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd
View file @ a67a0f49
...@@ -161,89 +161,101 @@ begin ...@@ -161,89 +161,101 @@ begin
); );
U_Sync1: entity work.gc_pulse_synchronizer U_Sync1: entity work.gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_ref_i, clk_out_i => clk_ref_i,
rst_n_i => rst_sys_n_i, rst_in_n_i => rst_sys_n_i,
rst_out_n_i => rst_n_wr,
d_p_i => regs_out.csr_trig0, d_p_i => regs_out.csr_trig0,
q_p_o => ch(0).arm); q_p_o => ch(0).arm);
U_Sync2: entity work.gc_pulse_synchronizer U_Sync2: entity work.gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_ref_i, clk_out_i => clk_ref_i,
rst_n_i => rst_sys_n_i, rst_in_n_i => rst_sys_n_i,
rst_out_n_i => rst_n_wr,
d_p_i => regs_out.csr_trig1, d_p_i => regs_out.csr_trig1,
q_p_o => ch(1).arm); q_p_o => ch(1).arm);
U_Sync3: entity work.gc_pulse_synchronizer U_Sync3: entity work.gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_ref_i, clk_out_i => clk_ref_i,
rst_n_i => rst_sys_n_i, rst_in_n_i => rst_sys_n_i,
rst_out_n_i => rst_n_wr,
d_p_i => regs_out.csr_trig2, d_p_i => regs_out.csr_trig2,
q_p_o => ch(2).arm); q_p_o => ch(2).arm);
U_Sync4: entity work.gc_pulse_synchronizer U_Sync4: entity work.gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_ref_i, clk_out_i => clk_ref_i,
rst_n_i => rst_sys_n_i, rst_in_n_i => rst_sys_n_i,
rst_out_n_i => rst_n_wr,
d_p_i => regs_out.csr_trig3, d_p_i => regs_out.csr_trig3,
q_p_o => ch(3).arm); q_p_o => ch(3).arm);
U_Sync5: entity work.gc_pulse_synchronizer U_Sync5: entity work.gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_ref_i, clk_out_i => clk_ref_i,
rst_n_i => rst_sys_n_i, rst_in_n_i => rst_sys_n_i,
rst_out_n_i => rst_n_wr,
d_p_i => regs_out.csr_trig4, d_p_i => regs_out.csr_trig4,
q_p_o => ch(4).arm); q_p_o => ch(4).arm);
U_Sync6: entity work.gc_pulse_synchronizer U_Sync6: entity work.gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_ref_i, clk_out_i => clk_ref_i,
rst_n_i => rst_sys_n_i, rst_in_n_i => rst_sys_n_i,
rst_out_n_i => rst_n_wr,
d_p_i => regs_out.csr_trig5, d_p_i => regs_out.csr_trig5,
q_p_o => ch(5).arm); q_p_o => ch(5).arm);
U_Sync71: entity work.gc_pulse_synchronizer U_Sync71: entity work.gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_ref_i, clk_out_i => clk_ref_i,
rst_n_i => rst_sys_n_i, rst_in_n_i => rst_sys_n_i,
rst_out_n_i => rst_n_wr,
d_p_i => regs_out.csr_force0, d_p_i => regs_out.csr_force0,
q_p_o => ch(0).force_tr); q_p_o => ch(0).force_tr);
U_Sync72: entity work.gc_pulse_synchronizer U_Sync72: entity work.gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_ref_i, clk_out_i => clk_ref_i,
rst_n_i => rst_sys_n_i, rst_in_n_i => rst_sys_n_i,
rst_out_n_i => rst_n_wr,
d_p_i => regs_out.csr_force1, d_p_i => regs_out.csr_force1,
q_p_o => ch(1).force_tr); q_p_o => ch(1).force_tr);
U_Sync73: entity work.gc_pulse_synchronizer U_Sync73: entity work.gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_ref_i, clk_out_i => clk_ref_i,
rst_n_i => rst_sys_n_i, rst_in_n_i => rst_sys_n_i,
rst_out_n_i => rst_n_wr,
d_p_i => regs_out.csr_force2, d_p_i => regs_out.csr_force2,
q_p_o => ch(2).force_tr); q_p_o => ch(2).force_tr);
U_Sync74: entity work.gc_pulse_synchronizer U_Sync74: entity work.gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_ref_i, clk_out_i => clk_ref_i,
rst_n_i => rst_sys_n_i, rst_in_n_i => rst_sys_n_i,
rst_out_n_i => rst_n_wr,
d_p_i => regs_out.csr_force3, d_p_i => regs_out.csr_force3,
q_p_o => ch(3).force_tr); q_p_o => ch(3).force_tr);
U_Sync75: entity work.gc_pulse_synchronizer U_Sync75: entity work.gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_ref_i, clk_out_i => clk_ref_i,
rst_n_i => rst_sys_n_i, rst_in_n_i => rst_sys_n_i,
rst_out_n_i => rst_n_wr,
d_p_i => regs_out.csr_force4, d_p_i => regs_out.csr_force4,
q_p_o => ch(4).force_tr); q_p_o => ch(4).force_tr);
U_Sync76: entity work.gc_pulse_synchronizer U_Sync76: entity work.gc_pulse_synchronizer2
port map ( port map (
clk_in_i => clk_sys_i, clk_in_i => clk_sys_i,
clk_out_i => clk_ref_i, clk_out_i => clk_ref_i,
rst_n_i => rst_sys_n_i, rst_in_n_i => rst_sys_n_i,
rst_out_n_i => rst_n_wr,
d_p_i => regs_out.csr_force5, d_p_i => regs_out.csr_force5,
q_p_o => ch(5).force_tr); q_p_o => ch(5).force_tr);
...@@ -410,7 +422,7 @@ begin ...@@ -410,7 +422,7 @@ begin
clk_par_i => clk_par, clk_par_i => clk_par,
clk_serdes_i => clk_ser, clk_serdes_i => clk_ser,
rst_serdes_i => rst_serdes, rst_serdes_i => rst_serdes,
rst_sys_n_i => rst_sys_n_i, rst_par_n_i => rst_n_wr,
trig_p_i => ch(I).trig_p, trig_p_i => ch(I).trig_p,
cont_i => ch(i).cont, cont_i => ch(i).cont,
coarse_i => ch(I).coarse, coarse_i => ch(I).coarse,
......
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