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Dimitris Lampridis authored
The previous implementation was introducing latches to the GN4124 core under Xilinx ISE. Tested and verified to work with the following SPEC-based reference designs: - WR - MT - WRTD
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altera | ||
common | ||
generic | ||
xilinx | ||
.gitignore | ||
Manifest.py | ||
genram_pkg.vhd | ||
memory_loader_pkg.vhd |