minor modifications to help with meeting timing

6a6e3589 · Dimitris Lampridis · b5752886 · 6a6e3589 · 6a6e3589 · 6a6e3589
Commit 6a6e3589 authored May 06, 2019 by Dimitris Lampridis
Showing with 34 additions and 14 deletions

gn4124_core.vhd hdl/gn4124core/rtl/spartan6/gn4124_core.vhd +11 -6

p2l_des.vhd hdl/gn4124core/rtl/spartan6/p2l_des.vhd +22 -7

wbmaster32.vhd hdl/gn4124core/rtl/wbmaster32.vhd +1 -1

No files found.
--- a/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
+++ b/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
@@ -147,6 +147,7 @@ architecture rtl of gn4124_core is
  signal io_clk         : std_logic;
  signal serdes_strobe  : std_logic;
  signal p2l_pll_locked : std_logic;
+  signal arst_logic_in  : std_logic;

  attribute keep                 : string;
  attribute keep of sys_clk : signal is "TRUE";
@@ -324,18 +325,22 @@ begin
      bitslip         => open,
      reset           => arst_pll,
      datain          => open,
-      rx_bufpll_lckd  => p2l_pll_locked) ;
+      rx_bufpll_lckd  => p2l_pll_locked);

  ------------------------------------------------------------------------------
  -- Reset aligned to core clock
  ------------------------------------------------------------------------------

-  cmp_core_rst_sync: gc_sync_ffs
+  arst_logic_in <= not p2l_pll_locked;
+
+  cmp_core_rst_sync : gc_reset_multi_aasd
+    generic map (
+      g_CLOCKS  => 1,
+      g_RST_LEN => 16)
    port map (
-      clk_i    => sys_clk,
-      rst_n_i  => rst_n_a_i,
-      data_i   => p2l_pll_locked,
-      synced_o => sys_rst_n);
+      arst_i     => arst_logic_in,
+      clks_i(0)  => sys_clk,
+      rst_n_o(0) => sys_rst_n);

  -- Always active high reset for PLL and SERDES
  arst_pll <= not(rst_n_a_i);

--- a/hdl/gn4124core/rtl/spartan6/p2l_des.vhd
+++ b/hdl/gn4124core/rtl/spartan6/p2l_des.vhd
@@ -97,12 +97,15 @@ architecture rtl of p2l_des is
  -----------------------------------------------------------------------------

  -- SDR signals
-  signal p2l_valid_t   : std_logic_vector(1 downto 0) := (others => '0');
-  signal p2l_dframe_t  : std_logic_vector(1 downto 0) := (others => '0');
+  signal p2l_data_t   : std_logic_vector(31 downto 0) := (others => '0');
+  signal p2l_data_d   : std_logic_vector(31 downto 0) := (others => '0');
+  signal p2l_dframe_t : std_logic_vector(1 downto 0)  := (others => '0');
+  signal p2l_dframe_d : std_logic                     := '0';
+  signal p2l_valid_t  : std_logic_vector(1 downto 0)  := (others => '0');
+  signal p2l_valid_d  : std_logic                     := '0';

 begin

-
  ------------------------------------------------------------------------------
  -- data inputs
  ------------------------------------------------------------------------------
@@ -119,7 +122,7 @@ begin
      gclk               => sys_clk_i,
      bitslip            => '0',
      reset              => rst_a_i,
-      data_out           => p2l_data_o,
+      data_out           => p2l_data_t,
      debug_in           => "00",
      debug              => open);

@@ -143,8 +146,6 @@ begin
      debug_in           => "00",
      debug              => open);

-  p2l_dframe_o <= p2l_dframe_t(0);
-
  ------------------------------------------------------------------------------
  -- valid input
  ------------------------------------------------------------------------------
@@ -165,6 +166,20 @@ begin
      debug_in           => "00",
      debug              => open);

-  p2l_valid_o <= p2l_valid_t(0);
+  ------------------------------------------------------------------------------
+  -- register module outputs to help with timing
+  ------------------------------------------------------------------------------
+  p_p2l_reg_out : process (sys_clk_i) is
+  begin
+    if rising_edge(sys_clk_i) then
+      p2l_data_d   <= p2l_data_t;
+      p2l_dframe_d <= p2l_dframe_t(0);
+      p2l_valid_d  <= p2l_valid_t(0);
+    end if;
+  end process p_p2l_reg_out;
+
+  p2l_data_o   <= p2l_data_d;
+  p2l_dframe_o <= p2l_dframe_d;
+  p2l_valid_o  <= p2l_valid_d;

 end rtl;
--- a/hdl/gn4124core/rtl/wbmaster32.vhd
+++ b/hdl/gn4124core/rtl/wbmaster32.vhd
@@ -149,7 +149,7 @@ architecture behaviour of wbmaster32 is
  signal wb_we_t    : std_logic;
  signal wb_sel_t   : std_logic_vector(3 downto 0) := (others => '0');
  signal wb_stall_t : std_logic;
-  signal wb_cid_t : std_logic_vector(1 downto 0);
+  signal wb_cid_t   : std_logic_vector(1 downto 0) := (others => '0');

  signal wb_ack_timeout_cnt : unsigned(log2_ceil(g_ACK_TIMEOUT)-1 downto 0);
  signal wb_ack_timeout     : std_logic;