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Cycle Analytics
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Hdlmake
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cc56877a5ee04a537395eaec9ed220a577ea191a
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hdl-make
tests
counter
sim
modelsim
verilog
Manifest.py
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Simple 8-bit counter test for syn/sim, VHDL/Verilog
· cc56877a
garcialasheras
authored
Sep 16, 2014
cc56877a
Manifest.py
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