Use generics in VHDL counter test to select sim and syn dividers

03047436 · Javier D. Garcia-Lasheras · 7feedf4d · 03047436 · 03047436
Commit 03047436 authored Mar 10, 2017 by Javier D. Garcia-Lasheras
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Showing with 7 additions and 2 deletions

counter.vhd tests/counter/modules/counter/vhdl/counter.vhd +1 -1

counter_tb.vhd tests/counter/testbench/counter_tb/vhdl/counter_tb.vhd +6 -1

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--- a/tests/counter/modules/counter/vhdl/counter.vhd
+++ b/tests/counter/modules/counter/vhdl/counter.vhd
@@ -11,7 +11,7 @@ use ieee.numeric_std.all;
 entity counter is
-generic (cycles_per_second : unsigned := 12000000);
+generic (cycles_per_second : integer := 12000000);
 port(	
    clock:  in std_logic;

--- a/tests/counter/testbench/counter_tb/vhdl/counter_tb.vhd
+++ b/tests/counter/testbench/counter_tb/vhdl/counter_tb.vhd
@@ -14,6 +14,9 @@ end counter_tb;
 architecture testbench of counter_tb is
    component counter
+    generic(
+	    cycles_per_second: integer
+    );
    port(   
 	    clock:	in std_logic;
 	    clear:	in std_logic;
@@ -29,7 +32,9 @@ architecture testbench of counter_tb is
 begin
-    U_counter: counter port map (t_clock, t_clear, t_count, t_Q);
+    U_counter: counter
+        generic map (cycles_per_second => 500)
+        port map (t_clock, t_clear, t_count, t_Q);
    process				 
    begin