Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
H
Hdlmake
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
15
Issues
15
List
Board
Labels
Milestones
Merge Requests
4
Merge Requests
4
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Hdlmake
Commits
11db146e
Commit
11db146e
authored
Mar 18, 2017
by
Javier D. Garcia-Lasheras
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Add support for Xilinx ISE using the multi-shell approach
parent
6118ee24
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
32 additions
and
24 deletions
+32
-24
ise.py
hdlmake/tools/ise.py
+24
-22
make_syn.py
hdlmake/tools/make_syn.py
+8
-2
No files found.
hdlmake/tools/ise.py
View file @
11db146e
...
...
@@ -62,14 +62,14 @@ class ToolISE(ToolSyn):
'synopsys'
,
'unimacro'
,
'unisim'
,
'XilinxCoreLib'
]
SUPPORTED_FILES
=
{
UCFFile
:
'xfile add $
$filename
'
,
CDCFile
:
'xfile add $
$filename
'
,
NGCFile
:
'xfile add $
$filename
'
}
UCFFile
:
'xfile add $
(sourcefile)
'
,
CDCFile
:
'xfile add $
(sourcefile)
'
,
NGCFile
:
'xfile add $
(sourcefile)
'
}
HDL_FILES
=
{
VHDLFile
:
'xfile add $
$filename
'
,
VerilogFile
:
'xfile add $
$filename
'
,
SVFile
:
'xfile add $
$filename
'
}
VHDLFile
:
'xfile add $
(sourcefile)
'
,
VerilogFile
:
'xfile add $
(sourcefile)
'
,
SVFile
:
'xfile add $
(sourcefile)
'
}
CLEAN_TARGETS
=
{
'clean'
:
[
"xst xlnx_auto_*_xdb"
,
"iseconfig _xmsgs"
,
"_ngo"
,
"*.b"
,
"*_summary.html"
,
"*.tcl"
,
...
...
@@ -90,11 +90,10 @@ class ToolISE(ToolSyn):
_ISE_RUN
=
'''
\
$(TCL_OPEN)
set process {{{0}}}
process run $$process
set result [process get $$process status]
if {{ $$result == "errors" }} {{
puts "$$process failed"
set process {{"{0}"}}
process run '$$'process
set result [process get '$$'process status]
if {{ '$$'result ==
\\
"errors
\\
" }} {{
exit 1
}}
$(TCL_SAVE)
...
...
@@ -106,7 +105,7 @@ $(TCL_CLOSE)'''
'save'
:
'project save'
,
'close'
:
'project close'
,
'project'
:
'$(TCL_CREATE)
\n
'
'
$(TCL_FILES)
\n
'
'
source files.tcl
\n
'
'{0}
\n
'
'project set top $(TOP_MODULE)
\n
'
'$(TCL_SAVE)
\n
'
...
...
@@ -127,11 +126,8 @@ $(TCL_CLOSE)'''
self
.
_clean_targets
.
update
(
ToolISE
.
CLEAN_TARGETS
)
self
.
_tcl_controls
.
update
(
ToolISE
.
TCL_CONTROLS
)
def
makefile_syn_tcl
(
self
):
"""Create a Xilinx synthesis project by TCL"""
syn_device
=
self
.
manifest_dict
[
"syn_device"
]
syn_grade
=
self
.
manifest_dict
[
"syn_grade"
]
syn_package
=
self
.
manifest_dict
[
"syn_package"
]
def
makefile_syn_top
(
self
):
"""Create the top part of the synthesis Makefile for ISE"""
syn_family
=
self
.
manifest_dict
.
get
(
"syn_family"
,
None
)
if
syn_family
is
None
:
syn_family
=
FAMILY_NAMES
.
get
(
...
...
@@ -141,15 +137,21 @@ $(TCL_CLOSE)'''
"syn_family is not defined in Manifest.py"
" and can not be guessed!"
)
quit
(
-
1
)
self
.
manifest_dict
[
"syn_family"
]
=
syn_family
super
(
ToolISE
,
self
)
.
makefile_syn_top
()
def
makefile_syn_tcl
(
self
):
"""Create a Xilinx synthesis project by TCL"""
syn_properties
=
self
.
manifest_dict
.
get
(
"syn_properties"
)
project_new
=
[]
project_tcl
=
self
.
_tcl_controls
[
"project"
]
tmp
=
'project set
"{0}" "{1}
"'
tmp
=
'project set
\\
"{0}
\\
"
\\
"{1}
\\
"'
properties
=
[
[
'family'
,
syn_family
],
[
'device'
,
syn_device
],
[
'package'
,
syn_package
],
[
'speed'
,
syn_grade
],
[
'family'
,
'$(SYN_FAMILY)'
],
[
'device'
,
'$(SYN_DEVICE)'
],
[
'package'
,
'$(SYN_PACKAGE)'
],
[
'speed'
,
'$(SYN_GRADE)'
],
[
'Manual Implementation Compile Order'
,
'false'
],
[
'Auto Implementation Top'
,
'false'
],
[
'Create Binary Configuration File'
,
'true'
]]
...
...
hdlmake/tools/make_syn.py
View file @
11db146e
...
...
@@ -87,6 +87,7 @@ ifneq ($$(strip $$(TOOL_PATH)),)
TCL_INTERPRETER := $$(TOOL_PATH)/$$(TCL_INTERPRETER)
endif
SYN_FAMILY := ${syn_family}
SYN_DEVICE := ${syn_device}
SYN_PACKAGE := ${syn_package}
SYN_GRADE := ${syn_grade}
...
...
@@ -96,6 +97,7 @@ SYN_GRADE := ${syn_grade}
project_name
=
os
.
path
.
splitext
(
self
.
manifest_dict
[
"syn_project"
])[
0
],
project_ext
=
self
.
_tool_info
[
"project_ext"
],
syn_family
=
self
.
manifest_dict
[
"syn_family"
],
syn_device
=
self
.
manifest_dict
[
"syn_device"
],
syn_package
=
self
.
manifest_dict
[
"syn_package"
],
syn_grade
=
self
.
manifest_dict
[
"syn_grade"
],
...
...
@@ -104,7 +106,11 @@ SYN_GRADE := ${syn_grade}
def
makefile_syn_tcl
(
self
):
"""Create the Makefile TCL dictionary for the selected tool"""
pass
command_list
=
[
"create"
,
"open"
,
"save"
,
"close"
]
for
command
in
command_list
:
if
command
in
self
.
_tcl_controls
:
self
.
writeln
(
'TCL_{1} := {0}'
.
format
(
self
.
_tcl_controls
[
command
],
command
.
upper
()))
self
.
writeln
()
def
makefile_syn_files
(
self
):
"""Write the files TCL section of the Makefile"""
...
...
@@ -143,7 +149,7 @@ SYN_GRADE := ${syn_grade}
"map"
,
"par"
,
"bitstream"
]
for
stage
in
stage_list
:
if
stage
in
self
.
_tcl_controls
:
echo_command
=
'
\t\t
echo
"{0}"
>> $@'
echo_command
=
'
\t\t
echo
{0}
>> $@'
tcl_command
=
[]
for
command
in
self
.
_tcl_controls
[
stage
]
.
split
(
'
\n
'
):
tcl_command
.
append
(
echo_command
.
format
(
command
))
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment