Add a test for previous commit.

11ebf1d0 · Tristan Gingold · c8be2839 · 11ebf1d0 · 11ebf1d0 · 11ebf1d0
Commit 11ebf1d0 authored Mar 02, 2020 by Tristan Gingold
5 changed files
--- a/testsuite/099vlog_parser/Makefile.ref
+++ b/testsuite/099vlog_parser/Makefile.ref
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+TOP_MODULE := gate
+
+MODELSIM_INI_PATH := ../linux_fakebin/..
+
+VCOM_FLAGS := -quiet -modelsimini modelsim.ini 
+VSIM_FLAGS := 
+VLOG_FLAGS := -quiet -modelsimini modelsim.ini 
+VMAP_FLAGS := -modelsimini modelsim.ini 
+#target for performing local simulation
+local: sim_pre_cmd simulation sim_post_cmd
+
+VERILOG_SRC := vlog.sv \
+
+VERILOG_OBJ := work/hdlmake/vlog_sv \
+
+VHDL_SRC := 
+VHDL_OBJ := 
+INCLUDE_DIRS :=
+LIBS := work
+LIB_IND := work/hdlmake/work-stamp
+
+simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
+$(VERILOG_OBJ): modelsim.ini
+$(VHDL_OBJ): $(LIB_IND) modelsim.ini
+
+modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
+		cp $< . 2>&1
+
+work/hdlmake/work-stamp:
+	(vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
+
+work/hdlmake/vlog_sv: vlog.sv
+		vlog -work work $(VLOG_FLAGS) -sv $(INCLUDE_DIRS) $<
+		@touch $@
+
+# USER SIM COMMANDS
+sim_pre_cmd:
+		
+sim_post_cmd:
+		
+
+CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
+
+clean:
+		rm -rf $(CLEAN_TARGETS)
+mrproper: clean
+		rm -rf *.vcd *.wlf
+
+.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
--- a/testsuite/099vlog_parser/Manifest.py
+++ b/testsuite/099vlog_parser/Manifest.py
+action = "simulation"
+
+sim_tool="modelsim"
+
+top_module = "gate"
+
+files = [ "vlog.sv", "gate1.v" ]
--- a/testsuite/099vlog_parser/gate1.v
+++ b/testsuite/099vlog_parser/gate1.v
+
+
+module gate3(input a);
+endmodule
--- a/testsuite/099vlog_parser/vlog.sv
+++ b/testsuite/099vlog_parser/vlog.sv
+module gate1(input a);
+endmodule
+
+module gate(input a);
+endmodule
+
+module gate2(input a);
+   gate1 g(a);
+endmodule
--- a/testsuite/test_all.py
+++ b/testsuite/test_all.py
@@ -268,12 +268,15 @@ def test_err_fetch():
 def test_xci():
    run_compare(path="023xci")

-def test_vlog_parser():
+def test_vlog_parser024():
    run_compare(path="024vlog_parser")

 def test_vlog_parser025():
    run_compare(path="025vlog_parser")

+def test_vlog_parser099():
+    run_compare(path="099vlog_parser")
+
 def test_gitsm_fetch026():
    with Config(path="026gitsm_fetch") as _:
        hdlmake.main.hdlmake(['fetch'])