Reformating, remove useless code.

125a66cd · Tristan Gingold · 262ba412 · 125a66cd
Commit 125a66cd authored Jun 07, 2019 by Tristan Gingold
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Showing with 16 additions and 20 deletions

vlog_parser.py hdlmake/vlog_parser.py +16 -20

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--- a/hdlmake/vlog_parser.py
+++ b/hdlmake/vlog_parser.py
@@ -238,9 +238,7 @@ class VerilogPreprocessor(object):
                    line = self._preprocess_file(
                        file_content=open(included_file_path, "r").read(),
                        file_name=included_file_path, library=library)
-                    self.vpp_filedeps[
-                        file_name +
-                        library].append(
+                    self.vpp_filedeps[file_name + library].append(
                        included_file_path)
                    # add the whole include chain to the dependencies of the
                    # currently parsed file
@@ -544,21 +542,18 @@ class VerilogParser(DepParser):
        logging.debug("Parsing %s", dep_file.path)
        # assert isinstance(dep_file, DepFile), print("unexpected type: " +
        # str(type(dep_file)))
+
+        # Preprocess the file and add included files as dependencies
        buf = self.preprocessor.preprocess(dep_file)
-        self.preprocessed = buf[:]
-        # add includes as dependencies
-        try:
-            includes = self.preprocessor.vpp_filedeps[
-                dep_file.path + dep_file.library]
-            for file_aux in includes:
-                dep_file.depends_on.add(
-                    create_source_file(path=file_aux,
-                                       module=dep_file.module,
-                                       is_include=True))
-            logging.debug("%s has %d includes.",
-                          str(dep_file), len(includes))
-        except KeyError:
-            logging.debug(str(dep_file) + " has no includes.")
+        includes = self.preprocessor.vpp_filedeps[
+            dep_file.path + dep_file.library]
+        for file_aux in includes:
+            dep_file.depends_on.add(
+                create_source_file(path=file_aux,
+                                   module=dep_file.module,
+                                   is_include=True))
+        logging.debug("%s has %d includes.", str(dep_file), len(includes))
+
        # look for packages used inside in file
        # it may generate false dependencies as package in SV can be used by:
        #    import my_package::*;
@@ -598,7 +593,8 @@ class VerilogParser(DepParser):
                DepRelation("%s.%s" % (dep_file.library, text.group(1)),
                            DepRelation.PROVIDE, DepRelation.PACKAGE))
        re.subn(m_inside_package, do_package, buf)
-        # modules and instatniations
+
+        # modules and instantiations
        m_inside_module = re.compile(
            r"(?:module|interface)\s+(\w+)\s*(?:\(.*?\))?\s*(.+?)"
            r"(?:endmodule|endinterface)",
@@ -627,9 +623,9 @@ class VerilogParser(DepParser):
                if mod_name in self.reserved_words:
                    return
                logging.debug("-> instantiates %s.%s as %s",
-                              dep_file.library, text.group(1), text.group(2))
+                              dep_file.library, mod_name, text.group(2))
                dep_file.add_relation(
-                    DepRelation("%s.%s" % (dep_file.library, text.group(1)),
+                    DepRelation("%s.%s" % (dep_file.library, mod_name),
                                DepRelation.USE, DepRelation.MODULE))
            re.subn(m_instantiation, do_inst, text.group(2))
        re.subn(m_inside_module, do_module, buf)