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Hdlmake
Commit 192361cf authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Remove unused simulation property from Vivado and PlanAhead

parent e8eed273
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hdlmake/tools/planahead.py
View file @ 192361cf
...@@ -89,7 +89,6 @@ class ToolPlanAhead(ActionMakefile): ...@@ -89,7 +89,6 @@ class ToolPlanAhead(ActionMakefile):
properties = [ properties = [
['part', syn_device + syn_package + syn_grade, 'current_project'], ['part', syn_device + syn_package + syn_grade, 'current_project'],
['target_language', 'VHDL', 'current_project'], ['target_language', 'VHDL', 'current_project'],
['ng.output_hdl_format', 'VHDL', 'get_filesets sim_1'],
['top', syn_top, 'get_property srcset [current_run]']] ['top', syn_top, 'get_property srcset [current_run]']]
for prop in properties: for prop in properties:
create_new.append(tmp.format(prop[0], prop[1], prop[2])) create_new.append(tmp.format(prop[0], prop[1], prop[2]))
......
hdlmake/tools/vivado.py
View file @ 192361cf
...@@ -98,7 +98,6 @@ class ToolVivado(ActionMakefile): ...@@ -98,7 +98,6 @@ class ToolVivado(ActionMakefile):
properties = [ properties = [
['part', syn_device + syn_package + syn_grade, 'current_project'], ['part', syn_device + syn_package + syn_grade, 'current_project'],
['target_language', 'VHDL', 'current_project'], ['target_language', 'VHDL', 'current_project'],
['ng.output_hdl_format', 'VHDL', 'get_filesets sim_1'],
['top', syn_top, 'get_property srcset [current_run]']] ['top', syn_top, 'get_property srcset [current_run]']]
for prop in properties: for prop in properties:
create_new.append(tmp.format(prop[0], prop[1], prop[2])) create_new.append(tmp.format(prop[0], prop[1], prop[2]))
......
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