Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
H
Hdlmake
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
15
Issues
15
List
Board
Labels
Milestones
Merge Requests
4
Merge Requests
4
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Hdlmake
Commits
1a8d6db9
Commit
1a8d6db9
authored
Aug 28, 2023
by
Benny Simonsen
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Package body in separate file not in dependencies, Test 126 FAIL
parent
0a1ec8c5
Show whitespace changes
Inline
Side-by-side
Showing
6 changed files
with
101 additions
and
0 deletions
+101
-0
Makefile.ref
testsuite/126package_body_in_separate_file/Makefile.ref
+69
-0
Manifest.py
testsuite/126package_body_in_separate_file/Manifest.py
+7
-0
gate5.vhdl
testsuite/files/gate5.vhdl
+16
-0
pkg5.vhdl
testsuite/files/pkg5.vhdl
+3
-0
pkg5_body.vhdl
testsuite/files/pkg5_body.vhdl
+3
-0
test_all.py
testsuite/test_all.py
+3
-0
No files found.
testsuite/126package_body_in_separate_file/Makefile.ref
0 → 100644
View file @
1a8d6db9
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE
:=
gate5
MODELSIM_INI_PATH
:=
../linux_fakebin/..
VCOM_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VSIM_FLAGS
:=
VLOG_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VMAP_FLAGS
:=
-modelsimini
modelsim.ini
#target for performing local simulation
local
:
sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC
:=
VERILOG_OBJ
:=
VHDL_SRC
:=
../files/gate5.vhdl
\
../files/pkg5.vhdl
\
../files/pkg5_body.vhdl
\
VHDL_OBJ
:=
work/hdlmake/gate5_vhdl
\
work/hdlmake/pkg5_vhdl
\
work/hdlmake/pkg5_body_vhdl
\
INCLUDE_DIRS
:=
LIBS
:=
work
LIB_IND
:=
work/hdlmake/work-stamp
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/hdlmake/work-stamp
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
mkdir
-p
work/hdlmake
&&
touch
work/hdlmake/work-stamp
)
||
rm
-rf
work
work/hdlmake/gate5_vhdl
:
../files/gate5.vhdl
\
work/hdlmake/pkg5_vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
@
touch
$@
work/hdlmake/pkg5_vhdl
:
../files/pkg5.vhdl
\
work/hdlmake/pkg5_body_vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
@
touch
$@
work/hdlmake/pkg5_body_vhdl
:
../files/pkg5_body.vhdl
\
work/hdlmake/pkg5_vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
@
touch
$@
# USER SIM COMMANDS
sim_pre_cmd
:
sim_post_cmd
:
CLEAN_TARGETS
:=
$(LIBS)
modelsim.ini transcript
clean
:
rm
-rf
$(CLEAN_TARGETS)
mrproper
:
clean
rm
-rf
*
.vcd
*
.wlf
.PHONY
:
mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/126package_body_in_separate_file/Manifest.py
0 → 100644
View file @
1a8d6db9
action
=
"simulation"
sim_tool
=
"modelsim"
top_module
=
"gate5"
files
=
[
"../files/gate5.vhdl"
,
"../files/pkg5.vhdl"
,
"../files/pkg5_body.vhdl"
]
testsuite/files/gate5.vhdl
0 → 100644
View file @
1a8d6db9
entity
gate5
is
port
(
i
:
in
bit
;
o
:
out
bit
);
end
gate5
;
library
work
;
use
work
.
pkg5
.
all
;
architecture
behav
of
gate5
is
begin
if
c_invert
then
o
<=
not
i
;
else
o
<=
i
;
end
behav
;
testsuite/files/pkg5.vhdl
0 → 100644
View file @
1a8d6db9
package
pkg5
is
constant
c_invert
:
boolean
;
end
package
pkg5
;
testsuite/files/pkg5_body.vhdl
0 → 100644
View file @
1a8d6db9
package
body
pkg5
is
constant
c_invert
:
boolean
:
=
true
;
end
package
body
pkg5
;
testsuite/test_all.py
View file @
1a8d6db9
...
...
@@ -589,6 +589,9 @@ def test_explicit_required_lib_124():
def
test_arch_in_separate_file_125
():
run_compare
(
path
=
"125arch_in_separate_file"
)
def
test_package_body_in_separate_file_126
():
run_compare
(
path
=
"126package_body_in_separate_file"
)
@
pytest
.
mark
.
xfail
def
test_xfail
():
"""This is a self-consistency test: the test is known to fail"""
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment