Package body in separate file not in dependencies, Test 126 FAIL

1a8d6db9 · Benny Simonsen · 0a1ec8c5 · 1a8d6db9 · 1a8d6db9 · 1a8d6db9
Commit 1a8d6db9 authored Aug 28, 2023 by Benny Simonsen
6 changed files
--- a/testsuite/126package_body_in_separate_file/Makefile.ref
+++ b/testsuite/126package_body_in_separate_file/Makefile.ref
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+TOP_MODULE := gate5
+
+MODELSIM_INI_PATH := ../linux_fakebin/..
+
+VCOM_FLAGS := -quiet -modelsimini modelsim.ini 
+VSIM_FLAGS := 
+VLOG_FLAGS := -quiet -modelsimini modelsim.ini 
+VMAP_FLAGS := -modelsimini modelsim.ini 
+#target for performing local simulation
+local: sim_pre_cmd simulation sim_post_cmd
+
+VERILOG_SRC := 
+VERILOG_OBJ := 
+VHDL_SRC := ../files/gate5.vhdl \
+../files/pkg5.vhdl \
+../files/pkg5_body.vhdl \
+
+VHDL_OBJ := work/hdlmake/gate5_vhdl \
+work/hdlmake/pkg5_vhdl \
+work/hdlmake/pkg5_body_vhdl \
+
+INCLUDE_DIRS :=
+LIBS := work
+LIB_IND := work/hdlmake/work-stamp
+
+simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
+$(VERILOG_OBJ): modelsim.ini
+$(VHDL_OBJ): $(LIB_IND) modelsim.ini
+
+modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
+		cp $< . 2>&1
+
+work/hdlmake/work-stamp:
+	(vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
+
+work/hdlmake/gate5_vhdl: ../files/gate5.vhdl \
+work/hdlmake/pkg5_vhdl
+		vcom $(VCOM_FLAGS) -work work $< 
+		@touch $@
+
+work/hdlmake/pkg5_vhdl: ../files/pkg5.vhdl \
+work/hdlmake/pkg5_body_vhdl
+		vcom $(VCOM_FLAGS) -work work $< 
+		@touch $@
+
+work/hdlmake/pkg5_body_vhdl: ../files/pkg5_body.vhdl \
+work/hdlmake/pkg5_vhdl
+		vcom $(VCOM_FLAGS) -work work $< 
+		@touch $@
+
+# USER SIM COMMANDS
+sim_pre_cmd:
+		
+sim_post_cmd:
+		
+
+CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
+
+clean:
+		rm -rf $(CLEAN_TARGETS)
+mrproper: clean
+		rm -rf *.vcd *.wlf
+
+.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
--- a/testsuite/126package_body_in_separate_file/Manifest.py
+++ b/testsuite/126package_body_in_separate_file/Manifest.py
+action = "simulation"
+
+sim_tool="modelsim"
+
+top_module = "gate5"
+
+files = [ "../files/gate5.vhdl", "../files/pkg5.vhdl" , "../files/pkg5_body.vhdl" ]
--- a/testsuite/files/gate5.vhdl
+++ b/testsuite/files/gate5.vhdl
+entity gate5 is
+  port (i : in bit;
+        o : out bit);
+end gate5;
+
+library work;
+use work.pkg5.all;
+
+architecture behav of gate5 is
+begin
+  if c_invert then
+    o <= not i;
+  else
+    o <= i;
+
+end behav;
--- a/testsuite/files/pkg5.vhdl
+++ b/testsuite/files/pkg5.vhdl
+package pkg5 is
+  constant c_invert : boolean;
+end package pkg5;
--- a/testsuite/files/pkg5_body.vhdl
+++ b/testsuite/files/pkg5_body.vhdl
+package body pkg5 is
+  constant c_invert : boolean := true;
+end package body pkg5;
--- a/testsuite/test_all.py
+++ b/testsuite/test_all.py
@@ -589,6 +589,9 @@ def test_explicit_required_lib_124():
 def test_arch_in_separate_file_125():
    run_compare(path="125arch_in_separate_file")

+def test_package_body_in_separate_file_126():
+    run_compare(path="126package_body_in_separate_file")
+
 @pytest.mark.xfail
 def test_xfail():
    """This is a self-consistency test: the test is known to fail"""