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Hdlmake
Commits
20c784df
Commit
20c784df
authored
Mar 08, 2013
by
Tomasz Wlostowski
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merge-cores option: append a notice saying that the file is automatically generated
parent
e982814b
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2 changed files
with
27 additions
and
3 deletions
+27
-3
hdlmake
hdlmake
+0
-0
hdlmake_kernel.py
src/hdlmake_kernel.py
+27
-3
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hdlmake
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src/hdlmake_kernel.py
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20c784df
...
@@ -402,11 +402,24 @@ class HdlmakeKernel(object):
...
@@ -402,11 +402,24 @@ class HdlmakeKernel(object):
flist
=
pool
.
build_global_file_list
();
flist
=
pool
.
build_global_file_list
();
flist_sorted
=
solver
.
solve
(
flist
);
flist_sorted
=
solver
.
solve
(
flist
);
if
not
os
.
path
.
exists
(
self
.
options
.
merge_cores
):
#
if not os.path.exists(self.options.merge_cores):
os
.
makedirs
(
self
.
options
.
merge_cores
)
#
os.makedirs(self.options.merge_cores)
base
=
self
.
options
.
merge_cores
+
"/"
+
self
.
options
.
merge_cores
base
=
self
.
options
.
merge_cores
f_out
=
open
(
base
+
".vhd"
,
"w"
)
f_out
=
open
(
base
+
".vhd"
,
"w"
)
f_out
.
write
(
"
\n\n\n\n
"
);
f_out
.
write
(
"------------------------------ WARNING -------------------------------
\n
"
);
f_out
.
write
(
"-- This code has been generated by hdlmake --merge-cores option --
\n
"
);
f_out
.
write
(
"-- It is provided for your convenience, to spare you from adding --
\n
"
);
f_out
.
write
(
"-- lots of individual source files to ISE/Modelsim/Quartus projects --
\n
"
);
f_out
.
write
(
"-- mainly for Windows users. Please DO NOT MODIFY this file. If you --
\n
"
);
f_out
.
write
(
"-- need to change something inside, edit the original source file --
\n
"
);
f_out
.
write
(
"-- and re-genrate the merged version! --
\n
"
);
f_out
.
write
(
"----------------------------------------------------------------------
\n
"
);
f_out
.
write
(
"
\n\n\n\n
"
);
for
vhdl
in
flist_sorted
.
filter
(
VHDLFile
):
for
vhdl
in
flist_sorted
.
filter
(
VHDLFile
):
f_out
.
write
(
"
\n\n
--- File:
%
s ----
\n\n
"
%
vhdl
.
rel_path
())
f_out
.
write
(
"
\n\n
--- File:
%
s ----
\n\n
"
%
vhdl
.
rel_path
())
f_out
.
write
(
open
(
vhdl
.
rel_path
(),
"r"
)
.
read
()
+
"
\n\n
"
)
f_out
.
write
(
open
(
vhdl
.
rel_path
(),
"r"
)
.
read
()
+
"
\n\n
"
)
...
@@ -415,6 +428,17 @@ class HdlmakeKernel(object):
...
@@ -415,6 +428,17 @@ class HdlmakeKernel(object):
f_out
=
open
(
base
+
".v"
,
"w"
)
f_out
=
open
(
base
+
".v"
,
"w"
)
f_out
.
write
(
"
\n\n\n\n
"
);
f_out
.
write
(
"////////////////////////////// WARNING ///////////////////////////////
\n
"
);
f_out
.
write
(
"// This code has been generated by hdlmake --merge-cores option //
\n
"
);
f_out
.
write
(
"// It is provided for your convenience, to spare you from adding //
\n
"
);
f_out
.
write
(
"// lots of individual source files to ISE/Modelsim/Quartus projects //
\n
"
);
f_out
.
write
(
"// mainly for Windows users. Please DO NOT MODIFY this file. If you //
\n
"
);
f_out
.
write
(
"// need to change something inside, edit the original source file //
\n
"
);
f_out
.
write
(
"// and re-genrate the merged version! //
\n
"
);
f_out
.
write
(
"//////////////////////////////////////////////////////////////////////
\n
"
);
f_out
.
write
(
"
\n\n\n\n
"
);
for
vlog
in
flist_sorted
.
filter
(
VerilogFile
):
for
vlog
in
flist_sorted
.
filter
(
VerilogFile
):
f_out
.
write
(
"
\n\n
// File:
%
s
\n\n
"
%
vlog
.
rel_path
())
f_out
.
write
(
"
\n\n
// File:
%
s
\n\n
"
%
vlog
.
rel_path
())
vpp
=
VerilogPreprocessor
()
vpp
=
VerilogPreprocessor
()
...
...
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