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Hdlmake
Commit 27255e5c authored by Tristan Gingold's avatar Tristan Gingold
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Merge branch 'develop' - fix minor conflict.

parents 43d55c33 d323bdaf
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Showing with 3359 additions and 123 deletions
hdlmake/__main__.py
View file @ 27255e5c
......@@ -33,7 +33,7 @@ from .module_pool import ModulePool
from ._version import __version__
def main():
def hdlmake(args):
"""This is the main function, where HDLMake starts.
Here, we make the next processes:
-- parse command
......@@ -49,7 +49,7 @@ def main():
#
# PARSE & GET OPTIONS
#
options = _get_options(sys, parser)
options = _get_options(args, parser)
try:
# Create a ModulePool object, this will become our workspace
......@@ -71,7 +71,6 @@ def _action_runner(modules_pool):
options = modules_pool.options
if options.command == "manifest-help":
ManifestParser().print_help()
quit(0)
elif options.command == "makefile":
modules_pool.makefile()
elif options.command == "fetch":
......@@ -205,18 +204,22 @@ def _get_parser():
return parser
def _get_options(sys_aux, parser):
def _get_options(args, parser):
"""Function that decodes and set the provided command user options"""
options = None
if len(sys_aux.argv[1:]) == 0:
if len(args) == 0:
options = parser.parse_args(['makefile'])
elif len(sys_aux.argv[1:]) == 2 and (
sys_aux.argv[1] == '-f' or sys_aux.argv[1] == '--filename'):
options = parser.parse_args(['makefile'] + sys_aux.argv[1:])
elif len(args) == 2 and (
args[0] == '-f' or args[0] == '--filename'):
options = parser.parse_args(['makefile'] + args)
else:
options = parser.parse_args(sys_aux.argv[1:])
options = parser.parse_args(args)
return options
def main():
"""Entry point used by the executable"""
hdlmake(sys.argv[1:])
if __name__ == "__main__":
main()
hdlmake/action/action.py
View file @ 27255e5c
......@@ -114,26 +114,6 @@ class Action(list):
new_module.parse_manifest()
return new_module
def _check_manifest_variable_is_set(self, name):
"""Method to check if a specific manifest variable is set"""
if getattr(self.top_module, name) is None:
raise Exception(
"Variable %s must be set in the manifest "
"to perform current action (%s)",
name, self.__class__.__name__)
def _check_manifest_variable_value(self, name, value):
"""Method to check if a manifest variable is set to a specific value"""
variable_match = False
manifest_value = getattr(self.top_module, name)
if manifest_value == value:
variable_match = True
if variable_match is False:
raise Exception(
"Variable %s must be set in the manifest and equal to '%s'.",
name, value)
def build_complete_file_set(self):
"""Build file set with all the files listed in the complete pool"""
logging.debug("Begin build complete file set")
......
hdlmake/fetch/fetcher.py
View file @ 27255e5c
......@@ -33,13 +33,3 @@ class Fetcher(object):
def fetch(self, module):
"""Stub method, this must be implemented by the code fetcher"""
pass
@staticmethod
def check_id(path, command):
"""Use the provided command to get the specific ID from
the repository at path"""
cur_dir = os.getcwd()
os.chdir(path)
identifier = shell.run(command)
os.chdir(cur_dir)
return identifier
hdlmake/fetch/git.py
View file @ 27255e5c
......@@ -106,12 +106,6 @@ class Git(Fetcher):
module.path = mod_path
return True
@staticmethod
def check_git_commit(path):
"""Get the revision number for the Git repository at path"""
git_cmd = 'git log -1 --format="%H" | cut -c1-32'
return Fetcher.check_id(path, git_cmd)
@staticmethod
def get_git_submodules(module):
"""Get a dictionary containing the git submodules
......@@ -135,7 +129,7 @@ class Git(Fetcher):
stdin=PIPE,
close_fds=not shell.check_windows(),
shell=True)
config_lines = [line.strip() for line
config_lines = [line.strip().decode('utf-8') for line
in config_content.stdout.readlines()]
config_submodule_lines = [line for line in config_lines
if line.startswith("submodule")]
......
hdlmake/fetch/local.py
View file @ 27255e5c
......@@ -30,11 +30,3 @@ class Local(Fetcher):
def __init__(self):
pass
def fetch(self, module):
pass
@staticmethod
def check_md5sum(path):
"""Get the ID for Local sources... maybe sha256 or md5sum?"""
pass
hdlmake/fetch/svn.py
View file @ 27255e5c
......@@ -56,9 +56,3 @@ class Svn(Fetcher):
module.isfetched = True
module.path = mod_path
return success
@staticmethod
def check_svn_revision(path):
"""Get the revision number for the SVN repository at path"""
svn_cmd = "svn info 2>/dev/null | awk '{if(NR == 5) {print $2}}'"
return Fetcher.check_id(path, svn_cmd)
hdlmake/manifest_parser/configparser.py
View file @ 27255e5c
......@@ -222,9 +222,7 @@ types:[<type 'int'>]
line = ' {0:15}; {1:29}; {2:45}{3}{4:10}'
try:
tmp_def = opt.default
if tmp_def == "":
tmp_def = '""'
tmp_def = opt.default or '""'
line = line.format(
opt.name,
str(opt.types),
......
hdlmake/srcfile.py
View file @ 27255e5c
......@@ -194,10 +194,13 @@ class VEOFile(File):
pass
class XCIFile(File):
class XCIFile(SourceFile):
"""Xilinx Core IP File"""
pass
def __init__(self, path, module, library=None):
SourceFile.__init__(self, path=path, module=module, library=library)
from hdlmake.xci_parser import XCIParser
self.parser = XCIParser(self)
XILINX_FILE_DICT = {
'xise': XISEFile,
......@@ -370,27 +373,6 @@ class SourceFileSet(set):
out.add(file_aux)
return out
def inversed_filter(self, filetype):
"""Method that filters and returns all of the HDL source files
contained in the instance SourceFileSet NOT matching the provided
type"""
out = SourceFileSet()
for file_aux in self:
if not isinstance(file_aux, filetype):
out.add(file_aux)
return out
def get_libs(self):
"""Method that returns a set containing all of the libraries that are
provided by any of the source files in the SourceFileSet"""
ret = set()
for file_aux in self:
try:
ret.add(file_aux.library)
except TypeError:
pass
return ret
def create_source_file(path, module, library=None,
include_dirs=None, is_include=False):
......
hdlmake/tools/make_sim.py
View file @ 27255e5c
......@@ -41,6 +41,7 @@ class ToolSim(ToolMakefile):
self._makefile_sim_command()
self._makefile_sim_clean()
self._makefile_sim_phony()
self.makefile_close()
def _makefile_sim_top(self):
"""Generic method to write the simulation Makefile top section"""
......
hdlmake/tools/make_syn.py
View file @ 27255e5c
......@@ -52,6 +52,7 @@ class ToolSyn(ToolMakefile):
self._makefile_syn_build()
self._makefile_syn_clean()
self._makefile_syn_phony()
self.makefile_close()
logging.info(self._tool_info['name'] + " synthesis makefile generated.")
def _makefile_syn_top(self):
......
hdlmake/tools/makefile.py
View file @ 27255e5c
......@@ -177,6 +177,10 @@ class ToolMakefile(object):
elif not self._file:
self._file = open(self._filename, "a+")
def makefile_close(self):
self._file.close()
self._file = None
def write(self, line=None):
"""Write a string in the manifest, no new line"""
if not self._initialized:
......
hdlmake/tools/vivado.py
View file @ 27255e5c
......@@ -26,7 +26,8 @@
from __future__ import absolute_import
from .xilinx import ToolXilinx
from hdlmake.srcfile import (XDCFile, XCIFile, NGCFile, XMPFile,
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile,
XDCFile, XCIFile, NGCFile, XMPFile,
XCOFile, COEFile, BDFile, TCLFile, BMMFile,
MIFFile, RAMFile, VHOFile, VEOFile, XCFFile)
......@@ -48,7 +49,6 @@ class ToolVivado(ToolXilinx):
SUPPORTED_FILES = {
XDCFile: ToolXilinx._XILINX_SOURCE,
XCFFile: ToolXilinx._XILINX_SOURCE,
XCIFile: ToolXilinx._XILINX_SOURCE,
NGCFile: ToolXilinx._XILINX_SOURCE,
XMPFile: ToolXilinx._XILINX_SOURCE,
XCOFile: ToolXilinx._XILINX_SOURCE,
......@@ -61,6 +61,12 @@ class ToolVivado(ToolXilinx):
VHOFile: ToolXilinx._XILINX_SOURCE,
VEOFile: ToolXilinx._XILINX_SOURCE}
HDL_FILES = {
VHDLFile: ToolXilinx._XILINX_SOURCE,
VerilogFile: ToolXilinx._XILINX_SOURCE,
SVFile: ToolXilinx._XILINX_SOURCE,
XCIFile: ToolXilinx._XILINX_SOURCE}
CLEAN_TARGETS = {'clean': [".Xil", "*.jou", "*.log", "*.pb", "*.dmp",
"$(PROJECT).cache", "$(PROJECT).data", "work",
"$(PROJECT).runs", "$(PROJECT).hw",
......@@ -79,3 +85,4 @@ class ToolVivado(ToolXilinx):
self._standard_libs.extend(ToolVivado.STANDARD_LIBS)
self._clean_targets.update(ToolVivado.CLEAN_TARGETS)
self._tcl_controls.update(ToolVivado.TCL_CONTROLS)
self._hdl_files.update(ToolVivado.HDL_FILES)
hdlmake/util/path.py
View file @ 27255e5c
......@@ -83,40 +83,6 @@ def svn_basename(url):
return None
def pathsplit(path, rest=None):
"""
Split the provided path and return as a tuple
"""
if rest is None:
rest = []
(head, tail) = os.path.split(path)
if len(head) < 1:
return [tail] + rest
if len(tail) < 1:
return [head] + rest
return pathsplit(head, [tail] + rest)
def commonpath(path1, path2, common=None):
"""
Return the common path for the provided paths
"""
if common is None:
common = []
if len(path1) < 1:
return (common, path1, path2)
if len(path2) < 1:
return (common, path1, path2)
if path1[0] != path2[0]:
return (common, path1, path2)
return commonpath(path1[1:], path2[1:], common + [path1[0]])
def is_rel_path(path):
"""Check if the given path is relative"""
return not os.path.isabs(path)
def is_abs_path(path):
"""Check if the given path is absolute"""
return os.path.isabs(path)
......
hdlmake/util/shell.py
View file @ 27255e5c
......@@ -43,7 +43,7 @@ def run(command):
lines = command_out.stdout.readlines()
if len(lines) == 0:
return None
return lines[0].strip()
return lines[0].strip().decode('utf-8')
except CalledProcessError as process_error:
logging.error("Cannot execute the shell command: %s",
process_error.output)
......
hdlmake/env.py → hdlmake/xci_parser.py
View file @ 27255e5c
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
# Author: Nick Brereton
#
# This file is part of Hdlmake.
#
......@@ -18,47 +15,45 @@
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
# along with Hdlmake. If not, see .
#
"""Package providing the bridge with the Host O.S. environment"""
"""This module provides a Xilinx XCI IP description parser for HDLMake"""
from __future__ import print_function
from __future__ import absolute_import
import os
import os.path
import re
import logging
import six
from xml.etree import ElementTree as ET
class Env(dict):
from .new_dep_solver import DepParser
from .dep_file import DepRelation
from hdlmake.srcfile import create_source_file
"""The Env (Environment) is a dictionary containing the environmental
variables related with HDLMake for a proper use in the Python code"""
class XCIParser(DepParser):
"""Class providing the Xilinx XCI parser"""
def __init__(self, options):
dict.__init__(self)
self.options = options
def __init__(self, dep_file):
DepParser.__init__(self, dep_file)
def _report_and_set_hdlmake_var(self, name):
"""Create a new entry in the Env dictionary and initialize the value
to the obtained from the O.S. environmental variable if defined"""
def _get(name):
"""Ask the Host O.S. for the value of an HDLMAKE_(name)
environmental variable"""
assert not name.startswith("HDLMAKE_")
assert isinstance(name, six.string_types)
name = name.upper()
return os.environ.get("HDLMAKE_%s" % name)
name = name.upper()
val = _get(name)
if val:
logging.debug('Environmental variable HDLMAKE_%s is set: "%s".',
name, val)
self[name.lower()] = val
return True
else:
logging.warning("Environmental variable HDLMAKE_%s is not set.",
name)
self[name.lower()] = None
return False
def parse(self, dep_file):
"""Parse a Xilinx XCI IP description file to determine the provided module(s)"""
if dep_file.is_parsed:
return
logging.debug("Parsing %s", dep_file.path)
with open(dep_file.path) as f:
# extract namespaces with a regex -- not really ideal, but without pulling in
# an external xml lib I can't think of a better way.
xmlnsre = re.compile(r'''\bxmlns:(\w+)\s*=\s*"(\w+://[^"]*)"''', re.MULTILINE)
xml = f.read()
nsmap = dict(xmlnsre.findall(xml))
value = ET.fromstring(xml).find('spirit:componentInstances/spirit:componentInstance/spirit:instanceName', nsmap)
if not value is None:
modulename = value.text
logging.debug("found module %s.%s", dep_file.library, modulename)
dep_file.add_relation(
DepRelation("%s.%s" % (dep_file.library, modulename),
DepRelation.PROVIDE, DepRelation.MODULE))
dep_file.is_parsed = True
testsuite/.coveragerc 0 → 100644
View file @ 27255e5c
[run]
source = ../hdlmake
# Termcolor is an external module
# tree has external dependencies
omit = ../hdlmake/util/termcolor.py
../hdlmake/action/tree.py
testsuite/001ise/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).xise
TOOL_PATH :=
TCL_INTERPRETER := xtclsh
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Spartan6
SYN_DEVICE := xc6slx45t
SYN_PACKAGE := fgg484
SYN_GRADE := -3
TCL_CREATE := project new $(PROJECT_FILE)
TCL_OPEN := project open $(PROJECT_FILE)
TCL_SAVE := project save
TCL_CLOSE := project close
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "xfile add $(sourcefile)" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_TRANSLATE_CMD :=
SYN_POST_TRANSLATE_CMD :=
SYN_PRE_MAP_CMD :=
SYN_POST_MAP_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo xfile remove [search \* -type file] >> $@
echo source files.tcl >> $@
echo project set \"family\" \"$(SYN_FAMILY)\" >> $@
echo project set \"device\" \"$(SYN_DEVICE)\" >> $@
echo project set \"package\" \"$(SYN_PACKAGE)\" >> $@
echo project set \"speed\" \"$(SYN_GRADE)\" >> $@
echo project set \"Manual Implementation Compile Order\" \"false\" >> $@
echo project set \"Auto Implementation Top\" \"false\" >> $@
echo project set \"Create Binary Configuration File\" \"true\" >> $@
echo set compile_directory . >> $@
echo project set top $(TOP_MODULE) >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Synthesize - XST} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
translate.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Translate} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
translate: synthesize translate.tcl
$(SYN_PRE_TRANSLATE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_TRANSLATE_CMD)
touch $@
map.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Map} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
map: translate map.tcl
$(SYN_PRE_MAP_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_MAP_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Place '&' Route} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
par: map par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Generate Programming File} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) xst xlnx_auto_0_xdb iseconfig _xmsgs _ngo *.b *_summary.html *.bld *.cmd_log *.drc *.lso *.ncd *.ngc *.ngd *.ngr *.pad *.par *.pcf *.prj *.ptwx *.stx *.syr *.twr *.twx *.gise *.gise *.bgn *.unroutes *.ut *.xpi *.xst *.xise *.xwbt *_envsettings.html *_guide.ncd *_map.map *_map.mrp *_map.ncd *_map.ngm *_map.xrpt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_par.xrpt *_summary.xml *_usage.xml *_xst.xrpt usage_statistics_webtalk.html webtalk.log par_usage_statistics.html webtalk_pn.xml
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.bit *.bin *.mcs
.PHONY: mrproper clean all
testsuite/001ise/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
language = "vhdl"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "gate"
syn_project = "gate.xise"
syn_tool = "ise"
files = [ "../files/gate.vhdl" ]
testsuite/002msim/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
MODELSIM_INI_PATH := ../linux_fakebin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/002msim/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
testsuite/003msim/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
MODELSIM_INI_PATH := my_ini
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/003msim/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="modelsim"
modelsim_ini_path="my_ini"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
testsuite/004msim/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
MODELSIM_INI_PATH := fake_bin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/004msim/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="modelsim"
sim_path="fake_bin"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
testsuite/005noact/Manifest.py 0 → 100644
View file @ 27255e5c
language = "vhdl"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
testsuite/006ahdl/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
simulation:
echo # Active-HDL command file, generated by HDLMake > run.command
echo # Create library and set as default target >> run.command
echo alib work >> run.command
echo set worklib work >> run.command
echo # Compiling HDL source files >> run.command
echo acom "../files/gate.vhdl" >> run.command
vsimsa -do run.command
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) run.command library.cfg work
clean:
del /s /q /f $(CLEAN_TARGETS)
@-rmdir /s /q $(CLEAN_TARGETS) >nul 2>&1
mrproper: clean
del /s /q /f *.vcd *.asdb
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/006ahdl/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="active_hdl"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
testsuite/007diamond/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).ldf
TOOL_PATH :=
TCL_INTERPRETER := diamondc
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY :=
SYN_DEVICE := anfpga
SYN_PACKAGE := ff
SYN_GRADE := 3
TCL_CREATE := prj_project new -name $(PROJECT) -impl $(PROJECT) -dev ANFPGA3FF -synthesis "synplify"
TCL_OPEN := prj_project open $(PROJECT).ldf
TCL_SAVE := prj_project save
TCL_CLOSE := prj_project close
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "prj_src add $(sourcefile)" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo source files.tcl >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo prj_run PAR -impl $(PROJECT) >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
par: project par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo prj_run Export -impl $(PROJECT) -task Bitgen >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) *.sty $(PROJECT)
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.jed
.PHONY: mrproper clean all
testsuite/007diamond/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
syn_tool="diamond"
syn_device="anfpga"
syn_grade="3"
syn_package="ff"
syn_project="gate"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
testsuite/008ghdl/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
GHDL := ghdl
GHDL_OPT :=
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
simulation: $(VERILOG_OBJ) $(VHDL_OBJ)
$(GHDL) -e $(GHDL_OPT) $(TOP_MODULE)
work/gate/.gate_vhdl: ../files/gate.vhdl
$(GHDL) -a $(GHDL_OPT) $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) *.cf *.o $(TOP_MODULE) work
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/008ghdl/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="ghdl"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
testsuite/009icestorm/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate2
PWD := $(shell pwd)
PROJECT := gate2
PROJECT_FILE := $(PROJECT).
TOOL_PATH :=
TCL_INTERPRETER := yosys -c
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := iCE40
SYN_DEVICE := ice40
SYN_PACKAGE := ff
SYN_GRADE := 3
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VerilogFile := \
../files/gate2.v
files.tcl:
@$(foreach sourcefile, $(SOURCES_VerilogFile), echo "read_verilog $(sourcefile)" >> $@ &)
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
synthesize.tcl:
echo yosys -import >> $@
echo source files.tcl >> $@
echo synth_ice40 -top $(TOP_MODULE) -blif $(PROJECT).blif >> $@
synthesize: files.tcl synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
par.tcl:
echo catch {exec arachne-pnr -d $(SYN_DEVICE) -P $(SYN_PACKAGE) -p $(SOURCES_PCFFile) -o $(PROJECT).asc $(PROJECT).blif} >> $@
par: synthesize par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo catch {exec icepack $(PROJECT).asc $(PROJECT).bin} >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) $(PROJECT).asc $(PROJECT).blif
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf $(PROJECT).bin
.PHONY: mrproper clean all
testsuite/009icestorm/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
syn_tool="icestorm"
syn_device="ice40"
syn_grade="3"
syn_package="ff"
syn_project="gate2"
top_module = "gate2"
files = [ "../files/gate2.v" ]
testsuite/010isim/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD := $(shell pwd)
TOP_MODULE := gate_tb
FUSE_OUTPUT ?= isim_proj
VHPCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := ../files/gate_tb.v \
VERILOG_OBJ := work/gate_tb/.gate_tb_v \
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
LIBS := work
LIB_IND := work/.work
simulation: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse
$(VERILOG_OBJ): $(LIB_IND) xilinxsim.ini
$(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
xilinxsim.ini: $(XILINX_INI_PATH)/xilinxsim.ini
cp $< .
fuse:
fuse work.$(TOP_MODULE) -intstyle ise -incremental -o $(FUSE_OUTPUT)
work/.work:
(mkdir -p work && touch work/.work && echo work=work >> xilinxsim.ini) || rm -rf work
work/gate_tb/.gate_tb_v: ../files/gate_tb.v ../files/gate.vhdl
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../files $<
@mkdir -p $(dir $@) && touch $@
work/gate/.gate_vhdl: ../files/gate.vhdl work/gate/.gate
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gate/.gate:
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) xilinxsim.ini $(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log isim.wdb isim_proj isim_proj.*
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/010isim/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="isim"
top_module = "gate_tb"
files = [ "../files/gate.vhdl", "../files/gate_tb.v" ]
testsuite/011xfail/Makefile 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).xise
TOOL_PATH :=
TCL_INTERPRETER := xtclsh
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Spartan6
SYN_DEVICE := xc6slx45t
SYN_PACKAGE := fgg484
SYN_GRADE := -3
TCL_CREATE := project new $(PROJECT_FILE)
TCL_OPEN := project open $(PROJECT_FILE)
TCL_SAVE := project save
TCL_CLOSE := project close
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "xfile add $(sourcefile)" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_TRANSLATE_CMD :=
SYN_POST_TRANSLATE_CMD :=
SYN_PRE_MAP_CMD :=
SYN_POST_MAP_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo xfile remove [search \* -type file] >> $@
echo source files.tcl >> $@
echo project set \"family\" \"$(SYN_FAMILY)\" >> $@
echo project set \"device\" \"$(SYN_DEVICE)\" >> $@
echo project set \"package\" \"$(SYN_PACKAGE)\" >> $@
echo project set \"speed\" \"$(SYN_GRADE)\" >> $@
echo project set \"Manual Implementation Compile Order\" \"false\" >> $@
echo project set \"Auto Implementation Top\" \"false\" >> $@
echo project set \"Create Binary Configuration File\" \"true\" >> $@
echo set compile_directory . >> $@
echo project set top $(TOP_MODULE) >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Synthesize - XST} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
translate.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Translate} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
translate: synthesize translate.tcl
$(SYN_PRE_TRANSLATE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_TRANSLATE_CMD)
touch $@
map.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Map} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
map: translate map.tcl
$(SYN_PRE_MAP_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_MAP_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Place '&' Route} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
par: map par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Generate Programming File} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) xst xlnx_auto_0_xdb iseconfig _xmsgs _ngo *.b *_summary.html *.bld *.cmd_log *.drc *.lso *.ncd *.ngc *.ngd *.ngr *.pad *.par *.pcf *.prj *.ptwx *.stx *.syr *.twr *.twx *.gise *.gise *.bgn *.unroutes *.ut *.xpi *.xst *.xise *.xwbt *_envsettings.html *_guide.ncd *_map.map *_map.mrp *_map.ncd *_map.ngm *_map.xrpt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_par.xrpt *_summary.xml *_usage.xml *_xst.xrpt usage_statistics_webtalk.html webtalk.log par_usage_statistics.html webtalk_pn.xml
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.bit *.bin *.mcs
.PHONY: mrproper clean all
testsuite/011xfail/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
extra_line: makefile differs...
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).xise
TOOL_PATH :=
TCL_INTERPRETER := xtclsh
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Spartan6
SYN_DEVICE := xc6slx45t
SYN_PACKAGE := fgg484
SYN_GRADE := -3
TCL_CREATE := project new $(PROJECT_FILE)
TCL_OPEN := project open $(PROJECT_FILE)
TCL_SAVE := project save
TCL_CLOSE := project close
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "xfile add $(sourcefile)" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_TRANSLATE_CMD :=
SYN_POST_TRANSLATE_CMD :=
SYN_PRE_MAP_CMD :=
SYN_POST_MAP_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo xfile remove [search \* -type file] >> $@
echo source files.tcl >> $@
echo project set \"family\" \"$(SYN_FAMILY)\" >> $@
echo project set \"device\" \"$(SYN_DEVICE)\" >> $@
echo project set \"package\" \"$(SYN_PACKAGE)\" >> $@
echo project set \"speed\" \"$(SYN_GRADE)\" >> $@
echo project set \"Manual Implementation Compile Order\" \"false\" >> $@
echo project set \"Auto Implementation Top\" \"false\" >> $@
echo project set \"Create Binary Configuration File\" \"true\" >> $@
echo set compile_directory . >> $@
echo project set top $(TOP_MODULE) >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Synthesize - XST} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
translate.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Translate} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
translate: synthesize translate.tcl
$(SYN_PRE_TRANSLATE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_TRANSLATE_CMD)
touch $@
map.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Map} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
map: translate map.tcl
$(SYN_PRE_MAP_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_MAP_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Place '&' Route} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
par: map par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Generate Programming File} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) xst xlnx_auto_0_xdb iseconfig _xmsgs _ngo *.b *_summary.html *.bld *.cmd_log *.drc *.lso *.ncd *.ngc *.ngd *.ngr *.pad *.par *.pcf *.prj *.ptwx *.stx *.syr *.twr *.twx *.gise *.gise *.bgn *.unroutes *.ut *.xpi *.xst *.xise *.xwbt *_envsettings.html *_guide.ncd *_map.map *_map.mrp *_map.ncd *_map.ngm *_map.xrpt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_par.xrpt *_summary.xml *_usage.xml *_xst.xrpt usage_statistics_webtalk.html webtalk.log par_usage_statistics.html webtalk_pn.xml
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.bit *.bin *.mcs
.PHONY: mrproper clean all
testsuite/011xfail/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
language = "vhdl"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "gate"
syn_project = "gate.xise"
syn_tool = "ise"
files = [ "../files/gate.vhdl" ]
testsuite/012icarus/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate2
PWD := $(shell pwd)
IVERILOG_OPT :=
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := ../files/gate2.v \
VERILOG_OBJ := work/gate2/.gate2_v \
VHDL_SRC :=
VHDL_OBJ :=
simulation: include_dirs $(VERILOG_OBJ) $(VHDL_OBJ)
iverilog $(IVERILOG_OPT) -s $(TOP_MODULE) -o $(TOP_MODULE).vvp -c run.command
include_dirs:
echo "# IVerilog command file, generated by HDLMake" > run.command
work/gate2/.gate2_v: ../files/gate2.v
echo $< >> run.command
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) run.command ivl_vhdl_work work
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.vvp
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/012icarus/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="iverilog"
top_module = "gate2"
files = [ "../files/gate2.v" ]
testsuite/013libero/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).prjx
TOOL_PATH :=
TCL_INTERPRETER := libero SCRIPT:
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY :=
SYN_DEVICE := anfpga
SYN_PACKAGE := ff
SYN_GRADE := 3
TCL_CREATE := new_project -location {./gate} -name {gate} -hdl {VHDL} -family {ProASIC3} -die {ANFPGA} -package {FF} -speed {3} -die_voltage {1.5}
TCL_OPEN := open_project -file {$(PROJECT)/$(PROJECT_FILE)}
TCL_SAVE := save_project
TCL_CLOSE := close_project
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
SOURCES_SDCFile := \
syn.sdc
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "create_links -hdl_source $(sourcefile)" >> $@ &)
@$(foreach sourcefile, $(SOURCES_SDCFile), echo "create_links -sdc $(sourcefile)" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo source files.tcl >> $@
echo organize_tool_files -tool {SYNTHESIZE} -file {syn.sdc} -module {$(TOP_MODULE)::work} -input_type {constraint} >> $@
echo organize_tool_files -tool {COMPILE} -file {syn.sdc} -module {$(TOP_MODULE)::work} -input_type {constraint} >> $@
echo set_root -module {$(TOP_MODULE)::work} >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo update_and_run_tool -name {GENERATEPROGRAMMINGDATA} >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
bitstream: project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) $(PROJECT)
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.pdb *.stp
.PHONY: mrproper clean all
testsuite/013libero/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
syn_tool="libero"
syn_device="anfpga"
syn_grade="3"
syn_package="ff"
syn_project="gate"
top_module = "gate"
# Not reliable.
#files = [ "../files/gate.vhdl", "syn.sdc", "comp.pdc" ]
files = [ "../files/gate.vhdl", "syn.sdc" ]
testsuite/014planahead/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).ppr
TOOL_PATH :=
TCL_INTERPRETER := planAhead -mode tcl -source
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY :=
SYN_DEVICE := xc6slx45t
SYN_PACKAGE := fgg484
SYN_GRADE := -3
TCL_CREATE := create_project $(PROJECT) ./
TCL_OPEN := open_project $(PROJECT_FILE)
TCL_CLOSE := exit
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "add_files -norecurse $(sourcefile); set_property IS_GLOBAL_INCLUDE 1 [get_files $(sourcefile)]" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo # project properties >> $@
echo set_property "part" "$(SYN_DEVICE)$(SYN_PACKAGE)$(SYN_GRADE)" [current_project] >> $@
echo set_property "target_language" "vhdl" [current_project] >> $@
echo set_property "top" "$(TOP_MODULE)" [get_property srcset [current_run]] >> $@
echo source files.tcl >> $@
echo update_compile_order -fileset sources_1 >> $@
echo update_compile_order -fileset sim_1 >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo # synthesize properties >> $@
echo reset_run synth_1 >> $@
echo launch_runs synth_1 >> $@
echo wait_on_run synth_1 >> $@
echo set result [get_property STATUS [get_runs synth_1]] >> $@
echo set keyword [lindex [split '$$'result " "] end] >> $@
echo if { '$$'keyword != \"Complete!\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_CLOSE) >> $@
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo # par properties >> $@
echo reset_run impl_1 >> $@
echo launch_runs impl_1 >> $@
echo wait_on_run impl_1 >> $@
echo set result [get_property STATUS [get_runs impl_1]] >> $@
echo set keyword [lindex [split '$$'result " "] end] >> $@
echo if { '$$'keyword != \"Complete!\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_CLOSE) >> $@
par: synthesize par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo launch_runs impl_1 -to_step Bitgen >> $@
echo wait_on_run impl_1 >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) planAhead_* planAhead.* .Xil $(PROJECT).cache $(PROJECT).data $(PROJECT).runs $(PROJECT).ppr
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.bit *.bin
.PHONY: mrproper clean all
testsuite/014planahead/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
language = "vhdl"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "gate"
syn_project = "gate.xise"
syn_tool = "planahead"
files = [ "../files/gate.vhdl" ]
testsuite/015quartus/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate_prj
PROJECT_FILE := $(PROJECT).qpf
TOOL_PATH :=
TCL_INTERPRETER := quartus_sh -t
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Arria V
SYN_DEVICE := 5agxmb1g4f40c4
SYN_PACKAGE := 40
SYN_GRADE := c4
TCL_CREATE := project_new $(PROJECT)
TCL_OPEN := project_open $(PROJECT)
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@echo >> $@
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "set_global_assignment -name VHDL_FILE $(sourcefile) -library work" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo load_package flow >> $@
echo $(TCL_CREATE) >> $@
echo remove_all_global_assignments -name *_FILE >> $@
echo source files.tcl >> $@
echo set_global_assignment -name FAMILY \"$(SYN_FAMILY)\" >> $@
echo set_global_assignment -name DEVICE \"$(SYN_DEVICE)\" >> $@
echo set_global_assignment -name TOP_LEVEL_ENTITY \"$(TOP_MODULE)\" >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
bitstream.tcl:
echo load_package flow >> $@
echo $(TCL_OPEN) >> $@
echo execute_flow -compile >> $@
bitstream: project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) *.rpt *.smsg *.summary *.done *.jdi *.pin *.qws db incremental_db $(PROJECT).qsf *.qpf
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.sof *.pof *.jam *.jbc *.ekp *.jic
.PHONY: mrproper clean all
testsuite/015quartus/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
language = "vhdl"
syn_family = "Arria V"
syn_device = "5agxmb1g4f"
syn_grade = "c4"
syn_package = "40"
syn_top = "gate"
syn_project = "gate_prj"
syn_tool = "quartus"
files = [ "../files/gate.vhdl" ]
testsuite/016quartus_nofam/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate_prj
PROJECT_FILE := $(PROJECT).qpf
TOOL_PATH :=
TCL_INTERPRETER := quartus_sh -t
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Arria V
SYN_DEVICE := 5agxmb1g4f40c4
SYN_PACKAGE := 40
SYN_GRADE := c4
TCL_CREATE := project_new $(PROJECT)
TCL_OPEN := project_open $(PROJECT)
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@echo >> $@
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "set_global_assignment -name VHDL_FILE $(sourcefile) -library work" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo load_package flow >> $@
echo $(TCL_CREATE) >> $@
echo remove_all_global_assignments -name *_FILE >> $@
echo source files.tcl >> $@
echo set_global_assignment -name FAMILY \"$(SYN_FAMILY)\" >> $@
echo set_global_assignment -name DEVICE \"$(SYN_DEVICE)\" >> $@
echo set_global_assignment -name TOP_LEVEL_ENTITY \"$(TOP_MODULE)\" >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
bitstream.tcl:
echo load_package flow >> $@
echo $(TCL_OPEN) >> $@
echo execute_flow -compile >> $@
bitstream: project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) *.rpt *.smsg *.summary *.done *.jdi *.pin *.qws db incremental_db $(PROJECT).qsf *.qpf
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.sof *.pof *.jam *.jbc *.ekp *.jic
.PHONY: mrproper clean all
testsuite/016quartus_nofam/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
language = "vhdl"
syn_device = "5agxmb1g4f"
syn_grade = "c4"
syn_package = "40"
syn_top = "gate"
syn_project = "gate_prj"
syn_tool = "quartus"
files = [ "../files/gate.vhdl" ]
testsuite/017riviera/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
VCOM_FLAGS := -quiet -2008
VSIM_FLAGS :=
VLOG_FLAGS := -quiet
VMAP_FLAGS :=
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/.work
simulation: $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) :
$(VHDL_OBJ): $(LIB_IND)
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) *.asdb
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/017riviera/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="riviera"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
testsuite/018vivado/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).xpr
TOOL_PATH :=
TCL_INTERPRETER := vivado -mode tcl -source
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY :=
SYN_DEVICE := xc7z030
SYN_PACKAGE := ffg676
SYN_GRADE := -2
TCL_CREATE := create_project $(PROJECT) ./
TCL_OPEN := open_project $(PROJECT_FILE)
TCL_CLOSE := exit
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "add_files -norecurse $(sourcefile); set_property IS_GLOBAL_INCLUDE 1 [get_files $(sourcefile)]" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo # project properties >> $@
echo set_property "part" "$(SYN_DEVICE)$(SYN_PACKAGE)$(SYN_GRADE)" [current_project] >> $@
echo set_property "target_language" "vhdl" [current_project] >> $@
echo set_property "top" "$(TOP_MODULE)" [get_property srcset [current_run]] >> $@
echo source files.tcl >> $@
echo update_compile_order -fileset sources_1 >> $@
echo update_compile_order -fileset sim_1 >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo # synthesize properties >> $@
echo reset_run synth_1 >> $@
echo launch_runs synth_1 >> $@
echo wait_on_run synth_1 >> $@
echo set result [get_property STATUS [get_runs synth_1]] >> $@
echo set keyword [lindex [split '$$'result " "] end] >> $@
echo if { '$$'keyword != \"Complete!\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_CLOSE) >> $@
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo # par properties >> $@
echo reset_run impl_1 >> $@
echo launch_runs impl_1 >> $@
echo wait_on_run impl_1 >> $@
echo set result [get_property STATUS [get_runs impl_1]] >> $@
echo set keyword [lindex [split '$$'result " "] end] >> $@
echo if { '$$'keyword != \"Complete!\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_CLOSE) >> $@
par: synthesize par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo launch_runs impl_1 -to_step write_bitstream >> $@
echo wait_on_run impl_1 >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) .Xil *.jou *.log *.pb *.dmp $(PROJECT).cache $(PROJECT).data work $(PROJECT).runs $(PROJECT).hw $(PROJECT).ip_user_files $(PROJECT_FILE)
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.bit *.bin
.PHONY: mrproper clean all
testsuite/018vivado/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
language = "vhdl"
syn_device = "xc7z030"
syn_grade = "-2"
syn_package = "ffg676"
syn_top = "gate"
syn_project = "gate.xise"
syn_tool = "vivado"
files = [ "../files/gate.vhdl" ]
testsuite/019vsim/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
simulation: $(VERILOG_OBJ) $(VHDL_OBJ)
xelab -debug all $(TOP_MODULE) -s $(TOP_MODULE)
work/gate/.gate_vhdl: ../files/gate.vhdl
xvhdl $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) .Xil *.jou *.log *.pb work xsim.dir
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.wdb *.vcd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/019vsim/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="vivado_sim"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
testsuite/020git_fetch/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
fetchto = "ipcores"
files = [ "../files/gate.vhdl" ]
modules = { "git" : "git@test.org:tester/module1.git" }
testsuite/021svn_fetch/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
fetchto = "ipcores"
files = [ "../files/gate.vhdl" ]
modules = { "svn" : "http://test.org:tester/module1" }
testsuite/022gitsm_fetch/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
fetchto = "ipcores"
files = [ "../files/gate.vhdl" ]
modules = { "gitsm" : "git@test.org:tester/module1.git" }
testsuite/023xci/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).xpr
TOOL_PATH :=
TCL_INTERPRETER := vivado -mode tcl -source
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY :=
SYN_DEVICE := xc7z030
SYN_PACKAGE := ffg676
SYN_GRADE := -2
TCL_CREATE := create_project $(PROJECT) ./
TCL_OPEN := open_project $(PROJECT_FILE)
TCL_CLOSE := exit
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "add_files -norecurse $(sourcefile); set_property IS_GLOBAL_INCLUDE 1 [get_files $(sourcefile)]" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo # project properties >> $@
echo set_property "part" "$(SYN_DEVICE)$(SYN_PACKAGE)$(SYN_GRADE)" [current_project] >> $@
echo set_property "target_language" "vhdl" [current_project] >> $@
echo set_property "top" "$(TOP_MODULE)" [get_property srcset [current_run]] >> $@
echo source files.tcl >> $@
echo update_compile_order -fileset sources_1 >> $@
echo update_compile_order -fileset sim_1 >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo # synthesize properties >> $@
echo reset_run synth_1 >> $@
echo launch_runs synth_1 >> $@
echo wait_on_run synth_1 >> $@
echo set result [get_property STATUS [get_runs synth_1]] >> $@
echo set keyword [lindex [split '$$'result " "] end] >> $@
echo if { '$$'keyword != \"Complete!\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_CLOSE) >> $@
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo # par properties >> $@
echo reset_run impl_1 >> $@
echo launch_runs impl_1 >> $@
echo wait_on_run impl_1 >> $@
echo set result [get_property STATUS [get_runs impl_1]] >> $@
echo set keyword [lindex [split '$$'result " "] end] >> $@
echo if { '$$'keyword != \"Complete!\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_CLOSE) >> $@
par: synthesize par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo launch_runs impl_1 -to_step write_bitstream >> $@
echo wait_on_run impl_1 >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) .Xil *.jou *.log *.pb *.dmp $(PROJECT).cache $(PROJECT).data work $(PROJECT).runs $(PROJECT).hw $(PROJECT).ip_user_files $(PROJECT_FILE)
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.bit *.bin
.PHONY: mrproper clean all
testsuite/023xci/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
language = "vhdl"
syn_device = "xc7z030"
syn_grade = "-2"
syn_package = "ffg676"
syn_top = "gate"
syn_project = "gate.xise"
syn_tool = "vivado"
files = [ "../files/gate.vhdl", "ip.xci" ]
testsuite/023xci/ip.xci 0 → 100644
View file @ 27255e5c
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>my_ip</spirit:instanceName>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
testsuite/024vlog_parser/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
MODELSIM_INI_PATH := ../linux_fakebin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := vlog.v \
VERILOG_OBJ := work/vlog/.vlog_v \
VHDL_SRC :=
VHDL_OBJ :=
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/vlog/.vlog_v: vlog.v \
macros.v
vlog -work work $(VLOG_FLAGS) ${INCLUDE_DIRS} $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/024vlog_parser/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
files = [ "vlog.v" ]
testsuite/024vlog_parser/macros.v 0 → 100644
View file @ 27255e5c
`define MYWIRE(n) wire n;
testsuite/024vlog_parser/vlog.v 0 → 100644
View file @ 27255e5c
`include "macros.v"
module gate;
// My comment
`ifdef MYWIRE
`MYWIRE(w);
`endif
`ifndef MYWIRE
wire w2;
`elsif ALL
/* nothing. */
`else
wire \
w3;
`endif
endmodule
`pragma protect begin_protected
`pragma none
`pragma protect end_protected
testsuite/025vlog_parser/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
MODELSIM_INI_PATH := ../linux_fakebin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := vlog.v \
VERILOG_OBJ := work/vlog/.vlog_v \
VHDL_SRC :=
VHDL_OBJ :=
INCLUDE_DIRS := +incdir+inc
LIBS := work
LIB_IND := work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/vlog/.vlog_v: vlog.v \
inc/macros.v
vlog -work work $(VLOG_FLAGS) ${INCLUDE_DIRS} $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/025vlog_parser/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
include_dirs=["inc"]
files = [ "vlog.v" ]
testsuite/025vlog_parser/vlog.v 0 → 100644
View file @ 27255e5c
`include "macros.v"
module gate;
// My comment
`ifdef MYWIRE
`MYWIRE(w);
`endif
endmodule
testsuite/026gitsm_fetch/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
fetchto = "ipcores"
files = [ "../files/gate.vhdl" ]
modules = { "gitsm" : "git@test.org:tester/module2.git" }
testsuite/027vhdl_parser/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
MODELSIM_INI_PATH := ../linux_fakebin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := pkg.vhdl \
gate.vhdl \
VHDL_OBJ := work/pkg/.pkg_vhdl \
work/gate/.gate_vhdl \
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/pkg/.pkg_vhdl: pkg.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gate/.gate_vhdl: gate.vhdl \
work/pkg/.pkg_vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/027vhdl_parser/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
files = [ "gate.vhdl", "pkg.vhdl" ]
testsuite/027vhdl_parser/gate.vhdl 0 → 100644
View file @ 27255e5c
library ieee;
use work.pkg.all;
use ieee.unsigned.all;
entity gate is
end;
architecture arch of gate is
signal s : unsigned (3 downto 0);
type rec is record
a : natural;
end record;
component comp is
port (a : in bit);
end component;
function f return natural is
begin
return 1;
end f;
begin
assert false report msg;
inst1: entity work.ent1 port map (s);
end arch;
testsuite/027vhdl_parser/pkg.vhdl 0 → 100644
View file @ 27255e5c
package pkg is
constant msg : string := "hello";
end;
testsuite/028manifest_print/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
print("hello from Manifest.py")
testsuite/029manifest_quit/Manifest.py 0 → 100644
View file @ 27255e5c
import sys
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
sys.exit(1)
testsuite/030manifest_syntax/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
if True
pass
testsuite/031manifest_except/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
assert False
testsuite/032manifest_vars/Makefile 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
MODELSIM_INI_PATH := ../linux_fakebin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/032manifest_vars/Manifest.py 0 → 100644
View file @ 27255e5c
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
files = [ "../files/gate.vhdl" ]
__hidden = 5
myvar = 7
testsuite/033quartus/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate_prj
PROJECT_FILE := $(PROJECT).qpf
TOOL_PATH :=
TCL_INTERPRETER := quartus_sh -t
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Arria V
SYN_DEVICE := 5agxmb1g4f40c4
SYN_PACKAGE := 40
SYN_GRADE := c4
TCL_CREATE := project_new $(PROJECT)
TCL_OPEN := project_open $(PROJECT)
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@echo set_global_assignment -name PRE_FLOW_SCRIPT_FILE \""quartus_sh:none.tcl"\" >> $@
@echo set_global_assignment -name POST_MODULE_SCRIPT_FILE \""quartus_sh:none.tcl"\" >> $@
@echo set_global_assignment -name POST_FLOW_SCRIPT_FILE \""quartus_sh:none.tcl"\" >> $@
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "set_global_assignment -name VHDL_FILE $(sourcefile) -library work" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo load_package flow >> $@
echo $(TCL_CREATE) >> $@
echo remove_all_global_assignments -name *_FILE >> $@
echo source files.tcl >> $@
echo set_global_assignment -name FAMILY \"$(SYN_FAMILY)\" >> $@
echo set_global_assignment -name DEVICE \"$(SYN_DEVICE)\" >> $@
echo set_global_assignment -name TOP_LEVEL_ENTITY \"$(TOP_MODULE)\" >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
bitstream.tcl:
echo load_package flow >> $@
echo $(TCL_OPEN) >> $@
echo execute_flow -compile >> $@
bitstream: project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) *.rpt *.smsg *.summary *.done *.jdi *.pin *.qws db incremental_db $(PROJECT).qsf *.qpf
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.sof *.pof *.jam *.jbc *.ekp *.jic
.PHONY: mrproper clean all
testsuite/033quartus/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
language = "vhdl"
syn_family = "Arria V"
syn_device = "5agxmb1g4f"
syn_grade = "c4"
syn_package = "40"
syn_top = "gate"
syn_project = "gate_prj"
syn_tool = "quartus"
quartus_preflow='none.tcl'
quartus_postmodule='none.tcl'
quartus_postflow='none.tcl'
files = [ "../files/gate.vhdl" ]
testsuite/034quartus_prop/Makefile 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate_prj
PROJECT_FILE := $(PROJECT).qpf
TOOL_PATH :=
TCL_INTERPRETER := quartus_sh -t
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Arria V
SYN_DEVICE := 5agxmb1g4f40c4
SYN_PACKAGE := 40
SYN_GRADE := c4
TCL_CREATE := project_new $(PROJECT)
TCL_OPEN := project_open $(PROJECT)
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@echo >> $@
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "set_global_assignment -name VHDL_FILE $(sourcefile) -library work" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo load_package flow >> $@
echo $(TCL_CREATE) >> $@
echo remove_all_global_assignments -name *_FILE >> $@
echo source files.tcl >> $@
echo set_global_assignment -name FAMILY \"$(SYN_FAMILY)\" >> $@
echo set_global_assignment -name DEVICE \"$(SYN_DEVICE)\" >> $@
echo set_global_assignment -name TOP_LEVEL_ENTITY \"$(TOP_MODULE)\" >> $@
echo set_global_assignment vwaht -name vname \"vval\" -from vfrom -tag vtag -to vto -section_id vsid >> $@
echo set_global_assignment -name SEARCH_PATH \".\" >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
bitstream.tcl:
echo load_package flow >> $@
echo $(TCL_OPEN) >> $@
echo execute_flow -compile >> $@
bitstream: project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) *.rpt *.smsg *.summary *.done *.jdi *.pin *.qws db incremental_db $(PROJECT).qsf *.qpf
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.sof *.pof *.jam *.jbc *.ekp *.jic
.PHONY: mrproper clean all
testsuite/034quartus_prop/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate_prj
PROJECT_FILE := $(PROJECT).qpf
TOOL_PATH :=
TCL_INTERPRETER := quartus_sh -t
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Arria V
SYN_DEVICE := 5agxmb1g4f40c4
SYN_PACKAGE := 40
SYN_GRADE := c4
TCL_CREATE := project_new $(PROJECT)
TCL_OPEN := project_open $(PROJECT)
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@echo >> $@
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "set_global_assignment -name VHDL_FILE $(sourcefile) -library work" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo load_package flow >> $@
echo $(TCL_CREATE) >> $@
echo remove_all_global_assignments -name *_FILE >> $@
echo source files.tcl >> $@
echo set_global_assignment -name FAMILY \"$(SYN_FAMILY)\" >> $@
echo set_global_assignment -name DEVICE \"$(SYN_DEVICE)\" >> $@
echo set_global_assignment -name TOP_LEVEL_ENTITY \"$(TOP_MODULE)\" >> $@
echo set_global_assignment -name vname \"vval\" -from vfrom -tag vtag -to vto -section_id vsid >> $@
echo set_global_assignment -name SEARCH_PATH \".\" >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
bitstream.tcl:
echo load_package flow >> $@
echo $(TCL_OPEN) >> $@
echo execute_flow -compile >> $@
bitstream: project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) *.rpt *.smsg *.summary *.done *.jdi *.pin *.qws db incremental_db $(PROJECT).qsf *.qpf
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.sof *.pof *.jam *.jbc *.ekp *.jic
.PHONY: mrproper clean all
testsuite/034quartus_prop/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
language = "vhdl"
syn_family = "Arria V"
syn_device = "5agxmb1g4f"
syn_grade = "c4"
syn_package = "40"
syn_top = "gate"
syn_project = "gate_prj"
syn_tool = "quartus"
include_dirs=['.']
syn_properties=[{'what': 'vwaht',
'name': 'vname', 'from': 'vfrom', 'value': 'vval',
'tag': 'vtag',
'to': 'vto', 'section_id': 'vsid'}]
files = [ "../files/gate.vhdl" ]
testsuite/035quartus_err/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
language = "vhdl"
syn_family = "Arria V"
syn_device = "5agxmb1g4f"
syn_grade = "c4"
syn_package = "40"
syn_top = "gate"
syn_project = "gate_prj"
syn_tool = "quartus"
quartus_preflow='err.tcl'
files = [ "../files/gate.vhdl" ]
testsuite/036quartus_err/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
language = "vhdl"
syn_family = "Arria V"
syn_device = "5agxmb1g4f"
syn_grade = "c4"
syn_package = "40"
syn_top = "gate"
syn_project = "gate_prj"
syn_tool = "quartus"
quartus_postflow='err.tcl'
files = [ "../files/gate.vhdl" ]
testsuite/037quartus_err/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
language = "vhdl"
syn_family = "Arria V"
syn_device = "5agxmb1g4f"
syn_grade = "c4"
syn_package = "40"
syn_top = "gate"
syn_project = "gate_prj"
syn_tool = "quartus"
quartus_postmodule='err.tcl'
files = [ "../files/gate.vhdl" ]
testsuite/038quartus_err/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
language = "vhdl"
syn_family = "Arria V"
syn_device = "5agxmb1g4f"
syn_grade = "c4"
syn_package = "40"
syn_top = "gate"
syn_project = "gate_prj"
syn_tool = "quartus"
syn_properties=[[]]
files = [ "../files/gate.vhdl" ]
testsuite/039quartus_err/Manifest.py 0 → 100644
View file @ 27255e5c
action = "synthesis"
language = "vhdl"
syn_device = "unknown"
syn_grade = "c4"
syn_package = "40"
syn_top = "gate"
syn_project = "gate_prj"
syn_tool = "quartus"
files = [ "../files/gate.vhdl" ]
testsuite/040srcfiles/Makefile.ref 0 → 100644
View file @ 27255e5c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := mod2
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).xise
TOOL_PATH :=
TCL_INTERPRETER := xtclsh
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Spartan6
SYN_DEVICE := xc6slx45t
SYN_PACKAGE := fgg484
SYN_GRADE := -3
TCL_CREATE := project new $(PROJECT_FILE)
TCL_OPEN := project open $(PROJECT_FILE)
TCL_SAVE := project save
TCL_CLOSE := project close
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_SVFile := \
f2.sv
files.tcl:
@$(foreach sourcefile, $(SOURCES_SVFile), echo "xfile add $(sourcefile)" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_TRANSLATE_CMD :=
SYN_POST_TRANSLATE_CMD :=
SYN_PRE_MAP_CMD :=
SYN_POST_MAP_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo xfile remove [search \* -type file] >> $@
echo source files.tcl >> $@
echo project set \"family\" \"$(SYN_FAMILY)\" >> $@
echo project set \"device\" \"$(SYN_DEVICE)\" >> $@
echo project set \"package\" \"$(SYN_PACKAGE)\" >> $@
echo project set \"speed\" \"$(SYN_GRADE)\" >> $@
echo project set \"Manual Implementation Compile Order\" \"false\" >> $@
echo project set \"Auto Implementation Top\" \"false\" >> $@
echo project set \"Create Binary Configuration File\" \"true\" >> $@
echo set compile_directory . >> $@
echo project set top $(TOP_MODULE) >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Synthesize - XST} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
translate.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Translate} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
translate: synthesize translate.tcl
$(SYN_PRE_TRANSLATE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_TRANSLATE_CMD)
touch $@
map.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Map} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
map: translate map.tcl
$(SYN_PRE_MAP_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_MAP_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Place '&' Route} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
par: map par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo set process {Generate Programming File} >> $@
echo process run '$$'process >> $@
echo set result [process get '$$'process status] >> $@
echo if { '$$'result == \"errors\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_SAVE) >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) xst xlnx_auto_0_xdb iseconfig _xmsgs _ngo *.b *_summary.html *.bld *.cmd_log *.drc *.lso *.ncd *.ngc *.ngd *.ngr *.pad *.par *.pcf *.prj *.ptwx *.stx *.syr *.twr *.twx *.gise *.gise *.bgn *.unroutes *.ut *.xpi *.xst *.xise *.xwbt *_envsettings.html *_guide.ncd *_map.map *_map.mrp *_map.ncd *_map.ngm *_map.xrpt *_ngdbuild.xrpt *_pad.csv *_pad.txt *_par.xrpt *_summary.xml *_usage.xml *_xst.xrpt usage_statistics_webtalk.html webtalk.log par_usage_statistics.html webtalk_pn.xml
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.bit *.bin *.mcs
.PHONY: mrproper clean all
testsuite/040srcfiles/Manifest.py 0 → 100644
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action = "synthesis"
language = "vhdl"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "mod2"
syn_project = "gate.xise"
syn_tool = "ise"
files = [ "../files/gate.vhdl", "f2.sv",
's1.wb',
's2.tcl',
's3.qsys',
's4.edn',
's5.pdc']
testsuite/040srcfiles/f2.sv 0 → 100644
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module mod2;
logic v;
endmodule;
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