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Commit 28ecb151 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Clean the iverilog tool file: this need a revamp

parent 15814765
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hdlmake/tools/iverilog/iverilog.py
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......@@ -148,66 +148,3 @@ mrproper: clean
self.write(makefile_text_2)
# Below is the old makefile generator: I'll keep it for some time while testing
def generate_iverilog_makefile(self, fileset, top_module, modules_pool):
print('javi checkpoint 0')
from hdlmake.srcfile import VerilogFile
for f in top_module.incl_makefiles:
self.writeln("include " + f)
target_list = []
for vl in fileset.filter(VerilogFile):
rel_dir_path = os.path.dirname(vl.rel_path())
if rel_dir_path:
rel_dir_path = rel_dir_path + '/'
target_name = os.path.join(rel_dir_path+vl.purename)
target_list.append(target_name)
dependencies_string = ' '.join([f.rel_path() for f in vl.depends_on if (f.name != vl.name)])
include_dirs = list(set([os.path.dirname(f.rel_path()) for f in vl.depends_on if f.name.endswith("vh")]))
while "" in include_dirs:
include_dirs.remove("")
include_dir_string = " -I".join(include_dirs)
if include_dir_string:
include_dir_string = ' -I'+include_dir_string
self.writeln("VFLAGS_"+target_name+"="+include_dir_string)
self.writeln('# jd checkpoint')
self.writeln(target_name+"_deps = "+dependencies_string)
print('javi target_list', target_list)
sim_only_files = []
for m in modules_pool:
for f in m.sim_only_files:
sim_only_files.append(f.name)
print('javi sim_only_files', sim_only_files)
# bit file targets are those that are only used in simulation
bit_targets = []
for m in modules_pool:
bit_targets = bit_targets + list(m.bit_file_targets)
print('javi bit_targets', bit_targets)
for bt in bit_targets:
bt = bt.purename
bt_syn_deps = []
# This can perhaps be done faster (?)
for vl in fileset.filter(VerilogFile):
if vl.purename == bt:
for f in vl.depends_on:
if (f.name != vl.name and f.name not in sim_only_files):
bt_syn_deps.append(f)
self.writeln(bt+'syn_deps = '+ ' '.join([f.rel_path() for f in bt_syn_deps]))
if not os.path.exists("%s.ucf" % bt):
logging.warning("The file %s.ucf doesn't exist!" % bt)
self.writeln(bt+".bit:\t"+bt+".v $("+bt+"syn_deps) "+bt+".ucf")
part=(top_module.syn_device+'-'+
top_module.syn_package+
top_module.syn_grade)
self.writeln("\tPART="+part+" $(SYNTH) "+bt+" $^")
self.writeln("\tmv _xilinx/"+bt+".bit $@")
self.writeln("clean:")
self.writeln("\t\trm -f "+" ".join(target_list)+"\n\t\trm -rf _xilinx")
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