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Hdlmake
Commit 32cebda7 authored by Paweł Szostek's avatar Paweł Szostek
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remove a nasty bug in regex in VHDL parser

parent befa5a90
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hdlmake/vhdl_parser.py
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......@@ -109,7 +109,7 @@ class VHDLParser(DepParser):
import re
patterns = {
"use": "^ *use *(\w+) *\. *(\w+) *. *\w+ *;",
"use": "^ *use +(\w+) *\. *(\w+) *\. *\w+ *;",
"entity": "^ *entity +(\w+) +is +(port|generic)",
"package": "^ *package +(\w+) +is",
"arch_begin": "^ *architecture +(\w+) +of +(\w+) +is +",
......
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