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Commit 3e9257b0 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Fixing simulation with Icarus Verilog

parent 58e4552f
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Showing with 11 additions and 17 deletions
hdlmake/action/simulation.py
View file @ 3e9257b0
......@@ -27,6 +27,8 @@ import importlib
from hdlmake.dep_file import DepFile
import hdlmake.new_dep_solver as dep_solver
from hdlmake.srcfile import SourceFileFactory, SourceFileSet
from hdlmake.dependable_file import DependableFile
from .action import Action
......@@ -69,19 +71,15 @@ class GenerateSimulationMakefile(Action):
self.env.check_tool(tool_object)
self.env.check_general()
if self.env[path_key] is None and self.options.force is not True:
logging.error("Can't generate a " + name + " makefile. " + bin_name + " not found.")
sys.exit("Exiting")
logging.info("Generating " + name + " makefile for simulation.")
pool = self.modules_pool
top_module = pool.get_top_module()
fset = pool.build_file_set()
dep_files = fset.filter(DepFile)
#dep_solver.solve(dep_files)
tool_object.generate_simulation_makefile(dep_files, top_module)
self.modules_pool.build_file_set()
tool_object.generate_simulation_makefile(
self.modules_pool.hierarchy_solved,
self.modules_pool.get_top_module()
)
hdlmake/tools/iverilog/iverilog.py
View file @ 3e9257b0
......@@ -92,14 +92,10 @@ simulation:
for inc in top_module.include_dirs:
self.writeln("\t\techo \"+incdir+" + inc + "\" >> run.command")
for vl in fileset.filter(VerilogFile):
self.writeln("\t\techo \"" + vl.rel_path() + "\" >> run.command")
for vhdl in fileset.filter(VHDLFile):
self.writeln("\t\techo \"" + vhdl.rel_path() + "\" >> run.command")
for sv in fileset.filter(SVFile):
self.writeln("\t\techo \"" + sv.rel_path() + "\" >> run.command")
# The list starts from top_module: reverse!
fileset.reverse()
for f in fileset:
self.writeln("\t\techo \"" + f.rel_path() + "\" >> run.command")
makefile_tmplt_2 = string.Template("""
......
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