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Hdlmake
Commits
3ef43942
Commit
3ef43942
authored
Aug 02, 2016
by
Javier D. Garcia-Lasheras
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The method supported_files from tools is not longer required
parent
39977d46
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Showing
13 changed files
with
53 additions
and
133 deletions
+53
-133
synthesis.py
hdlmake/action/synthesis.py
+12
-6
active_hdl.py
hdlmake/tools/active_hdl.py
+2
-7
diamond.py
hdlmake/tools/diamond.py
+3
-11
ghdl.py
hdlmake/tools/ghdl.py
+3
-9
ise.py
hdlmake/tools/ise.py
+5
-17
isim.py
hdlmake/tools/isim.py
+3
-5
iverilog.py
hdlmake/tools/iverilog.py
+3
-6
libero.py
hdlmake/tools/libero.py
+3
-10
modelsim.py
hdlmake/tools/modelsim.py
+2
-4
planahead.py
hdlmake/tools/planahead.py
+4
-11
quartus.py
hdlmake/tools/quartus.py
+6
-24
riviera.py
hdlmake/tools/riviera.py
+2
-4
vivado.py
hdlmake/tools/vivado.py
+5
-19
No files found.
hdlmake/action/synthesis.py
View file @
3ef43942
...
...
@@ -237,13 +237,19 @@ end sdb_meta_pkg;""")
top_mod
=
self
.
get_top_module
()
fileset
=
self
.
build_file_set
(
top_mod
.
manifest_dict
[
"syn_top"
])
privative_files
=
tool_object
.
supported_files
(
self
.
build_complete_file_set
())
if
privative_files
:
logging
.
info
(
"Privative / non-parseable files detected:
%
s"
,
len
(
privative_files
))
fileset
.
add
(
privative_files
)
sup_files
=
self
.
build_complete_file_set
()
privative_files
=
[]
for
file_aux
in
sup_files
:
if
any
(
isinstance
(
file_aux
,
file_type
)
for
file_type
in
tool_object
.
SUPPORTED_FILES
):
privative_files
.
append
(
file_aux
)
if
len
(
privative_files
)
>
0
:
logging
.
info
(
"Detected
%
d supported files that are not parseable"
,
len
(
privative_files
))
fileset
.
add
(
privative_files
)
sff
=
SourceFileFactory
()
if
self
.
env
.
options
.
generate_project_vhd
:
...
...
hdlmake/tools/active_hdl.py
View file @
3ef43942
...
...
@@ -24,6 +24,7 @@
import
string
from
hdlmake.action
import
ActionMakefile
from
hdlmake.srcfile
import
VHDLFile
,
VerilogFile
,
SVFile
class
ToolActiveHDL
(
ActionMakefile
):
...
...
@@ -34,6 +35,7 @@ class ToolActiveHDL(ActionMakefile):
'windows_bin'
:
'vsimsa'
,
'linux_bin'
:
None
}
SUPPORTED_FILES
=
[]
def
__init__
(
self
):
super
(
ToolActiveHDL
,
self
)
.
__init__
()
...
...
@@ -41,12 +43,6 @@ class ToolActiveHDL(ActionMakefile):
def
detect_version
(
self
,
path
):
pass
def
supported_files
(
self
,
fileset
):
from
hdlmake.srcfile
import
SourceFileSet
sup_files
=
SourceFileSet
()
# Return an empty fileset
return
sup_files
def
_print_clean
(
self
,
top_module
):
self
.
writeln
(
"""
\
...
...
@@ -62,7 +58,6 @@ mrproper: clean
def
_print_sim_compilation
(
self
,
fileset
,
top_module
):
# TODO: ??
from
hdlmake.srcfile
import
VHDLFile
,
VerilogFile
,
SVFile
self
.
writeln
(
"simulation:"
)
...
...
hdlmake/tools/diamond.py
View file @
3ef43942
...
...
@@ -28,6 +28,7 @@ import logging
import
string
from
hdlmake.action
import
ActionMakefile
from
hdlmake.srcfile
import
VHDLFile
,
VerilogFile
,
SVFile
,
EDFFile
,
LPFFile
DIAMOND_STANDARD_LIBS
=
[
'ieee'
,
'std'
]
...
...
@@ -41,6 +42,8 @@ class ToolDiamond(ActionMakefile):
'linux_bin'
:
'diamondc'
,
'project_ext'
:
'ldf'
}
SUPPORTED_FILES
=
[
EDFFile
,
LPFFile
]
def
__init__
(
self
):
super
(
ToolDiamond
,
self
)
.
__init__
()
...
...
@@ -171,20 +174,9 @@ mrproper:
tmp
=
'prj_project open
\"
{0}
\"
'
self
.
header
=
tmp
.
format
(
self
.
filename
+
'.ldf'
)
def
supported_files
(
self
,
fileset
):
from
hdlmake.srcfile
import
EDFFile
,
LPFFile
,
SourceFileSet
sup_files
=
SourceFileSet
()
for
f
in
fileset
:
if
(
isinstance
(
f
,
EDFFile
))
or
(
isinstance
(
f
,
LPFFile
)):
sup_files
.
add
(
f
)
else
:
continue
return
sup_files
def
__emit_files
(
self
,
update
=
False
):
tmp
=
'prj_src {0}
\"
{1}
\"
'
ret
=
[]
from
hdlmake.srcfile
import
VHDLFile
,
VerilogFile
,
SVFile
,
EDFFile
,
LPFFile
for
f
in
self
.
files
:
line
=
''
if
isinstance
(
f
,
VHDLFile
)
or
isinstance
(
f
,
VerilogFile
)
or
isinstance
(
f
,
SVFile
)
or
isinstance
(
f
,
EDFFile
):
...
...
hdlmake/tools/ghdl.py
View file @
3ef43942
...
...
@@ -23,6 +23,7 @@
import
string
from
hdlmake.action
import
ActionMakefile
from
hdlmake.srcfile
import
VHDLFile
GHDL_STANDARD_LIBS
=
[
'ieee'
,
'std'
]
...
...
@@ -34,16 +35,14 @@ class ToolGHDL(ActionMakefile):
'windows_bin'
:
'ghdl'
,
'linux_bin'
:
'ghdl'
}
SUPPORTED_FILES
=
[]
def
__init__
(
self
):
super
(
ToolGHDL
,
self
)
.
__init__
()
def
detect_version
(
self
,
path
):
pass
def
supported_files
(
self
,
fileset
):
from
hdlmake.srcfile
import
SourceFileSet
sup_files
=
SourceFileSet
()
return
sup_files
def
_print_sim_options
(
self
,
top_module
):
if
top_module
.
manifest_dict
[
"ghdl_opt"
]:
...
...
@@ -70,16 +69,11 @@ mrproper: clean
def
_print_sim_compilation
(
self
,
fileset
,
top_module
):
# TODO: vhdl87 vs vhdl97 options
from
hdlmake.srcfile
import
VHDLFile
self
.
writeln
(
"simulation:"
)
self
.
writeln
(
"
\t\t
# Analyze sources"
)
for
vhdl
in
fileset
.
filter
(
VHDLFile
):
self
.
writeln
(
"
\t\t
ghdl -a "
+
vhdl
.
rel_path
())
self
.
writeln
()
self
.
writeln
(
"
\t\t
# Elaborate design"
)
self
.
writeln
(
"
\t\t
ghdl -e $(TOP_MODULE)"
)
self
.
writeln
()
...
...
hdlmake/tools/ise.py
View file @
3ef43942
...
...
@@ -29,6 +29,7 @@ import xml.parsers.expat
import
logging
import
re
import
os
import
sys
import
string
from
subprocess
import
Popen
,
PIPE
...
...
@@ -36,6 +37,8 @@ import hdlmake.new_dep_solver as dep_solver
from
hdlmake.action
import
ActionMakefile
from
hdlmake.util
import
path
as
path_mod
from
hdlmake.srcfile
import
(
UCFFile
,
VHDLFile
,
VerilogFile
,
CDCFile
,
NGCFile
,
SourceFileSet
)
XML_IMPL
=
xml
.
dom
.
minidom
.
getDOMImplementation
()
...
...
@@ -64,6 +67,8 @@ class ToolISE(ActionMakefile):
'linux_bin'
:
'ise'
,
'project_ext'
:
'xise'
}
SUPPORTED_FILES
=
[
UCFFile
,
CDCFile
,
NGCFile
]
def
__init__
(
self
):
super
(
ToolISE
,
self
)
.
__init__
()
self
.
props
=
{}
...
...
@@ -436,7 +441,6 @@ mrproper:
file_xml
=
open
(
filename
)
self
.
xml_doc
=
xml
.
dom
.
minidom
.
parse
(
file_xml
)
self
.
xml_project
=
self
.
xml_doc
.
getElementsByTagName
(
"project"
)[
0
]
import
sys
try
:
self
.
_parse_props
()
except
xml
.
parsers
.
expat
.
ExpatError
:
...
...
@@ -480,8 +484,6 @@ mrproper:
def
_output_files
(
self
,
node
):
"""Add the HDL design files to the Xilinx ISE Project"""
from
hdlmake.srcfile
import
(
UCFFile
,
VHDLFile
,
VerilogFile
,
CDCFile
,
NGCFile
)
for
file_aux
in
self
.
files
:
file_project
=
self
.
xml_doc
.
createElement
(
"file"
)
file_project
.
setAttribute
(
"xil_pn:name"
,
...
...
@@ -514,7 +516,6 @@ mrproper:
def
_output_bindings
(
self
,
node
):
"""Add ChipScope bindings to the Xilinx ISE project"""
from
hdlmake.srcfile
import
CDCFile
for
binding
in
[
file_aux
for
file_aux
in
self
.
files
if
isinstance
(
file_aux
,
CDCFile
)]:
binding_project
=
self
.
xml_doc
.
createElement
(
"binding"
)
...
...
@@ -592,19 +593,6 @@ mrproper:
top_element
.
appendChild
(
self
.
xml_bindings
)
top_element
.
appendChild
(
version
)
def
supported_files
(
self
,
fileset
):
"""Filter the non dependable but supported files"""
from
hdlmake.srcfile
import
UCFFile
,
CDCFile
,
NGCFile
,
SourceFileSet
sup_files
=
SourceFileSet
()
for
file_aux
in
fileset
:
if
((
isinstance
(
file_aux
,
UCFFile
))
or
(
isinstance
(
file_aux
,
NGCFile
))
or
(
isinstance
(
file_aux
,
CDCFile
))):
sup_files
.
add
(
file_aux
)
else
:
continue
return
sup_files
class
ISEProjectProperty
(
object
):
"""Class that serves as container for the Xilinx ISE project properties"""
...
...
hdlmake/tools/isim.py
View file @
3ef43942
...
...
@@ -33,6 +33,7 @@ import platform
from
hdlmake.util
import
path
as
path_mod
from
hdlmake.action
import
ActionMakefile
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
ISIM_STANDARD_LIBS
=
[
'std'
,
'ieee'
,
'ieee_proposed'
,
'vl'
,
'synopsys'
,
...
...
@@ -50,6 +51,8 @@ class ToolISim(ActionMakefile):
'windows_bin'
:
'isimgui'
,
'linux_bin'
:
'isimgui'
}
SUPPORTED_FILES
=
[]
def
__init__
(
self
):
super
(
ToolISim
,
self
)
.
__init__
()
...
...
@@ -68,10 +71,6 @@ class ToolISim(ActionMakefile):
return
None
return
isim_version
def
supported_files
(
self
,
fileset
):
from
hdlmake.srcfile
import
SourceFileSet
sup_files
=
SourceFileSet
()
return
sup_files
def
_print_sim_top
(
self
,
top_module
):
self
.
writeln
(
"""## variables #############################
...
...
@@ -103,7 +102,6 @@ mrproper: clean
def
_print_sim_compilation
(
self
,
fileset
,
top_module
):
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
make_preambule_p2
=
"""## rules #################################
simulation: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse
$(VERILOG_OBJ): $(LIB_IND) xilinxsim.ini
...
...
hdlmake/tools/iverilog.py
View file @
3ef43942
...
...
@@ -29,6 +29,7 @@ import logging
from
hdlmake.util
import
path
as
path_mod
from
hdlmake.action
import
ActionMakefile
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
IVERILOG_STANDARD_LIBS
=
[
'std'
,
'ieee'
,
'ieee_proposed'
,
'vl'
,
'synopsys'
,
...
...
@@ -46,6 +47,8 @@ class ToolIVerilog(ActionMakefile):
'windows_bin'
:
'iverilog'
,
'linux_bin'
:
'iverilog'
}
SUPPORTED_FILES
=
[]
def
__init__
(
self
):
super
(
ToolIVerilog
,
self
)
.
__init__
()
...
...
@@ -59,13 +62,7 @@ class ToolIVerilog(ActionMakefile):
version
=
iverilog
.
stdout
.
readlines
()[
0
]
.
strip
()
return
version
def
supported_files
(
self
,
fileset
):
from
hdlmake.srcfile
import
SourceFileSet
sup_files
=
SourceFileSet
()
return
sup_files
def
_print_sim_compilation
(
self
,
fileset
,
top_module
):
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
self
.
writeln
(
"simulation:"
)
...
...
hdlmake/tools/libero.py
View file @
3ef43942
...
...
@@ -28,6 +28,7 @@ import string
import
logging
from
hdlmake.action
import
ActionMakefile
from
hdlmake.srcfile
import
VHDLFile
,
VerilogFile
,
SDCFile
,
PDCFile
LIBERO_STANDARD_LIBS
=
[
'ieee'
,
'std'
]
...
...
@@ -42,6 +43,8 @@ class ToolLibero(ActionMakefile):
'linux_bin'
:
'libero'
,
'project_ext'
:
'prjx'
}
SUPPORTED_FILES
=
[
SDCFile
,
PDCFile
]
def
__init__
(
self
):
super
(
ToolLibero
,
self
)
.
__init__
()
...
...
@@ -171,7 +174,6 @@ mrproper:
synthesis_constraints
=
[]
compilation_constraints
=
[]
ret
=
[]
from
hdlmake.srcfile
import
VHDLFile
,
VerilogFile
,
SDCFile
,
PDCFile
# First stage: linking files
for
f
in
self
.
files
:
if
isinstance
(
f
,
VHDLFile
)
or
isinstance
(
f
,
VerilogFile
):
...
...
@@ -209,12 +211,3 @@ mrproper:
ret
.
append
(
line
)
return
(
'
\n
'
.
join
(
ret
))
+
'
\n
'
def
supported_files
(
self
,
fileset
):
from
hdlmake.srcfile
import
SDCFile
,
PDCFile
,
SourceFileSet
sup_files
=
SourceFileSet
()
for
f
in
fileset
:
if
(
isinstance
(
f
,
SDCFile
))
or
(
isinstance
(
f
,
PDCFile
)):
sup_files
.
add
(
f
)
else
:
continue
return
sup_files
hdlmake/tools/modelsim.py
View file @
3ef43942
...
...
@@ -40,6 +40,8 @@ class ToolModelsim(VsimMakefileWriter):
'windows_bin'
:
'vsim'
,
'linux_bin'
:
'vsim'
}
SUPPORTED_FILES
=
[]
def
__init__
(
self
):
super
(
ToolModelsim
,
self
)
.
__init__
()
...
...
@@ -55,10 +57,6 @@ class ToolModelsim(VsimMakefileWriter):
def
detect_version
(
self
,
path
):
pass
def
supported_files
(
self
,
fileset
):
from
hdlmake.srcfile
import
SourceFileSet
sup_files
=
SourceFileSet
()
return
sup_files
def
_print_sim_options
(
self
,
top_module
):
if
top_module
.
pool
.
env
[
"modelsim_path"
]:
...
...
hdlmake/tools/planahead.py
View file @
3ef43942
...
...
@@ -29,6 +29,8 @@ from string import Template
import
logging
from
hdlmake.action
import
ActionMakefile
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
UCFFile
,
NGCFile
,
XMPFile
,
XCOFile
)
PLANAHEAD_STANDARD_LIBS
=
[
'ieee'
,
'std'
]
...
...
@@ -43,6 +45,8 @@ class ToolPlanAhead(ActionMakefile):
'linux_bin'
:
'planAhead'
,
'project_ext'
:
'ppr'
}
SUPPORTED_FILES
=
[
UCFFile
,
NGCFile
,
XMPFile
,
XCOFile
]
def
__init__
(
self
):
super
(
ToolPlanAhead
,
self
)
.
__init__
()
...
...
@@ -221,7 +225,6 @@ mrproper:
def
__emit_files
(
self
):
tmp
=
"add_files -norecurse {0}"
ret
=
[]
from
hdlmake.srcfile
import
VHDLFile
,
VerilogFile
,
SVFile
,
UCFFile
,
NGCFile
,
XMPFile
,
XCOFile
for
f
in
self
.
files
:
if
isinstance
(
f
,
VHDLFile
)
or
isinstance
(
f
,
VerilogFile
)
or
isinstance
(
f
,
SVFile
)
or
isinstance
(
f
,
UCFFile
)
or
isinstance
(
f
,
NGCFile
)
or
isinstance
(
f
,
XMPFile
)
or
isinstance
(
f
,
XCOFile
):
line
=
tmp
.
format
(
f
.
rel_path
())
...
...
@@ -230,16 +233,6 @@ mrproper:
ret
.
append
(
line
)
return
(
'
\n
'
.
join
(
ret
))
+
'
\n
'
def
supported_files
(
self
,
fileset
):
from
hdlmake.srcfile
import
UCFFile
,
NGCFile
,
XMPFile
,
XCOFile
,
SourceFileSet
sup_files
=
SourceFileSet
()
for
f
in
fileset
:
if
(
isinstance
(
f
,
UCFFile
))
or
(
isinstance
(
f
,
NGCFile
))
or
(
isinstance
(
f
,
XMPFile
))
or
(
isinstance
(
f
,
XCOFile
)):
sup_files
.
add
(
f
)
else
:
continue
return
sup_files
class
_PlanAheadProjectProperty
:
...
...
hdlmake/tools/quartus.py
View file @
3ef43942
...
...
@@ -30,6 +30,9 @@ import logging
from
hdlmake
import
fetch
from
hdlmake.action
import
ActionMakefile
from
hdlmake.util
import
path
as
path_mod
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
SignalTapFile
,
SDCFile
,
QIPFile
,
QSYSFile
,
DPFFile
,
QSFFile
,
BSFFile
,
BDFFile
,
TDFFile
,
GDFFile
)
QUARTUS_STANDARD_LIBS
=
[
'altera'
,
'altera_mf'
,
'lpm'
,
'ieee'
,
'std'
]
...
...
@@ -44,6 +47,9 @@ class ToolQuartus(ActionMakefile):
'linux_bin'
:
'quartus'
,
'project_ext'
:
'qsf'
}
SUPPORTED_FILES
=
[
SignalTapFile
,
SDCFile
,
QIPFile
,
QSYSFile
,
DPFFile
,
QSFFile
,
BSFFile
,
BDFFile
,
TDFFile
,
GDFFile
]
def
__init__
(
self
):
self
.
_preflow
=
None
self
.
_postmodule
=
None
...
...
@@ -201,9 +207,6 @@ mrproper:
return
pre
+
'
\n
'
+
mod
+
'
\n
'
+
post
+
'
\n
'
def
__emit_files
(
self
):
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
SignalTapFile
,
SDCFile
,
QIPFile
,
QSYSFile
,
DPFFile
,
QSFFile
,
BSFFile
,
BDFFile
,
TDFFile
,
GDFFile
)
tmp
=
"set_global_assignment -name {0} {1}"
tmplib
=
tmp
+
" -library {2}"
ret
=
[]
...
...
@@ -242,27 +245,6 @@ mrproper:
ret
.
append
(
line
)
return
(
'
\n
'
.
join
(
ret
))
+
'
\n
'
def
supported_files
(
self
,
fileset
):
from
hdlmake.srcfile
import
SignalTapFile
,
SDCFile
,
QIPFile
,
QSYSFile
,
DPFFile
,
QSFFile
from
hdlmake.srcfile
import
BSFFile
,
BDFFile
,
TDFFile
,
GDFFile
,
SourceFileSet
sup_files
=
SourceFileSet
()
for
f
in
fileset
:
if
(
(
isinstance
(
f
,
SignalTapFile
))
or
(
isinstance
(
f
,
SDCFile
))
or
(
isinstance
(
f
,
QIPFile
))
or
(
isinstance
(
f
,
QSYSFile
))
or
(
isinstance
(
f
,
DPFFile
))
or
(
isinstance
(
f
,
QSFFile
))
or
(
isinstance
(
f
,
BSFFile
))
or
(
isinstance
(
f
,
BDFFile
))
or
(
isinstance
(
f
,
TDFFile
))
or
(
isinstance
(
f
,
GDFFile
))
):
sup_files
.
add
(
f
)
else
:
continue
return
sup_files
def
add_property
(
self
,
val
):
# don't save files (they are unneeded)
...
...
hdlmake/tools/riviera.py
View file @
3ef43942
...
...
@@ -68,6 +68,8 @@ class ToolRiviera(VsimMakefileWriter):
'windows_bin'
:
'vsim'
,
'linux_bin'
:
'vsim'
}
SUPPORTED_FILES
=
[]
def
__init__
(
self
):
super
(
ToolRiviera
,
self
)
.
__init__
()
self
.
vcom_flags
.
append
(
"-2008"
)
...
...
@@ -76,7 +78,3 @@ class ToolRiviera(VsimMakefileWriter):
def
detect_version
(
self
,
path
):
pass
def
supported_files
(
self
,
fileset
):
from
hdlmake.srcfile
import
SourceFileSet
sup_files
=
SourceFileSet
()
return
sup_files
hdlmake/tools/vivado.py
View file @
3ef43942
...
...
@@ -28,6 +28,8 @@ import string
import
logging
from
hdlmake.action
import
ActionMakefile
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
UCFFile
,
NGCFile
,
XMPFile
,
XCOFile
,
BDFile
,
TCLFile
)
VIVADO_STANDARD_LIBS
=
[
'ieee'
,
'std'
]
...
...
@@ -43,6 +45,9 @@ class ToolVivado(ActionMakefile):
'project_ext'
:
'xpr'
}
SUPPORTED_FILES
=
[
UCFFile
,
NGCFile
,
XMPFile
,
XCOFile
,
BDFile
,
TCLFile
]
def
__init__
(
self
):
super
(
ToolVivado
,
self
)
.
__init__
()
...
...
@@ -219,7 +224,6 @@ mrproper:
tmp
=
"add_files -norecurse {0}"
tcl
=
"source {0}"
ret
=
[]
from
hdlmake.srcfile
import
VHDLFile
,
VerilogFile
,
SVFile
,
UCFFile
,
NGCFile
,
XMPFile
,
XCOFile
,
BDFile
,
TCLFile
for
f
in
self
.
files
:
if
isinstance
(
f
,
VHDLFile
)
or
isinstance
(
f
,
VerilogFile
)
or
isinstance
(
f
,
SVFile
)
or
isinstance
(
f
,
UCFFile
)
or
isinstance
(
f
,
NGCFile
)
or
isinstance
(
f
,
XMPFile
)
or
isinstance
(
f
,
XCOFile
)
or
isinstance
(
f
,
BDFile
):
line
=
tmp
.
format
(
f
.
rel_path
())
...
...
@@ -230,24 +234,6 @@ mrproper:
ret
.
append
(
line
)
return
(
'
\n
'
.
join
(
ret
))
+
'
\n
'
def
supported_files
(
self
,
fileset
):
from
hdlmake.srcfile
import
UCFFile
,
NGCFile
,
XMPFile
,
XCOFile
from
hdlmake.srcfile
import
BDFile
,
TCLFile
,
SourceFileSet
sup_files
=
SourceFileSet
()
for
f
in
fileset
:
if
(
(
isinstance
(
f
,
UCFFile
))
or
(
isinstance
(
f
,
NGCFile
))
or
(
isinstance
(
f
,
XMPFile
))
or
(
isinstance
(
f
,
XCOFile
))
or
(
isinstance
(
f
,
BDFile
))
or
(
isinstance
(
f
,
TCLFile
))
):
sup_files
.
add
(
f
)
else
:
continue
return
sup_files
class
_VivadoProjectProperty
:
...
...
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