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Hdlmake
Commit 414f5740 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Refactor Vivado and PlanAhead so that they support the new project stage

parent c3d259de
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Showing with 35 additions and 21 deletions
hdlmake/tools/planahead.py
View file @ 414f5740
...@@ -48,8 +48,10 @@ class ToolPlanAhead(ToolXilinx): ...@@ -48,8 +48,10 @@ class ToolPlanAhead(ToolXilinx):
".Xil", "$(PROJECT).cache", "$(PROJECT).data", ".Xil", "$(PROJECT).cache", "$(PROJECT).data",
" $(PROJECT).runs", "$(PROJECT).ppr"]} " $(PROJECT).runs", "$(PROJECT).ppr"]}
TCL_CONTROLS = {'bitstream': 'launch_runs impl_1 -to_step Bitgen\n' TCL_CONTROLS = {'bitstream': '$(TCL_OPEN)\n'
'wait_on_run impl_1'} 'launch_runs impl_1 -to_step Bitgen\n'
'wait_on_run impl_1\n'
'$(TCL_CLOSE)'}
def __init__(self): def __init__(self):
super(ToolPlanAhead, self).__init__() super(ToolPlanAhead, self).__init__()
......
hdlmake/tools/vivado.py
View file @ 414f5740
...@@ -56,9 +56,11 @@ class ToolVivado(ToolXilinx, ToolSim): ...@@ -56,9 +56,11 @@ class ToolVivado(ToolXilinx, ToolSim):
"$(PROJECT).ip_user_files", "$(PROJECT_FILE)"], "$(PROJECT).ip_user_files", "$(PROJECT_FILE)"],
'mrproper': ["*.wdb"]} 'mrproper': ["*.wdb"]}
TCL_CONTROLS = {'bitstream': 'launch_runs impl_1 -to_step write_bitstream' TCL_CONTROLS = {'bitstream': '$(TCL_OPEN)\n'
'launch_runs impl_1 -to_step write_bitstream'
'\n' '\n'
'wait_on_run impl_1'} 'wait_on_run impl_1\n'
'$(TCL_CLOSE)'}
SIMULATOR_CONTROLS = {'vlog': 'xvlog $<', SIMULATOR_CONTROLS = {'vlog': 'xvlog $<',
'vhdl': 'xvhdl $<', 'vhdl': 'xvhdl $<',
......
hdlmake/tools/xilinx.py
View file @ 414f5740
...@@ -39,6 +39,8 @@ class ToolXilinx(ToolSyn): ...@@ -39,6 +39,8 @@ class ToolXilinx(ToolSyn):
CLEAN_TARGETS = {'mrproper': ["*.bit", "*.bin"]} CLEAN_TARGETS = {'mrproper': ["*.bit", "*.bin"]}
_XILINX_RUN = '''\ _XILINX_RUN = '''\
$(TCL_OPEN)
{1}
reset_run {0} reset_run {0}
launch_runs {0} launch_runs {0}
wait_on_run {0} wait_on_run {0}
...@@ -47,16 +49,20 @@ set keyword [lindex [split $$result " "] end] ...@@ -47,16 +49,20 @@ set keyword [lindex [split $$result " "] end]
if {{ $$keyword != "Complete!" }} {{ if {{ $$keyword != "Complete!" }} {{
puts "{0} failed" puts "{0} failed"
exit 1 exit 1
}}''' }}
$(TCL_CLOSE)'''
TCL_CONTROLS = {'create': 'create_project $(PROJECT) ./', TCL_CONTROLS = {'create': 'create_project $(PROJECT) ./',
'open': 'open_project $(PROJECT_FILE)', 'open': 'open_project $(PROJECT_FILE)',
'save': '',
'close': 'exit', 'close': 'exit',
'synthesize': _XILINX_RUN.format("synth_1"), 'project': '$(TCL_CREATE)\n'
'translate': '', '{0}\n'
'map': '', '$(TCL_FILES)\n'
'par': _XILINX_RUN.format("impl_1"), 'update_compile_order -fileset sources_1\n'
'update_compile_order -fileset sim_1\n'
'$(TCL_CLOSE)',
'synthesize': _XILINX_RUN,
'par': _XILINX_RUN,
'install_source': '$(PROJECT).runs/impl_1/$(SYN_TOP).bit'} 'install_source': '$(PROJECT).runs/impl_1/$(SYN_TOP).bit'}
def __init__(self): def __init__(self):
...@@ -74,8 +80,7 @@ if {{ $$keyword != "Complete!" }} {{ ...@@ -74,8 +80,7 @@ if {{ $$keyword != "Complete!" }} {{
syn_package = self.manifest_dict["syn_package"] syn_package = self.manifest_dict["syn_package"]
syn_top = self.manifest_dict["syn_top"] syn_top = self.manifest_dict["syn_top"]
syn_properties = self.manifest_dict.get("syn_properties") syn_properties = self.manifest_dict.get("syn_properties")
create_new = [] project_new = []
create_new.append(self._tcl_controls["create"])
synthesize_new = [] synthesize_new = []
par_new = [] par_new = []
properties = [ properties = [
...@@ -106,17 +111,24 @@ if {{ $$keyword != "Complete!" }} {{ ...@@ -106,17 +111,24 @@ if {{ $$keyword != "Complete!" }} {{
par_new.append(tmp.format( par_new.append(tmp.format(
prop[0], prop[1], 'get_runs impl_1')) prop[0], prop[1], 'get_runs impl_1'))
else: else:
create_new.append(tmp.format( project_new.append(tmp.format(
prop[0], prop[1], 'current_project')) prop[0], prop[1], 'current_project'))
elif len(prop) == 3: elif len(prop) == 3:
create_new.append(tmp.format(prop[0], prop[1], prop[2])) project_new.append(tmp.format(prop[0], prop[1], prop[2]))
else: else:
logging.error('Unknown project property: %s', prop[0]) logging.error('Unknown project property: %s', prop[0])
synthesize_new.append(self._tcl_controls["synthesize"]) tmp_dict = {}
par_new.append(self._tcl_controls["par"]) tmp_dict["project"] = self._tcl_controls["project"]
self._tcl_controls["create"] = "\n".join(create_new) tmp_dict["synthesize"] = self._tcl_controls["synthesize"]
self._tcl_controls["synthesize"] = "\n".join(synthesize_new) tmp_dict["par"] = self._tcl_controls["par"]
self._tcl_controls["par"] = "\n".join(par_new) self._tcl_controls["project"] = tmp_dict["project"].format(
"\n".join(project_new))
self._tcl_controls["synthesize"] = tmp_dict["synthesize"].format(
"synth_1",
"\n".join(synthesize_new))
self._tcl_controls["par"] = tmp_dict["par"].format(
"impl_1",
"\n".join(par_new))
super(ToolXilinx, self).makefile_syn_tcl() super(ToolXilinx, self).makefile_syn_tcl()
def makefile_syn_files(self): def makefile_syn_files(self):
...@@ -131,7 +143,5 @@ if {{ $$keyword != "Complete!" }} {{ ...@@ -131,7 +143,5 @@ if {{ $$keyword != "Complete!" }} {{
else: else:
self.writeln(tmp.format(file_aux.rel_path())) self.writeln(tmp.format(file_aux.rel_path()))
self.writeln(hack.format(file_aux.rel_path())) self.writeln(hack.format(file_aux.rel_path()))
self.writeln('update_compile_order -fileset sources_1')
self.writeln('update_compile_order -fileset sim_1')
self.writeln("endef") self.writeln("endef")
self.writeln("export TCL_FILES") self.writeln("export TCL_FILES")
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