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Projects
Hdlmake
Commits
44783c06
Commit
44783c06
authored
Aug 16, 2016
by
Javier D. Garcia-Lasheras
Browse files
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Python 3 support: code modified by Modernize Python tool
parent
5bf93f51
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38 changed files
with
432 additions
and
382 deletions
+432
-382
__main__.py
hdlmake/__main__.py
+1
-0
action.py
hdlmake/action/action.py
+1
-0
core.py
hdlmake/action/core.py
+8
-6
qsys_hw_tcl_update.py
hdlmake/action/qsys_hw_tcl_update.py
+1
-0
tree.py
hdlmake/action/tree.py
+1
-0
dep_file.py
hdlmake/dep_file.py
+7
-4
env.py
hdlmake/env.py
+4
-2
backend_factory.py
hdlmake/fetch/backend_factory.py
+3
-1
fetcher.py
hdlmake/fetch/fetcher.py
+1
-0
git.py
hdlmake/fetch/git.py
+1
-0
svn.py
hdlmake/fetch/svn.py
+1
-0
configparser.py
hdlmake/manifest_parser/configparser.py
+1
-0
manifest_parser.py
hdlmake/manifest_parser/manifest_parser.py
+1
-0
content.py
hdlmake/module/content.py
+3
-1
core.py
hdlmake/module/core.py
+1
-0
module.py
hdlmake/module/module.py
+3
-1
new_dep_solver.py
hdlmake/new_dep_solver.py
+1
-0
srcfile.py
hdlmake/srcfile.py
+365
-363
active_hdl.py
hdlmake/tools/active_hdl.py
+1
-0
diamond.py
hdlmake/tools/diamond.py
+1
-0
ghdl.py
hdlmake/tools/ghdl.py
+1
-0
ise.py
hdlmake/tools/ise.py
+1
-0
isim.py
hdlmake/tools/isim.py
+1
-0
iverilog.py
hdlmake/tools/iverilog.py
+1
-0
libero.py
hdlmake/tools/libero.py
+1
-0
make_sim.py
hdlmake/tools/make_sim.py
+1
-0
make_syn.py
hdlmake/tools/make_syn.py
+1
-0
makefile.py
hdlmake/tools/makefile.py
+1
-0
modelsim.py
hdlmake/tools/modelsim.py
+1
-0
planahead.py
hdlmake/tools/planahead.py
+1
-0
quartus.py
hdlmake/tools/quartus.py
+1
-0
sim_makefile_support.py
hdlmake/tools/sim_makefile_support.py
+4
-2
vivado.py
hdlmake/tools/vivado.py
+1
-0
xilinx.py
hdlmake/tools/xilinx.py
+1
-0
path.py
hdlmake/util/path.py
+1
-0
termcolor.py
hdlmake/util/termcolor.py
+3
-0
vhdl_parser.py
hdlmake/vhdl_parser.py
+1
-0
vlog_parser.py
hdlmake/vlog_parser.py
+4
-2
No files found.
hdlmake/__main__.py
View file @
44783c06
...
...
@@ -23,6 +23,7 @@
"""This is the entry point for HDLMake working in command line app mode"""
from
__future__
import
print_function
from
__future__
import
absolute_import
import
os
import
argparse
import
logging
...
...
hdlmake/action/action.py
View file @
44783c06
...
...
@@ -23,6 +23,7 @@
from
__future__
import
print_function
from
__future__
import
absolute_import
import
os
import
logging
from
subprocess
import
PIPE
,
Popen
...
...
hdlmake/action/core.py
View file @
44783c06
...
...
@@ -21,6 +21,8 @@
"""This module provides the core actions to the pool"""
from
__future__
import
absolute_import
from
__future__
import
print_function
import
logging
import
os
import
os.path
...
...
@@ -80,12 +82,12 @@ class ActionCore(Action):
delimiter
=
"
\n
"
else
:
delimiter
=
self
.
env
.
options
.
delimiter
print
delimiter
.
join
(
files_str
)
print
(
delimiter
.
join
(
files_str
)
)
def
_print_comment
(
self
,
message
):
"""Private method that prints a message to stdout if not terse"""
if
not
self
.
env
.
options
.
terse
:
print
message
print
(
message
)
def
_print_file_list
(
self
,
file_list
):
"""Print file list to standard out"""
...
...
@@ -93,8 +95,8 @@ class ActionCore(Action):
self
.
_print_comment
(
"# * This module has no files"
)
else
:
for
file_aux
in
file_list
:
print
"
%
s
\t
%
s"
%
(
path_mod
.
relpath
(
file_aux
.
path
),
"file"
)
print
(
"
%
s
\t
%
s"
%
(
path_mod
.
relpath
(
file_aux
.
path
),
"file"
)
)
def
list_modules
(
self
):
"""List the modules that are contained by the pool"""
...
...
@@ -122,8 +124,8 @@ class ActionCore(Action):
%
mod_aux
.
parent
.
url
)
else
:
self
.
_print_comment
(
"# * This is the root module"
)
print
"
%
s
\t
%
s"
%
(
path_mod
.
relpath
(
mod_aux
.
path
),
_convert_to_source_name
(
mod_aux
.
source
))
print
(
"
%
s
\t
%
s"
%
(
path_mod
.
relpath
(
mod_aux
.
path
),
_convert_to_source_name
(
mod_aux
.
source
))
)
if
self
.
env
.
options
.
withfiles
:
self
.
_print_file_list
(
mod_aux
.
files
)
self
.
_print_comment
(
"# MODULE END ->
%
s"
%
mod_aux
.
url
)
...
...
hdlmake/action/qsys_hw_tcl_update.py
View file @
44783c06
...
...
@@ -23,6 +23,7 @@
NOTE: This module is provided by the SKA telescope collaboration
and need a rework to fully fit into the HDLMake structure. """
from
__future__
import
absolute_import
import
hdlmake.new_dep_solver
as
dep_solver
import
os
import
shutil
...
...
hdlmake/action/tree.py
View file @
44783c06
...
...
@@ -21,6 +21,7 @@
"""Module providing graph funtionalities to HDLMake"""
from
__future__
import
absolute_import
from
hdlmake.util
import
path
import
logging
...
...
hdlmake/dep_file.py
View file @
44783c06
...
...
@@ -21,10 +21,13 @@
"""Module providing the Classes used to provide and handle dependable files"""
from
__future__
import
absolute_import
from
__future__
import
print_function
import
os
import
logging
from
.util
import
path
as
path_mod
import
six
class
DepRelation
(
object
):
...
...
@@ -104,7 +107,7 @@ class File(object):
def
__init__
(
self
,
path
,
module
=
None
):
self
.
path
=
path
assert
not
isinstance
(
module
,
basestring
)
assert
not
isinstance
(
module
,
six
.
string_types
)
self
.
module
=
module
@
property
...
...
@@ -166,7 +169,7 @@ class File(object):
def
show
(
self
):
"""Print the file path to stdout"""
print
self
.
path
print
(
self
.
path
)
def
extension
(
self
):
"""Method that gets the extension for the file instance"""
...
...
@@ -182,7 +185,7 @@ class DepFile(File):
def
__init__
(
self
,
file_path
,
module
):
from
hdlmake.module
import
Module
assert
isinstance
(
file_path
,
basestring
)
assert
isinstance
(
file_path
,
six
.
string_types
)
assert
isinstance
(
module
,
Module
)
File
.
__init__
(
self
,
path
=
file_path
,
module
=
module
)
self
.
file_path
=
file_path
...
...
@@ -233,7 +236,7 @@ class DepFile(File):
"""Print the file relations to stdout: can be used for logging"""
# self._parse_if_needed()
for
relation
in
self
.
rels
:
print
str
(
relation
)
print
(
str
(
relation
)
)
@
property
def
filename
(
self
):
...
...
hdlmake/env.py
View file @
44783c06
...
...
@@ -24,12 +24,14 @@
"""Package providing the bridge with the Host O.S. environment"""
from
__future__
import
print_function
from
__future__
import
absolute_import
import
os
import
sys
import
os.path
import
logging
from
.util
import
path
as
path_mod
import
six
class
Env
(
dict
):
...
...
@@ -56,7 +58,7 @@ class Env(dict):
if
path
is
not
None
:
return
os
.
path
.
exists
(
os
.
path
.
join
(
path
,
name
))
else
:
assert
isinstance
(
name
,
basestring
)
assert
isinstance
(
name
,
six
.
string_types
)
path
=
_get_path
(
name
)
return
len
(
path
)
>
0
...
...
@@ -98,7 +100,7 @@ class Env(dict):
"""Ask the Host O.S. for the value of an HDLMAKE_(name)
environmental variable"""
assert
not
name
.
startswith
(
"HDLMAKE_"
)
assert
isinstance
(
name
,
basestring
)
assert
isinstance
(
name
,
six
.
string_types
)
name
=
name
.
upper
()
return
os
.
environ
.
get
(
"HDLMAKE_
%
s"
%
name
)
name
=
name
.
upper
()
...
...
hdlmake/fetch/backend_factory.py
View file @
44783c06
...
...
@@ -21,8 +21,10 @@
"""Module providing the BackendFactory, a mechanism to create fetchers"""
from
__future__
import
absolute_import
import
logging
from
.constants
import
(
LOCAL
)
import
six
class
BackendFactory
(
object
):
...
...
@@ -48,7 +50,7 @@ class BackendFactory(object):
error_string
=
"No registered backend found for module: "
+
\
str
(
module
)
+
"
\n
"
+
\
"Registered backends are:
\n
"
for
backend_id
in
s
elf
.
backend_table
.
iterkeys
(
):
for
backend_id
in
s
ix
.
iterkeys
(
self
.
backend_table
):
error_string
+=
"
\t
%
d"
%
(
backend_id
)
logging
.
error
(
error_string
)
raise
...
...
hdlmake/fetch/fetcher.py
View file @
44783c06
...
...
@@ -21,6 +21,7 @@
"""Module providing the base class for the different code fetchers"""
from
__future__
import
absolute_import
import
os
from
hdlmake.util
import
path
as
path_utils
import
logging
...
...
hdlmake/fetch/git.py
View file @
44783c06
...
...
@@ -21,6 +21,7 @@
"""Module providing the stuff for handling Git repositories"""
from
__future__
import
absolute_import
import
os
from
hdlmake.util
import
path
as
path_utils
import
logging
...
...
hdlmake/fetch/svn.py
View file @
44783c06
...
...
@@ -21,6 +21,7 @@
"""Module providing the stuff for handling SVN repositories"""
from
__future__
import
absolute_import
import
os
import
logging
from
hdlmake.util
import
path
as
path_utils
...
...
hdlmake/manifest_parser/configparser.py
View file @
44783c06
...
...
@@ -22,6 +22,7 @@
"""Module providing the parser for HDLMake Manifest.py files"""
from
__future__
import
print_function
from
__future__
import
absolute_import
import
logging
import
os
import
sys
...
...
hdlmake/manifest_parser/manifest_parser.py
View file @
44783c06
...
...
@@ -22,6 +22,7 @@
"""Module providing the HDLMake Manifest and its associated parser"""
from
__future__
import
absolute_import
import
os
import
logging
...
...
hdlmake/module/content.py
View file @
44783c06
"""This provides the stuff related with the HDLMake module,
from files to required submodules"""
from
__future__
import
absolute_import
import
logging
from
hdlmake
import
fetch
from
hdlmake.util
import
path
as
path_mod
from
.core
import
ModuleCore
import
six
class
ModuleContent
(
ModuleCore
):
...
...
@@ -104,7 +106,7 @@ class ModuleContent(ModuleCore):
"""Get the extra makefiles defined in the HDLMake module"""
# Included Makefiles
included_makefiles_aux
=
[]
if
isinstance
(
self
.
manifest_dict
[
"incl_makefiles"
],
basestring
):
if
isinstance
(
self
.
manifest_dict
[
"incl_makefiles"
],
six
.
string_types
):
included_makefiles_aux
.
append
(
self
.
manifest_dict
[
"incl_makefiles"
])
else
:
# list
included_makefiles_aux
=
self
.
manifest_dict
[
"incl_makefiles"
][:]
...
...
hdlmake/module/core.py
View file @
44783c06
"""Provides the core functionality for the HDLMake module"""
from
__future__
import
absolute_import
import
os
import
sys
import
logging
...
...
hdlmake/module/module.py
View file @
44783c06
...
...
@@ -28,12 +28,14 @@ specific parent modules providing specific methods and attributes.
"""
from
__future__
import
print_function
from
__future__
import
absolute_import
import
os
import
logging
from
hdlmake.util
import
path
as
path_mod
from
hdlmake.manifest_parser
import
ManifestParser
from
.content
import
ModuleContent
import
six
class
ModuleArgs
(
object
):
...
...
@@ -137,7 +139,7 @@ class Module(ModuleContent):
# Include dirs
include_dirs
=
[]
if
self
.
manifest_dict
[
"include_dirs"
]
is
not
None
:
if
isinstance
(
self
.
manifest_dict
[
"include_dirs"
],
basestring
):
if
isinstance
(
self
.
manifest_dict
[
"include_dirs"
],
six
.
string_types
):
dir_list
=
path_mod
.
compose
(
self
.
path
,
self
.
manifest_dict
[
"include_dirs"
])
include_dirs
.
append
(
dir_list
)
...
...
hdlmake/new_dep_solver.py
View file @
44783c06
...
...
@@ -24,6 +24,7 @@
HDLMake filesets"""
from
__future__
import
print_function
from
__future__
import
absolute_import
import
logging
from
.dep_file
import
DepFile
...
...
hdlmake/srcfile.py
View file @
44783c06
This diff is collapsed.
Click to expand it.
hdlmake/tools/active_hdl.py
View file @
44783c06
...
...
@@ -23,6 +23,7 @@
"""Module providing support for Aldec Active-HDL simulator"""
from
__future__
import
absolute_import
from
.make_sim
import
ToolSim
from
hdlmake.srcfile
import
VHDLFile
,
VerilogFile
,
SVFile
...
...
hdlmake/tools/diamond.py
View file @
44783c06
...
...
@@ -24,6 +24,7 @@
"""Module providing support for Lattice Diamond IDE"""
from
__future__
import
absolute_import
from
.make_syn
import
ToolSyn
from
hdlmake.srcfile
import
EDFFile
,
LPFFile
,
VHDLFile
,
VerilogFile
...
...
hdlmake/tools/ghdl.py
View file @
44783c06
...
...
@@ -23,6 +23,7 @@
"""Module providing support for GHDL simulator"""
from
__future__
import
absolute_import
import
string
from
.make_sim
import
ToolSim
...
...
hdlmake/tools/ise.py
View file @
44783c06
...
...
@@ -24,6 +24,7 @@
"""Module providing the classes that are used to handle Xilinx ISE"""
from
__future__
import
print_function
from
__future__
import
absolute_import
import
logging
from
.make_syn
import
ToolSyn
...
...
hdlmake/tools/isim.py
View file @
44783c06
...
...
@@ -25,6 +25,7 @@
"""Module providing support for Xilinx ISim simulator"""
from
__future__
import
absolute_import
import
os
import
os.path
import
logging
...
...
hdlmake/tools/iverilog.py
View file @
44783c06
...
...
@@ -23,6 +23,7 @@
"""Module providing support for IVerilog (Icarus Verilog) simulator"""
from
__future__
import
absolute_import
import
string
from
.make_sim
import
ToolSim
...
...
hdlmake/tools/libero.py
View file @
44783c06
...
...
@@ -24,6 +24,7 @@
"""Module providing support for Microsemi Libero IDE synthesis"""
from
__future__
import
absolute_import
from
.make_syn
import
ToolSyn
from
hdlmake.srcfile
import
VHDLFile
,
VerilogFile
,
SDCFile
,
PDCFile
...
...
hdlmake/tools/make_sim.py
View file @
44783c06
"""Module providing the simulation functionality for writing Makefiles"""
from
__future__
import
absolute_import
import
os
import
sys
import
string
...
...
hdlmake/tools/make_syn.py
View file @
44783c06
"""Module providing the synthesis functionality for writing Makefiles"""
from
__future__
import
absolute_import
import
sys
import
logging
import
string
...
...
hdlmake/tools/makefile.py
View file @
44783c06
...
...
@@ -23,6 +23,7 @@
"""Module providing the core functionality for writing Makefiles"""
from
__future__
import
absolute_import
import
os
from
hdlmake.util
import
path
as
path_mod
...
...
hdlmake/tools/modelsim.py
View file @
44783c06
...
...
@@ -24,6 +24,7 @@
"""Module providing support for Mentor Modelsim simulation"""
from
__future__
import
print_function
from
__future__
import
absolute_import
import
os
from
.sim_makefile_support
import
VsimMakefileWriter
...
...
hdlmake/tools/planahead.py
View file @
44783c06
...
...
@@ -23,6 +23,7 @@
"""Module providing support for Xilinx PlanAhead synthesis"""
from
__future__
import
absolute_import
from
.xilinx
import
ToolXilinx
from
hdlmake.srcfile
import
(
UCFFile
,
NGCFile
,
XMPFile
,
XCOFile
)
...
...
hdlmake/tools/quartus.py
View file @
44783c06
...
...
@@ -23,6 +23,7 @@
"""Module providing support for Altera Quartus synthesis"""
from
__future__
import
absolute_import
import
os
import
sys
import
logging
...
...
hdlmake/tools/sim_makefile_support.py
View file @
44783c06
...
...
@@ -23,12 +23,14 @@
"""Module providing common stuff for Modelsim, Vsim... like simulators"""
from
__future__
import
absolute_import
import
os
import
string
from
.make_sim
import
ToolSim
from
hdlmake.util
import
path
as
path_mod
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
import
six
class
VsimMakefileWriter
(
ToolSim
):
...
...
@@ -77,7 +79,7 @@ class VsimMakefileWriter(ToolSim):
self
.
vcom_flags
.
append
(
top_module
.
manifest_dict
[
"vcom_opt"
])
self
.
vmap_flags
.
append
(
top_module
.
manifest_dict
[
"vmap_opt"
])
self
.
vsim_flags
.
append
(
top_module
.
manifest_dict
[
"vsim_opt"
])
for
var
,
value
in
s
elf
.
custom_variables
.
iteritems
(
):
for
var
,
value
in
s
ix
.
iteritems
(
self
.
custom_variables
):
self
.
writeln
(
"
%
s :=
%
s"
%
(
var
,
value
))
self
.
writeln
()
self
.
writeln
(
"VCOM_FLAGS :=
%
s"
%
(
' '
.
join
(
self
.
vcom_flags
)))
...
...
@@ -119,7 +121,7 @@ class VsimMakefileWriter(ToolSim):
' '
.
join
(
self
.
additional_deps
))
self
.
writeln
()
for
filename
,
filesource
in
s
elf
.
copy_rules
.
iteritems
(
):
for
filename
,
filesource
in
s
ix
.
iteritems
(
self
.
copy_rules
):
self
.
write
(
__create_copy_rule
(
filename
,
filesource
))
for
lib
in
libs
:
self
.
write
(
lib
+
path_mod
.
slash_char
()
+
"."
+
lib
+
":
\n
"
)
...
...
hdlmake/tools/vivado.py
View file @
44783c06
...
...
@@ -24,6 +24,7 @@
"""Module providing support for Xilinx Vivado synthesis"""
from
__future__
import
absolute_import
from
.xilinx
import
ToolXilinx
from
.make_sim
import
ToolSim
from
hdlmake.srcfile
import
(
UCFFile
,
NGCFile
,
XMPFile
,
...
...
hdlmake/tools/xilinx.py
View file @
44783c06
...
...
@@ -24,6 +24,7 @@
"""Module providing generic support for Xilinx synthesis tools"""
from
__future__
import
absolute_import
from
.make_syn
import
ToolSyn
from
hdlmake.srcfile
import
VHDLFile
,
VerilogFile
,
SVFile
,
TCLFile
...
...
hdlmake/util/path.py
View file @
44783c06
...
...
@@ -23,6 +23,7 @@
"""This module provides a set of functions that are commonly used in HDLMake"""
from
__future__
import
print_function
from
__future__
import
absolute_import
import
os
import
sys
import
logging
...
...
hdlmake/util/termcolor.py
View file @
44783c06
...
...
@@ -24,7 +24,10 @@
"""ANSII Color formatting for output in terminal."""
from
__future__
import
print_function
from
__future__
import
absolute_import
import
os
from
six.moves
import
range
from
six.moves
import
zip
__ALL__
=
[
'colored'
,
'cprint'
]
...
...
hdlmake/vhdl_parser.py
View file @
44783c06
...
...
@@ -23,6 +23,7 @@
"""Module providing the VHDL parser capabilities"""
from
__future__
import
absolute_import
import
logging
import
re
...
...
hdlmake/vlog_parser.py
View file @
44783c06
...
...
@@ -26,6 +26,7 @@
"""This module provides the Verilog parser for HDLMake"""
from
__future__
import
print_function
from
__future__
import
absolute_import
import
os
import
re
import
sys
...
...
@@ -34,6 +35,7 @@ import logging
from
.new_dep_solver
import
DepParser
from
.dep_file
import
DepRelation
from
hdlmake.srcfile
import
create_source_file
import
six
class
VerilogPreprocessor
(
object
):
...
...
@@ -202,7 +204,7 @@ class VerilogPreprocessor(object):
for
line
in
_degapize
(
buf
):
matches
=
{}
last
=
None
for
statement
,
stmt_regex
in
exps
.
iteritems
(
):
for
statement
,
stmt_regex
in
six
.
iteritems
(
exps
):
matches
[
statement
]
=
re
.
match
(
stmt_regex
,
line
)
if
matches
[
statement
]:
last
=
matches
[
statement
]
...
...
@@ -302,7 +304,7 @@ class VerilogPreprocessor(object):
"""Look for all of the defined preprocessor filedeps and return a list
containing all of them"""
deps
=
[]
for
filedep_key
in
s
elf
.
vpp_filedeps
.
iterkeys
(
):
for
filedep_key
in
s
ix
.
iterkeys
(
self
.
vpp_filedeps
):
for
filedep
in
self
.
vpp_filedeps
[
filedep_key
]:
deps
.
append
(
filedep
)
return
list
(
set
(
deps
))
...
...
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