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Hdlmake
Commit 46d8a6f1 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Apply autopep8 --aggressive on recently modified simulation files

parent f32be4eb
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Showing with 1 addition and 19 deletions
hdlmake/action/makefile.py
View file @ 46d8a6f1
......@@ -154,7 +154,6 @@ sim_post_cmd:
self.writeln(sim_command.substitute(sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd))
def _print_clean(self, clean_targets):
"""Print the Makefile clean target"""
if platform.system() == 'Windows':
......@@ -174,13 +173,11 @@ sim_post_cmd:
self.writeln(tmp)
self.writeln()
def _print_sim_phony(self, top_module):
"""Print simulation PHONY target list to the Makefile"""
self.writeln(
".PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation")
def initialize(self):
"""Open the Makefile file and print a header if not initialized"""
if not self._initialized:
......
hdlmake/action/simulation.py
View file @ 46d8a6f1
......@@ -105,4 +105,3 @@ class ActionSimulation(
tool_object._print_sim_command(top_module)
tool_object._print_clean(tool_object.CLEAN_TARGETS)
tool_object._print_sim_phony(top_module)
hdlmake/tools/active_hdl.py
View file @ 46d8a6f1
......@@ -42,16 +42,13 @@ class ToolActiveHDL(ActionMakefile):
CLEAN_TARGETS = {'clean': ["run.command", "library.cfg", "work"],
'mrproper': ["*.vcd", "*.asdb"]}
def __init__(self):
super(ToolActiveHDL, self).__init__()
def detect_version(self, path):
"""Get the version from the Aldec-HDL binary program"""
pass
def _print_sim_compilation(self, fileset, top_module):
"""Print Makefile compilation target for Aldec Active-HDL simulator"""
self.writeln("simulation:")
......
hdlmake/tools/ghdl.py
View file @ 46d8a6f1
......@@ -45,7 +45,6 @@ class ToolGHDL(ActionMakefile):
CLEAN_TARGETS = {'clean': ["*.cf", "*.o", "$(TOP_MODULE)"],
'mrproper': ["*.vcd"]}
def __init__(self):
super(ToolGHDL, self).__init__()
......@@ -64,7 +63,6 @@ class ToolGHDL(ActionMakefile):
self.writeln(ghdl_string.substitute(
ghdl_opt=ghdl_opt))
def _print_sim_compilation(self, fileset, top_module):
"""Print the GDHL simulation compilation target"""
self.writeln("simulation:")
......
hdlmake/tools/isim.py
View file @ 46d8a6f1
......@@ -57,7 +57,7 @@ class ToolISim(ActionMakefile):
CLEAN_TARGETS = {'clean': ["./xilinxsim.ini $(LIBS)", "fuse.xmsgs",
"fuse.log", "fuseRelaunch.cmd", "isim",
"isim.log", "isim.wdb", "isim_proj",
"isim.log", "isim.wdb", "isim_proj",
"isim_proj.*"],
'mrproper': ["*.vcd"]}
......@@ -91,7 +91,6 @@ XILINX_INI_PATH := """ + self.__get_xilinxsim_ini_dir(top_module.pool.env) +
"""
""")
def _print_sim_options(self, top_module):
"""Print the Xilinx ISim simulation options in the Makefile"""
self.writeln("""VHPCOMP_FLAGS := -intstyle default \
......@@ -102,7 +101,6 @@ VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ +
top_module.manifest_dict["vlog_opt"]) + """
""")
def _print_sim_compilation(self, fileset, top_module):
"""Print the compile simulation target for Xilinx ISim"""
make_preambule_p2 = """## rules #################################
......
hdlmake/tools/iverilog.py
View file @ 46d8a6f1
......@@ -53,11 +53,9 @@ class ToolIVerilog(ActionMakefile):
CLEAN_TARGETS = {'clean': ["run.command", "ivl_vhdl_work"],
'mrproper': ["*.vcd", "*.vvp"]}
def __init__(self):
super(ToolIVerilog, self).__init__()
def detect_version(self, path):
"""Get version from Icarus Verilog program"""
is_windows = path_mod.check_windows()
......@@ -69,7 +67,6 @@ class ToolIVerilog(ActionMakefile):
version = iverilog.stdout.readlines()[0].strip()
return version
def _print_sim_compilation(self, fileset, top_module):
"""Generate compile simulation Makefile target for IVerilog"""
......@@ -107,4 +104,3 @@ class ToolIVerilog(ActionMakefile):
"""IVERILOG_OPT := ${iverilog_opt}\n""")
self.writeln(iverilog_string.substitute(
iverilog_opt=iverilog_opt))
hdlmake/tools/modelsim.py
View file @ 46d8a6f1
......@@ -69,4 +69,3 @@ class ToolModelsim(VsimMakefileWriter):
modelsim_ini_path = os.path.join("$(HDLMAKE_MODELSIM_PATH)", "..")
self.custom_variables["MODELSIM_INI_PATH"] = modelsim_ini_path
super(ToolModelsim, self)._print_sim_options(top_module)
hdlmake/tools/riviera.py
View file @ 46d8a6f1
......@@ -81,7 +81,6 @@ class ToolRiviera(VsimMakefileWriter):
super(ToolRiviera, self).__init__()
self.vcom_flags.append("-2008")
def detect_version(self, path):
"""Get version from Aldec Riviera-PRO binary program"""
pass
hdlmake/tools/sim_makefile_support.py
View file @ 46d8a6f1
......@@ -78,7 +78,6 @@ class VsimMakefileWriter(ActionMakefile):
self.writeln("VLOG_FLAGS := %s" % (' '.join(self.vlog_flags)))
self.writeln("VMAP_FLAGS := %s" % (' '.join(self.vmap_flags)))
def _print_sim_compilation(self, fileset, top_module):
"""Write a properly formatted Makefile for the simulator.
The Makefile format is shared, but flags, dependencies, clean rules,
......
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