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Commit 48504671 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Some refactoring in the simulation Makefile generation

parent 05aeb6f4
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Showing with 242 additions and 256 deletions
hdlmake/action/action.py
View file @ 48504671
...@@ -221,10 +221,7 @@ class Action(list): ...@@ -221,10 +221,7 @@ class Action(list):
"""Guess origin (git, svn, local) of a module at given path""" """Guess origin (git, svn, local) of a module at given path"""
cwd = self.top_module.path cwd = self.top_module.path
try: try:
if platform.system() == 'Windows': is_windows = path_mod.check_windows()
is_windows = True
else:
is_windows = False
os.chdir(path) os.chdir(path)
git_out = Popen("git config --get remote.origin.url", git_out = Popen("git config --get remote.origin.url",
stdout=PIPE, shell=True, close_fds=not is_windows) stdout=PIPE, shell=True, close_fds=not is_windows)
......
hdlmake/action/makefile.py
View file @ 48504671
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
"""Module providing the core functionality for writing Makefiles""" """Module providing the core functionality for writing Makefiles"""
import os import os
import string
from .action import Action from .action import Action
...@@ -44,6 +45,119 @@ class ActionMakefile(Action): ...@@ -44,6 +45,119 @@ class ActionMakefile(Action):
if self._file: if self._file:
self._file.close() self._file.close()
def _print_sim_top(self, top_module):
top_parameter = string.Template("""TOP_MODULE := ${top_module}\n
PWD := $$(shell pwd)""")
self.writeln(top_parameter.substitute(
top_module=top_module.manifest_dict["sim_top"]))
def _print_syn_top(self, top_module):
top_parameter = string.Template("""TOP_MODULE := ${top_module}\n
PWD := $$(shell pwd)""")
self.writeln(top_parameter.substitute(
top_module=top_module.manifest_dict["syn_top"]))
def _print_sim_local(self, top_module):
self.writeln("#target for performing local simulation\n"
"local: sim_pre_cmd simulation sim_post_cmd\n")
def _print_sim_sources(self, fileset):
from hdlmake.srcfile import VerilogFile, VHDLFile
self.write("VERILOG_SRC := ")
for vl in fileset.filter(VerilogFile):
self.write(vl.rel_path() + " \\\n")
self.write("\n")
self.write("VERILOG_OBJ := ")
for vl in fileset.filter(VerilogFile):
# make a file compilation indicator (these .dat files are made even if
# the compilation process fails) and add an ending according to file's
# extension (.sv and .vhd files may have the same corename and this
# causes a mess
self.write(
os.path.join(
vl.library,
vl.purename,
"." +
vl.purename +
"_" +
vl.extension(
)) +
" \\\n")
self.write('\n')
self.write("VHDL_SRC := ")
for vhdl in fileset.filter(VHDLFile):
self.write(vhdl.rel_path() + " \\\n")
self.writeln()
# list vhdl objects (_primary.dat files)
self.write("VHDL_OBJ := ")
for vhdl in fileset.filter(VHDLFile):
# file compilation indicator (important: add _vhd ending)
self.write(
os.path.join(
vhdl.library,
vhdl.purename,
"." +
vhdl.purename +
"_" +
vhdl.extension(
)) +
" \\\n")
self.write('\n')
def _print_syn_command(self, top_module):
if top_module.manifest_dict["syn_pre_cmd"]:
syn_pre_cmd = top_module.manifest_dict["syn_pre_cmd"]
else:
syn_pre_cmd = ''
if top_module.manifest_dict["syn_post_cmd"]:
syn_post_cmd = top_module.manifest_dict["syn_post_cmd"]
else:
syn_post_cmd = ''
syn_command = string.Template("""# USER SYN COMMANDS
syn_pre_cmd:
\t\t${syn_pre_cmd}
syn_post_cmd:
\t\t${syn_post_cmd}
""")
self.writeln(syn_command.substitute(syn_pre_cmd=syn_pre_cmd,
syn_post_cmd=syn_post_cmd))
def _print_sim_command(self, top_module):
if top_module.manifest_dict["sim_pre_cmd"]:
sim_pre_cmd = top_module.manifest_dict["sim_pre_cmd"]
else:
sim_pre_cmd = ''
if top_module.manifest_dict["sim_post_cmd"]:
sim_post_cmd = top_module.manifest_dict["sim_post_cmd"]
else:
sim_post_cmd = ''
sim_command = string.Template("""# USER SIM COMMANDS
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd:
\t\t${sim_post_cmd}
""")
self.writeln(sim_command.substitute(sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd))
def _print_sim_phony(self, top_module):
self.writeln(".PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation")
def initialize(self): def initialize(self):
"""Open the Makefile file and print a header if not initialized""" """Open the Makefile file and print a header if not initialized"""
if not self._initialized: if not self._initialized:
...@@ -75,3 +189,4 @@ class ActionMakefile(Action): ...@@ -75,3 +189,4 @@ class ActionMakefile(Action):
self.write("\n") self.write("\n")
else: else:
self.write(text + "\n") self.write(text + "\n")
hdlmake/action/simulation.py
View file @ 48504671
...@@ -97,5 +97,13 @@ class ActionSimulation( ...@@ -97,5 +97,13 @@ class ActionSimulation(
dep_files = fset.filter(DepFile) dep_files = fset.filter(DepFile)
#dep_solver.solve(dep_files) #dep_solver.solve(dep_files)
tool_object.generate_simulation_makefile(dep_files, top_module) #tool_object.generate_simulation_makefile(dep_files, top_module)
tool_object._print_sim_top(top_module)
tool_object._print_sim_options(top_module)
tool_object._print_sim_local(top_module)
tool_object._print_sim_sources(dep_files)
tool_object._print_sim_compilation(dep_files, top_module)
tool_object._print_sim_command(top_module)
tool_object._print_clean(top_module)
tool_object._print_sim_phony(top_module)
hdlmake/fetch/__init__.py
View file @ 48504671
...@@ -22,3 +22,5 @@ ...@@ -22,3 +22,5 @@
from .constants import (GIT, SVN, LOCAL, fetch_type_lookup) from .constants import (GIT, SVN, LOCAL, fetch_type_lookup)
from .git import Git from .git import Git
from .svn import Svn from .svn import Svn
from .backend_factory import BackendFactory
hdlmake/fetch/git.py
View file @ 48504671
...@@ -108,8 +108,7 @@ class Git(Fetcher): ...@@ -108,8 +108,7 @@ class Git(Fetcher):
commit = None commit = None
stderr = TemporaryFile() stderr = TemporaryFile()
try: try:
if platform.system() == 'Windows': is_windows = True is_windows = path.check_windows()
else: is_windows = False
os.chdir(path) os.chdir(path)
git_cmd = 'git log -1 --format="%H" | cut -c1-32' git_cmd = 'git log -1 --format="%H" | cut -c1-32'
git_out = Popen(git_cmd, git_out = Popen(git_cmd,
......
hdlmake/fetch/svn.py
View file @ 48504671
...@@ -69,8 +69,7 @@ class Svn(Fetcher): ...@@ -69,8 +69,7 @@ class Svn(Fetcher):
stderr = TemporaryFile() stderr = TemporaryFile()
try: try:
if platform.system() == 'Windows': is_windows = True is_windows = path.check_windows()
else: is_windows = False
os.chdir(path) os.chdir(path)
svn_cmd = "svn info 2>/dev/null | awk '{if(NR == 5) {print $2}}'" svn_cmd = "svn info 2>/dev/null | awk '{if(NR == 5) {print $2}}'"
svn_out = Popen(svn_cmd, shell=True, stdin=PIPE, stdout=PIPE, stderr=stderr, close_fds=not is_windows) svn_out = Popen(svn_cmd, shell=True, stdin=PIPE, stdout=PIPE, stderr=stderr, close_fds=not is_windows)
......
hdlmake/tools/ise.py
View file @ 48504671
...@@ -33,6 +33,7 @@ from subprocess import Popen, PIPE ...@@ -33,6 +33,7 @@ from subprocess import Popen, PIPE
import hdlmake.new_dep_solver as dep_solver import hdlmake.new_dep_solver as dep_solver
from hdlmake.action import ActionMakefile from hdlmake.action import ActionMakefile
from hdlmake.util import path as path_mod
XmlImpl = xml.dom.minidom.getDOMImplementation() XmlImpl = xml.dom.minidom.getDOMImplementation()
...@@ -70,10 +71,7 @@ class ToolISE(ActionMakefile): ...@@ -70,10 +71,7 @@ class ToolISE(ActionMakefile):
return ISE_STANDARD_LIBS return ISE_STANDARD_LIBS
def detect_version(self, path): def detect_version(self, path):
if platform.system() == 'Windows': is_windows = path_mod.check_windows()
is_windows = True
else:
is_windows = False
version_pattern = re.compile( version_pattern = re.compile(
'.*?(?P<major>\d|\d\d)[^\d](?P<minor>\d|\d\d).*') '.*?(?P<major>\d|\d\d)[^\d](?P<minor>\d|\d\d).*')
......
hdlmake/tools/isim.py
View file @ 48504671
...@@ -31,6 +31,7 @@ import sys ...@@ -31,6 +31,7 @@ import sys
import string import string
import platform import platform
from hdlmake.util import path as path_mod
from hdlmake.action import ActionMakefile from hdlmake.action import ActionMakefile
...@@ -59,10 +60,7 @@ class ToolISim(ActionMakefile): ...@@ -59,10 +60,7 @@ class ToolISim(ActionMakefile):
return ISIM_STANDARD_LIBS return ISIM_STANDARD_LIBS
def detect_version(self, path): def detect_version(self, path):
if platform.system() == 'Windows': is_windows = path_mod.check_windows()
is_windows = True
else:
is_windows = False
isim = Popen( isim = Popen(
"%s --version | awk '{print $2}'" % os.path.join(path, "vlogcomp"), "%s --version | awk '{print $2}'" % os.path.join(path, "vlogcomp"),
shell=True, shell=True,
...@@ -81,91 +79,50 @@ class ToolISim(ActionMakefile): ...@@ -81,91 +79,50 @@ class ToolISim(ActionMakefile):
sup_files = SourceFileSet() sup_files = SourceFileSet()
return sup_files return sup_files
def generate_simulation_makefile(self, fileset, top_module): def _print_sim_top(self, top_module):
from hdlmake.srcfile import VerilogFile, VHDLFile self.writeln("""## variables #############################
make_preambule_p1 = """## variables #############################
PWD := $(shell pwd) PWD := $(shell pwd)
TOP_MODULE := """ + top_module.manifest_dict["sim_top"] + """ TOP_MODULE := """ + top_module.manifest_dict["sim_top"] + """
FUSE_OUTPUT ?= isim_proj FUSE_OUTPUT ?= isim_proj
XILINX_INI_PATH := """ + self.__get_xilinxsim_ini_dir(top_module.pool.env) + """ XILINX_INI_PATH := """ + self.__get_xilinxsim_ini_dir(top_module.pool.env) + """
""")
VHPCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini def _print_sim_options(self, top_module):
self.writeln("""VHPCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
ISIM_FLAGS := ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ + self.__get_rid_of_isim_incdirs(top_module.manifest_dict["vlog_opt"]) + """ VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ + self.__get_rid_of_isim_incdirs(top_module.manifest_dict["vlog_opt"]) + """
""" """)
make_preambule_p2 = string.Template("""## rules #################################
local: sim_pre_cmd simulation sim_post_cmd
simulation: xilinxsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ) fuse
$$(VERILOG_OBJ): $$(LIB_IND) xilinxsim.ini
$$(VHDL_OBJ): $$(LIB_IND) xilinxsim.ini
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd:
\t\t${sim_post_cmd}
xilinxsim.ini: $$(XILINX_INI_PATH)/xilinxsim.ini
\t\tcp $$< .
fuse:
\t\tfuse work.$$(TOP_MODULE) -intstyle ise -incremental -o $$(FUSE_OUTPUT)
def _print_clean(self, top_module):
self.writeln("""\
#target for cleaning all intermediate stuff
clean: clean:
\t\trm -rf ./xilinxsim.ini $$(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log \ \t\trm -rf ./xilinxsim.ini $(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log \
isim.wdb isim_proj isim_proj.* isim.wdb isim_proj isim_proj.*
.PHONY: clean sim_pre_cmd sim_post_cmd simulation
#target for cleaning final files
mrproper: clean
""") """)
# open the file and write the above preambule (part 1)
self.write(make_preambule_p1)
self.write("VERILOG_SRC := ")
for vl in fileset.filter(VerilogFile):
self.write(vl.rel_path() + " \\\n")
self.write("\n")
self.write("VERILOG_OBJ := ")
for vl in fileset.filter(VerilogFile):
# make a file compilation indicator (these .dat files are made even if
# the compilation process fails) and add an ending according to file's
# extension (.sv and .vhd files may have the same corename and this
# causes a mess
self.write(
os.path.join(
vl.library,
vl.purename,
"." +
vl.purename +
"_" +
vl.extension(
)) +
" \\\n")
self.write('\n')
libs = set(f.library for f in fileset) def _print_sim_compilation(self, fileset, top_module):
from hdlmake.srcfile import VerilogFile, VHDLFile
make_preambule_p2 = """## rules #################################
simulation: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse
$(VERILOG_OBJ): $(LIB_IND) xilinxsim.ini
$(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
self.write("VHDL_SRC := ") xilinxsim.ini: $(XILINX_INI_PATH)/xilinxsim.ini
for vhdl in fileset.filter(VHDLFile): \t\tcp $< .
self.write(vhdl.rel_path() + " \\\n") fuse:
self.writeln() \t\tfuse work.$(TOP_MODULE) -intstyle ise -incremental -o $(FUSE_OUTPUT)
# list vhdl objects (_primary.dat files) """
self.write("VHDL_OBJ := ")
for vhdl in fileset.filter(VHDLFile): libs = set(f.library for f in fileset)
# file compilation indicator (important: add _vhd ending)
self.write(
os.path.join(
vhdl.library,
vhdl.purename,
"." +
vhdl.purename +
"_" +
vhdl.extension(
)) +
" \\\n")
self.write('\n')
self.write('LIBS := ') self.write('LIBS := ')
self.write(' '.join(libs)) self.write(' '.join(libs))
...@@ -175,20 +132,8 @@ isim.wdb isim_proj isim_proj.* ...@@ -175,20 +132,8 @@ isim.wdb isim_proj isim_proj.*
self.write(' '.join([lib + "/." + lib for lib in libs])) self.write(' '.join([lib + "/." + lib for lib in libs]))
self.write('\n') self.write('\n')
if top_module.manifest_dict["sim_pre_cmd"]:
sim_pre_cmd = top_module.manifest_dict["sim_pre_cmd"]
else:
sim_pre_cmd = ''
if top_module.manifest_dict["sim_post_cmd"]:
sim_post_cmd = top_module.manifest_dict["sim_post_cmd"]
else:
sim_post_cmd = ''
make_text_p2 = make_preambule_p2.substitute( self.writeln(make_preambule_p2)
sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd)
self.writeln(make_text_p2)
# ISim does not have a vmap command to insert additional libraries in # ISim does not have a vmap command to insert additional libraries in
#.ini file. #.ini file.
......
hdlmake/tools/iverilog.py
View file @ 48504671
...@@ -27,6 +27,7 @@ import os ...@@ -27,6 +27,7 @@ import os
import platform import platform
import logging import logging
from hdlmake.util import path as path_mod
from hdlmake.action import ActionMakefile from hdlmake.action import ActionMakefile
...@@ -55,10 +56,7 @@ class ToolIVerilog(ActionMakefile): ...@@ -55,10 +56,7 @@ class ToolIVerilog(ActionMakefile):
return IVERILOG_STANDARD_LIBS return IVERILOG_STANDARD_LIBS
def detect_version(self, path): def detect_version(self, path):
if platform.system() == 'Windows': is_windows = path_mod.check_windows()
is_windows = True
else:
is_windows = False
iverilog = Popen("iverilog -v 2>/dev/null| awk '{if(NR==1) print $4}'", iverilog = Popen("iverilog -v 2>/dev/null| awk '{if(NR==1) print $4}'",
shell=True, shell=True,
stdin=PIPE, stdin=PIPE,
...@@ -75,24 +73,18 @@ class ToolIVerilog(ActionMakefile): ...@@ -75,24 +73,18 @@ class ToolIVerilog(ActionMakefile):
def generate_simulation_makefile(self, fileset, top_module): def generate_simulation_makefile(self, fileset, top_module):
# TODO FLAGS: 2009 enables SystemVerilog (ongoing support) and partial # TODO FLAGS: 2009 enables SystemVerilog (ongoing support) and partial
# VHDL support # VHDL support
self._print_sim_top(top_module)
self._print_sim_options(top_module)
self._print_sim_local(top_module)
self._print_sim_compilation(fileset, top_module)
self._print_sim_command(top_module)
self._print_clean(top_module)
self._print_sim_phony(top_module)
def _print_sim_compilation(self, fileset, top_module):
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
makefile_tmplt_1 = string.Template("""TOP_MODULE := ${top_module} self.writeln("simulation:")
IVERILOG_CRAP := \
run.command \
ivl_vhdl_work
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
simulation:
""")
makefile_text_1 = makefile_tmplt_1.substitute(
top_module=top_module.manifest_dict["sim_top"]
)
self.write(makefile_text_1)
self.writeln( self.writeln(
"\t\techo \"# IVerilog command file, generated by HDLMake\" > run.command") "\t\techo \"# IVerilog command file, generated by HDLMake\" > run.command")
...@@ -109,44 +101,30 @@ simulation: ...@@ -109,44 +101,30 @@ simulation:
for sv in fileset.filter(SVFile): for sv in fileset.filter(SVFile):
self.writeln("\t\techo \"" + sv.rel_path() + "\" >> run.command") self.writeln("\t\techo \"" + sv.rel_path() + "\" >> run.command")
makefile_tmplt_2 = string.Template(""" self.writeln("""
\t\tiverilog ${iverilog_opt} -s $$(TOP_MODULE) -o $$(TOP_MODULE).vvp -c run.command \t\tiverilog $(IVERILOG_OPT) -s $(TOP_MODULE) -o $(TOP_MODULE).vvp -c run.command
sim_pre_cmd: """)
\t\t${sim_pre_cmd}
sim_post_cmd: def _print_sim_options(self, top_module):
\t\t${sim_post_cmd} if top_module.manifest_dict["iverilog_opt"]:
iverilog_opt = top_module.manifest_dict["iverilog_opt"]
else:
iverilog_opt = ''
iverilog_string = string.Template(
"""IVERILOG_OPT := ${iverilog_opt}\n""")
self.writeln(iverilog_string.substitute(
iverilog_opt=iverilog_opt))
def _print_clean(self, top_module):
self.writeln("""\
#target for cleaning all intermediate stuff #target for cleaning all intermediate stuff
clean: clean:
\t\trm -rf $$(IVERILOG_CRAP) \t\trm -rf run.command ivl_vhdl_work
#target for cleaning final files #target for cleaning final files
mrproper: clean mrproper: clean
\t\trm -f *.vcd *.vvp \t\trm -f *.vcd *.vvp
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
""") """)
if top_module.manifest_dict["iverilog_opt"]:
iverilog_opt = top_module.manifest_dict["iverilog_opt"]
else:
iverilog_opt = ''
if top_module.manifest_dict["sim_pre_cmd"]:
sim_pre_cmd = top_module.manifest_dict["sim_pre_cmd"]
else:
sim_pre_cmd = ''
if top_module.manifest_dict["sim_post_cmd"]:
sim_post_cmd = top_module.manifest_dict["sim_post_cmd"]
else:
sim_post_cmd = ''
makefile_text_2 = makefile_tmplt_2.substitute(
iverilog_opt=iverilog_opt,
sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd,
)
self.write(makefile_text_2)
hdlmake/tools/modelsim.py
View file @ 48504671
...@@ -44,9 +44,8 @@ class ToolModelsim(VsimMakefileWriter): ...@@ -44,9 +44,8 @@ class ToolModelsim(VsimMakefileWriter):
tool_info = { tool_info = {
'name': 'Modelsim', 'name': 'Modelsim',
'id': 'modelsim', 'id': 'modelsim',
'windows_bin': 'vsim',
'linux_bin': 'vsim'
} }
tool_info.update(super(ToolModelsim, self).get_keys())
return tool_info return tool_info
def get_standard_libraries(self): def get_standard_libraries(self):
...@@ -57,7 +56,7 @@ class ToolModelsim(VsimMakefileWriter): ...@@ -57,7 +56,7 @@ class ToolModelsim(VsimMakefileWriter):
sup_files = SourceFileSet() sup_files = SourceFileSet()
return sup_files return sup_files
def generate_simulation_makefile(self, fileset, top_module): def _print_sim_options(self, top_module):
self.vcom_flags.extend(["-modelsimini", "modelsim.ini"]) self.vcom_flags.extend(["-modelsimini", "modelsim.ini"])
self.vlog_flags.extend(["-modelsimini", "modelsim.ini"]) self.vlog_flags.extend(["-modelsimini", "modelsim.ini"])
self.vmap_flags.extend(["-modelsimini", "modelsim.ini"]) self.vmap_flags.extend(["-modelsimini", "modelsim.ini"])
...@@ -68,14 +67,16 @@ class ToolModelsim(VsimMakefileWriter): ...@@ -68,14 +67,16 @@ class ToolModelsim(VsimMakefileWriter):
else: else:
modelsim_ini_path = os.path.join("$(HDLMAKE_MODELSIM_PATH)", "..") modelsim_ini_path = os.path.join("$(HDLMAKE_MODELSIM_PATH)", "..")
self.custom_variables["MODELSIM_INI_PATH"] = modelsim_ini_path self.custom_variables["MODELSIM_INI_PATH"] = modelsim_ini_path
super(ToolModelsim, self)._print_sim_options(top_module)
def _print_sim_compilation(self, fileset, top_module):
self.copy_rules["modelsim.ini"] = os.path.join(
"$(MODELSIM_INI_PATH)", "modelsim.ini")
self.additional_deps.append("modelsim.ini") self.additional_deps.append("modelsim.ini")
super(ToolModelsim, self)._print_sim_compilation(fileset, top_module)
def _print_sim_clean(self, top_module):
self.additional_clean.extend( self.additional_clean.extend(
["./modelsim.ini", "transcript", "*.vcd", "*.wlf"]) ["./modelsim.ini", "transcript", "*.vcd", "*.wlf"])
super(ToolModelsim, self)._print_sim_clean(top_module)
self.copy_rules["modelsim.ini"] = os.path.join(
"$(MODELSIM_INI_PATH)", "modelsim.ini")
super(
ToolModelsim,
self).generate_simulation_makefile(
fileset,
top_module)
hdlmake/tools/riviera.py
View file @ 48504671
...@@ -74,9 +74,8 @@ class ToolRiviera(VsimMakefileWriter): ...@@ -74,9 +74,8 @@ class ToolRiviera(VsimMakefileWriter):
tool_info = { tool_info = {
'name': 'Riviera', 'name': 'Riviera',
'id': 'riviera', 'id': 'riviera',
'windows_bin': 'vsim',
'linux_bin': 'vsim'
} }
tool_info.update(super(ToolRiviera, self).get_keys())
return tool_info return tool_info
def get_standard_libraries(self): def get_standard_libraries(self):
......
hdlmake/tools/sim_makefile_support.py
View file @ 48504671
...@@ -60,35 +60,22 @@ class VsimMakefileWriter(ActionMakefile): ...@@ -60,35 +60,22 @@ class VsimMakefileWriter(ActionMakefile):
self.copy_rules = {} self.copy_rules = {}
super(VsimMakefileWriter, self).__init__() super(VsimMakefileWriter, self).__init__()
def generate_simulation_makefile(self, fileset, top_module):
"""Write a properly formatted Makefile for the simulator.
The Makefile format is shared, but flags, dependencies, clean rules, def get_keys(self):
etc are defined by the specific tool. tool_info = {
""" 'windows_bin': 'vsim',
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile 'linux_bin': 'vsim'
}
return tool_info
if platform.system() == 'Windows':
del_command = "rm -rf"
mkdir_command = "mkdir"
slash_char = "\\"
else:
del_command = "rm -rf"
mkdir_command = "mkdir -p"
slash_char = "/"
def _print_sim_options(self, top_module):
self.vlog_flags.append( self.vlog_flags.append(
self.__get_rid_of_vsim_incdirs(top_module.manifest_dict["vlog_opt"])) self.__get_rid_of_vsim_incdirs(top_module.manifest_dict["vlog_opt"]))
self.vcom_flags.append(top_module.manifest_dict["vcom_opt"]) self.vcom_flags.append(top_module.manifest_dict["vcom_opt"])
self.vmap_flags.append(top_module.manifest_dict["vmap_opt"]) self.vmap_flags.append(top_module.manifest_dict["vmap_opt"])
self.vsim_flags.append(top_module.manifest_dict["vsim_opt"]) self.vsim_flags.append(top_module.manifest_dict["vsim_opt"])
tmp = """## variables #############################
PWD := $(shell pwd)
"""
self.write(tmp)
self.writeln()
for var, value in self.custom_variables.iteritems(): for var, value in self.custom_variables.iteritems():
self.writeln("%s := %s" % (var, value)) self.writeln("%s := %s" % (var, value))
self.writeln() self.writeln()
...@@ -97,54 +84,40 @@ PWD := $(shell pwd) ...@@ -97,54 +84,40 @@ PWD := $(shell pwd)
self.writeln("VSIM_FLAGS := %s" % (' '.join(self.vsim_flags))) self.writeln("VSIM_FLAGS := %s" % (' '.join(self.vsim_flags)))
self.writeln("VLOG_FLAGS := %s" % (' '.join(self.vlog_flags))) self.writeln("VLOG_FLAGS := %s" % (' '.join(self.vlog_flags)))
self.writeln("VMAP_FLAGS := %s" % (' '.join(self.vmap_flags))) self.writeln("VMAP_FLAGS := %s" % (' '.join(self.vmap_flags)))
# self.writeln("INCLUDE_DIRS := +incdir+%s" %
# ('+'.join(top_module.include_dirs)))
self.write("VERILOG_SRC := ") def _print_clean(self, top_module):
for vl in fileset.filter(VerilogFile): if platform.system() == 'Windows':
self.write(vl.rel_path() + " \\\n") del_command = "rm -rf"
self.write("\n") else:
del_command = "rm -rf"
self.writeln("clean:")
tmp = "\t\t" + del_command + \
" $(LIBS) " + ' '.join(self.additional_clean)
self.writeln(tmp)
self.writeln("#target for cleaning final files")
self.writeln("mrproper: clean")
self.write("VERILOG_OBJ := ") def _print_sim_compilation(self, fileset, top_module):
for vl in fileset.filter(VerilogFile): """Write a properly formatted Makefile for the simulator.
# make a file compilation indicator (these .dat files are made even if
# the compilation process fails) and add an ending according to file's
# extension (.sv and .vhd files may have the same corename and this
# causes a mess
self.write(
os.path.join(
vl.library,
vl.purename,
"." +
vl.purename +
"_" +
vl.extension(
)) +
" \\\n")
self.write('\n')
libs = set(f.library for f in fileset) The Makefile format is shared, but flags, dependencies, clean rules,
etc are defined by the specific tool.
"""
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
self.write("VHDL_SRC := ") if platform.system() == 'Windows':
for vhdl in fileset.filter(VHDLFile): del_command = "rm -rf"
self.write(vhdl.rel_path() + " \\\n") mkdir_command = "mkdir"
self.writeln() slash_char = "\\"
else:
del_command = "rm -rf"
mkdir_command = "mkdir -p"
slash_char = "/"
# list vhdl objects (_primary.dat files) # self.writeln("INCLUDE_DIRS := +incdir+%s" %
self.write("VHDL_OBJ := ") # ('+'.join(top_module.include_dirs)))
for vhdl in fileset.filter(VHDLFile):
# file compilation indicator (important: add _vhd ending) libs = set(f.library for f in fileset)
self.write(
os.path.join(
vhdl.library,
vhdl.purename,
"." +
vhdl.purename +
"_" +
vhdl.extension(
)) +
" \\\n")
self.write('\n')
self.write('LIBS := ') self.write('LIBS := ')
self.write(' '.join(libs)) self.write(' '.join(libs))
...@@ -154,9 +127,6 @@ PWD := $(shell pwd) ...@@ -154,9 +127,6 @@ PWD := $(shell pwd)
self.write(' '.join([lib + slash_char + "." + lib for lib in libs])) self.write(' '.join([lib + slash_char + "." + lib for lib in libs]))
self.write('\n') self.write('\n')
self.writeln("## rules #################################")
self.writeln()
self.writeln("local: sim_pre_cmd simulation sim_post_cmd")
self.writeln() self.writeln()
self.writeln( self.writeln(
"simulation: %s $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)" % "simulation: %s $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)" %
...@@ -168,39 +138,9 @@ PWD := $(shell pwd) ...@@ -168,39 +138,9 @@ PWD := $(shell pwd)
self.additional_deps)) self.additional_deps))
self.writeln() self.writeln()
simcommands = string.Template("""sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd:
\t\t${sim_post_cmd}
""")
if top_module.manifest_dict["sim_pre_cmd"]:
sim_pre_cmd = top_module.manifest_dict["sim_pre_cmd"]
else:
sim_pre_cmd = ''
if top_module.manifest_dict["sim_post_cmd"]:
sim_post_cmd = top_module.manifest_dict["sim_post_cmd"]
else:
sim_post_cmd = ''
simcommands = simcommands.substitute(sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd)
self.write(simcommands)
self.writeln()
for filename, filesource in self.copy_rules.iteritems(): for filename, filesource in self.copy_rules.iteritems():
self.write(self.__create_copy_rule(filename, filesource)) self.write(self.__create_copy_rule(filename, filesource))
self.writeln("clean:")
tmp = "\t\t" + del_command + \
" $(LIBS) " + ' '.join(self.additional_clean)
self.writeln(tmp)
self.writeln(".PHONY: clean sim_pre_cmd sim_post_cmd simulation")
self.writeln()
for lib in libs: for lib in libs:
self.write(lib + slash_char + "." + lib + ":\n") self.write(lib + slash_char + "." + lib + ":\n")
vmap_command = "vmap $(VMAP_FLAGS)" vmap_command = "vmap $(VMAP_FLAGS)"
......
hdlmake/util/path.py
View file @ 48504671
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
from __future__ import print_function from __future__ import print_function
import os import os
import logging import logging
import platform
def url_parse(url): def url_parse(url):
""" """
...@@ -158,4 +158,9 @@ def flatten_list(sth): ...@@ -158,4 +158,9 @@ def flatten_list(sth):
sth = [] sth = []
return sth return sth
def check_windows():
if platform.system() == 'Windows':
return True
else:
return False
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