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Hdlmake
Commit 4b45eeb5 authored by Tristan Gingold's avatar Tristan Gingold
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sort files to have stable outputs.

parent 07ab445c
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Showing with 29 additions and 24 deletions
hdlmake/srcfile.py
View file @ 4b45eeb5
......@@ -369,6 +369,10 @@ class SourceFileSet(set):
out.add(file_aux)
return out
def sort(self):
"""Return a sorted list of the fileset. This is useful to have always
the same output"""
return sorted(self, key=(lambda x: x.file_path))
def create_source_file(path, module, library=None,
include_dirs=None, is_include=False):
......
hdlmake/tools/make_sim.py
View file @ 4b45eeb5
......@@ -70,12 +70,12 @@ PWD := $$(shell pwd)
"""Generic method to write the simulation Makefile HDL sources"""
fileset = self.fileset
self.write("VERILOG_SRC := ")
for vlog in fileset.filter(VerilogFile):
for vlog in fileset.filter(VerilogFile).sort():
if not vlog.is_include:
self.writeln(vlog.rel_path() + " \\")
self.writeln()
self.write("VERILOG_OBJ := ")
for vlog in fileset.filter(VerilogFile):
for vlog in fileset.filter(VerilogFile).sort():
if vlog.is_include:
continue
# make a file compilation indicator (these .dat files are made even
......@@ -94,12 +94,12 @@ PWD := $$(shell pwd)
" \\")
self.writeln()
self.write("VHDL_SRC := ")
for vhdl in fileset.filter(VHDLFile):
for vhdl in fileset.filter(VHDLFile).sort():
self.write(vhdl.rel_path() + " \\\n")
self.writeln()
# list vhdl objects (_primary.dat files)
self.write("VHDL_OBJ := ")
for vhdl in fileset.filter(VHDLFile):
for vhdl in fileset.filter(VHDLFile).sort():
# file compilation indicator (important: add _vhd ending)
self.writeln(
os.path.join(
......@@ -115,7 +115,7 @@ PWD := $$(shell pwd)
def _makefile_sim_dep_files(self):
"""Print dummy targets to handle file dependencies"""
fileset = self.fileset
fileset = self.fileset.sort()
for file_aux in fileset:
if any(isinstance(file_aux, file_type)
for file_type in self._hdl_files):
......@@ -124,8 +124,9 @@ PWD := $$(shell pwd)
".%s_%s" % (file_aux.purename, file_aux.extension())),
file_aux.rel_path()))
# list dependencies, do not include the target file
for dep_file in [dfile for dfile in file_aux.depends_on
if dfile is not file_aux]:
for dep_file in sorted([dfile for dfile in file_aux.depends_on
if dfile is not file_aux],
key=(lambda x: x.file_path)):
if dep_file in fileset:
name = dep_file.purename
extension = dep_file.extension()
......
hdlmake/tools/sim_makefile_support.py
View file @ 4b45eeb5
......@@ -129,7 +129,7 @@ class VsimMakefileWriter(ToolSim):
self.write(' '.join(["||", shell.del_command(), lib, "\n"]))
self.write('\n\n')
# rules for all _primary.dat files for sv
for vlog in fileset.filter(VerilogFile):
for vlog in fileset.filter(VerilogFile).sort():
if vlog.is_include:
continue
self.write("%s: %s" % (os.path.join(
......@@ -158,7 +158,7 @@ class VsimMakefileWriter(ToolSim):
self.writeln(" && " + shell.touch_command() + " $@ \n\n")
self.writeln()
# list rules for all _primary.dat files for vhdl
for vhdl in fileset.filter(VHDLFile):
for vhdl in fileset.filter(VHDLFile).sort():
lib = vhdl.library
purename = vhdl.purename
# each .dat depends on corresponding .vhd file
......
testsuite/025vlog_parser/Manifest.py
View file @ 4b45eeb5
......@@ -5,4 +5,4 @@ sim_tool="modelsim"
top_module = "gate"
include_dirs=["inc"]
files = [ "vlog.v" ]
files = [ "vlog.v", "unused.v" ]
testsuite/027vhdl_parser/Makefile.ref
View file @ 4b45eeb5
......@@ -17,11 +17,11 @@ local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := pkg.vhdl \
gate.vhdl \
VHDL_SRC := gate.vhdl \
pkg.vhdl \
VHDL_OBJ := work/pkg/.pkg_vhdl \
work/gate/.gate_vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
work/pkg/.pkg_vhdl \
INCLUDE_DIRS :=
LIBS := work
......@@ -37,13 +37,13 @@ work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/pkg/.pkg_vhdl: pkg.vhdl
work/gate/.gate_vhdl: gate.vhdl \
work/pkg/.pkg_vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/gate/.gate_vhdl: gate.vhdl \
work/pkg/.pkg_vhdl
work/pkg/.pkg_vhdl: pkg.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......
testsuite/052svlog_parser/Makefile.ref
View file @ 4b45eeb5
......@@ -15,11 +15,11 @@ VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := vlog.sv \
pkg.sv \
VERILOG_SRC := pkg.sv \
vlog.sv \
VERILOG_OBJ := work/vlog/.vlog_sv \
work/pkg/.pkg_sv \
VERILOG_OBJ := work/pkg/.pkg_sv \
work/vlog/.vlog_sv \
VHDL_SRC :=
VHDL_OBJ :=
......@@ -37,14 +37,14 @@ work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/vlog/.vlog_sv: vlog.sv \
work/pkg/.pkg_sv
work/pkg/.pkg_sv: pkg.sv
vlog -work work $(VLOG_FLAGS) -sv ${INCLUDE_DIRS} $<
@mkdir -p $(dir $@) && touch $@
work/pkg/.pkg_sv: pkg.sv
work/vlog/.vlog_sv: vlog.sv \
work/pkg/.pkg_sv
vlog -work work $(VLOG_FLAGS) -sv ${INCLUDE_DIRS} $<
@mkdir -p $(dir $@) && touch $@
......
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