Commit 51a8d5e7 authored by garcialasheras's avatar garcialasheras

Fix unexpected indent when importing src file types for Quartus

parent 57567601
......@@ -181,8 +181,9 @@ mrproper:
return pre+'\n'+mod+'\n'+post+'\n'
def __emit_files(self):
from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile, SignalTapFile, SDCFile, QIPFile, DPFFile,
QSFFile, BSFFile, BDFFile, TDFFile, GDFFile
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile,
SignalTapFile, SDCFile, QIPFile, DPFFile,
QSFFile, BSFFile, BDFFile, TDFFile, GDFFile)
tmp = "set_global_assignment -name {0} {1}"
tmplib = tmp + " -library {2}"
ret = []
......
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