testsuite: add tests for xci (json) and xcix

51f93bef · Tristan Gingold · 8db9f23d · 51f93bef · 51f93bef · 51f93bef
Commit 51f93bef authored Mar 10, 2023 by Tristan Gingold
9 changed files
--- a/testsuite/105xci_json/Makefile.ref
+++ b/testsuite/105xci_json/Makefile.ref
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+TOP_MODULE := xci_test
+PROJECT := xci_test
+PROJECT_FILE := $(PROJECT).xpr
+TOOL_PATH := 
+TCL_INTERPRETER := vivado -mode tcl -source
+ifneq ($(strip $(TOOL_PATH)),)
+TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
+endif
+
+SYN_FAMILY := 
+SYN_DEVICE := xc7a200t
+SYN_PACKAGE := ffg1156
+SYN_GRADE := -2
+
+TCL_CREATE := create_project $(PROJECT) ./
+TCL_OPEN := open_project $(PROJECT_FILE)
+TCL_CLOSE := exit
+ifneq ($(wildcard $(PROJECT_FILE)),)
+TCL_CREATE := $(TCL_OPEN)
+endif
+
+#target for performing local synthesis
+all: bitstream
+
+files.tcl:
+	@echo add_files -norecurse '{' >> $@
+	@echo 'adc_memory.xci' >> $@
+	@echo 'xci_test.vhd' >> $@
+	@echo '}' >> $@
+
+SYN_PRE_PROJECT_CMD := 
+SYN_POST_PROJECT_CMD := 
+
+SYN_PRE_SYNTHESIZE_CMD := 
+SYN_POST_SYNTHESIZE_CMD := 
+
+SYN_PRE_PAR_CMD := 
+SYN_POST_PAR_CMD := 
+
+SYN_PRE_BITSTREAM_CMD := 
+SYN_POST_BITSTREAM_CMD := 
+
+project.tcl:
+		echo $(TCL_CREATE) >> $@
+		echo # project properties >> $@
+		echo set_property "part" "$(SYN_DEVICE)$(SYN_PACKAGE)$(SYN_GRADE)" [current_project] >> $@
+		echo set_property "target_language" "vhdl" [current_project] >> $@
+		echo set_property "top" "$(TOP_MODULE)" [get_property srcset [current_run]] >> $@
+		echo source files.tcl >> $@
+		echo update_compile_order -fileset sources_1 >> $@
+		echo update_compile_order -fileset sim_1 >> $@
+		echo $(TCL_CLOSE) >> $@
+
+project: files.tcl project.tcl
+		$(SYN_PRE_PROJECT_CMD)
+		$(TCL_INTERPRETER) $@.tcl
+		$(SYN_POST_PROJECT_CMD)
+		touch $@
+
+synthesize.tcl:
+		echo $(TCL_OPEN) >> $@
+		echo # synthesize properties >> $@
+		echo reset_run synth_1 >> $@
+		echo launch_runs synth_1 >> $@
+		echo wait_on_run synth_1 >> $@
+		echo set result [get_property STATUS [get_runs synth_1]] >> $@
+		echo set complete [string match \"*Complete*\" '$$'result] >> $@
+		echo set timing [string match \"*Failed Timing*\" '$$'result] >> $@
+		echo if { ! '$$'complete } { >> $@
+		echo     exit 1 >> $@
+		echo } >> $@
+		echo if { '$$'timing '&&' 1 } { >> $@
+		echo     exit 1 >> $@
+		echo } >> $@
+		echo $(TCL_CLOSE) >> $@
+
+synthesize: project synthesize.tcl xci_test.vhd
+		$(SYN_PRE_SYNTHESIZE_CMD)
+		$(TCL_INTERPRETER) $@.tcl
+		$(SYN_POST_SYNTHESIZE_CMD)
+		touch $@
+
+par.tcl:
+		echo $(TCL_OPEN) >> $@
+		echo # par properties >> $@
+		echo reset_run impl_1 >> $@
+		echo launch_runs impl_1 >> $@
+		echo wait_on_run impl_1 >> $@
+		echo set result [get_property STATUS [get_runs impl_1]] >> $@
+		echo set complete [string match \"*Complete*\" '$$'result] >> $@
+		echo set timing [string match \"*Failed Timing*\" '$$'result] >> $@
+		echo if { ! '$$'complete } { >> $@
+		echo     exit 1 >> $@
+		echo } >> $@
+		echo if { '$$'timing '&&' 1 } { >> $@
+		echo     exit 1 >> $@
+		echo } >> $@
+		echo $(TCL_CLOSE) >> $@
+
+par: synthesize par.tcl
+		$(SYN_PRE_PAR_CMD)
+		$(TCL_INTERPRETER) $@.tcl
+		$(SYN_POST_PAR_CMD)
+		touch $@
+
+bitstream.tcl:
+		echo $(TCL_OPEN) >> $@
+		echo launch_runs impl_1 -to_step write_bitstream >> $@
+		echo wait_on_run impl_1 >> $@
+		echo $(TCL_CLOSE) >> $@
+
+bitstream: par bitstream.tcl
+		$(SYN_PRE_BITSTREAM_CMD)
+		$(TCL_INTERPRETER) $@.tcl
+		$(SYN_POST_BITSTREAM_CMD)
+		touch $@
+
+CLEAN_TARGETS := $(LIBS) .Xil *.jou *.log *.pb *.dmp $(PROJECT).cache $(PROJECT).data work $(PROJECT).runs $(PROJECT).hw $(PROJECT).sim $(PROJECT).ip_user_files $(PROJECT).srcs $(PROJECT_FILE)
+
+clean:
+		rm -rf $(CLEAN_TARGETS)
+		rm -rf project synthesize par bitstream
+		rm -rf project.tcl synthesize.tcl par.tcl bitstream.tcl files.tcl
+
+mrproper: clean
+		rm -rf *.bit *.bin
+
+.PHONY: mrproper clean all
--- a/testsuite/105xci_json/Manifest.py
+++ b/testsuite/105xci_json/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+syn_device = "xc7a200t"
+syn_grade = "-2"
+syn_package = "ffg1156"
+syn_top = "xci_test"
+syn_project = "xci_test"
+syn_tool = "vivado"
+
+files = [
+    "adc_memory.xci",
+    "xci_test.vhd",
+]
--- a/testsuite/105xci_json/adc_memory.xci
+++ b/testsuite/105xci_json/adc_memory.xci
--- a/testsuite/105xci_json/xci_test.vhd
+++ b/testsuite/105xci_json/xci_test.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity xci_test is
+  port(
+    clk_i: in std_logic;
+    data_o: out std_logic_vector(63 downto 0)
+    );
+end xci_test;
+
+architecture xci_test_arch of xci_test is
+begin
+  --  Incomplete...
+  cmp_adc_memory : entity work.adc_memory
+  port map (
+    clk_a      => clk_i,
+    clk_b      => clk_i
+    );
+end xci_test_arch;
--- a/testsuite/106xcix/Makefile.ref
+++ b/testsuite/106xcix/Makefile.ref
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+TOP_MODULE := xcix_test
+PROJECT := xcix_test
+PROJECT_FILE := $(PROJECT).xpr
+TOOL_PATH := 
+TCL_INTERPRETER := vivado -mode tcl -source
+ifneq ($(strip $(TOOL_PATH)),)
+TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
+endif
+
+SYN_FAMILY := 
+SYN_DEVICE := xc7a200t
+SYN_PACKAGE := ffg1156
+SYN_GRADE := -2
+
+TCL_CREATE := create_project $(PROJECT) ./
+TCL_OPEN := open_project $(PROJECT_FILE)
+TCL_CLOSE := exit
+ifneq ($(wildcard $(PROJECT_FILE)),)
+TCL_CREATE := $(TCL_OPEN)
+endif
+
+#target for performing local synthesis
+all: bitstream
+
+files.tcl:
+	@echo add_files -norecurse '{' >> $@
+	@echo 'adc_memory.xcix' >> $@
+	@echo 'xcix_test.vhd' >> $@
+	@echo '}' >> $@
+
+SYN_PRE_PROJECT_CMD := 
+SYN_POST_PROJECT_CMD := 
+
+SYN_PRE_SYNTHESIZE_CMD := 
+SYN_POST_SYNTHESIZE_CMD := 
+
+SYN_PRE_PAR_CMD := 
+SYN_POST_PAR_CMD := 
+
+SYN_PRE_BITSTREAM_CMD := 
+SYN_POST_BITSTREAM_CMD := 
+
+project.tcl:
+		echo $(TCL_CREATE) >> $@
+		echo # project properties >> $@
+		echo set_property "part" "$(SYN_DEVICE)$(SYN_PACKAGE)$(SYN_GRADE)" [current_project] >> $@
+		echo set_property "target_language" "vhdl" [current_project] >> $@
+		echo set_property "top" "$(TOP_MODULE)" [get_property srcset [current_run]] >> $@
+		echo source files.tcl >> $@
+		echo update_compile_order -fileset sources_1 >> $@
+		echo update_compile_order -fileset sim_1 >> $@
+		echo $(TCL_CLOSE) >> $@
+
+project: files.tcl project.tcl
+		$(SYN_PRE_PROJECT_CMD)
+		$(TCL_INTERPRETER) $@.tcl
+		$(SYN_POST_PROJECT_CMD)
+		touch $@
+
+synthesize.tcl:
+		echo $(TCL_OPEN) >> $@
+		echo # synthesize properties >> $@
+		echo reset_run synth_1 >> $@
+		echo launch_runs synth_1 >> $@
+		echo wait_on_run synth_1 >> $@
+		echo set result [get_property STATUS [get_runs synth_1]] >> $@
+		echo set complete [string match \"*Complete*\" '$$'result] >> $@
+		echo set timing [string match \"*Failed Timing*\" '$$'result] >> $@
+		echo if { ! '$$'complete } { >> $@
+		echo     exit 1 >> $@
+		echo } >> $@
+		echo if { '$$'timing '&&' 1 } { >> $@
+		echo     exit 1 >> $@
+		echo } >> $@
+		echo $(TCL_CLOSE) >> $@
+
+synthesize: project synthesize.tcl xcix_test.vhd
+		$(SYN_PRE_SYNTHESIZE_CMD)
+		$(TCL_INTERPRETER) $@.tcl
+		$(SYN_POST_SYNTHESIZE_CMD)
+		touch $@
+
+par.tcl:
+		echo $(TCL_OPEN) >> $@
+		echo # par properties >> $@
+		echo reset_run impl_1 >> $@
+		echo launch_runs impl_1 >> $@
+		echo wait_on_run impl_1 >> $@
+		echo set result [get_property STATUS [get_runs impl_1]] >> $@
+		echo set complete [string match \"*Complete*\" '$$'result] >> $@
+		echo set timing [string match \"*Failed Timing*\" '$$'result] >> $@
+		echo if { ! '$$'complete } { >> $@
+		echo     exit 1 >> $@
+		echo } >> $@
+		echo if { '$$'timing '&&' 1 } { >> $@
+		echo     exit 1 >> $@
+		echo } >> $@
+		echo $(TCL_CLOSE) >> $@
+
+par: synthesize par.tcl
+		$(SYN_PRE_PAR_CMD)
+		$(TCL_INTERPRETER) $@.tcl
+		$(SYN_POST_PAR_CMD)
+		touch $@
+
+bitstream.tcl:
+		echo $(TCL_OPEN) >> $@
+		echo launch_runs impl_1 -to_step write_bitstream >> $@
+		echo wait_on_run impl_1 >> $@
+		echo $(TCL_CLOSE) >> $@
+
+bitstream: par bitstream.tcl
+		$(SYN_PRE_BITSTREAM_CMD)
+		$(TCL_INTERPRETER) $@.tcl
+		$(SYN_POST_BITSTREAM_CMD)
+		touch $@
+
+CLEAN_TARGETS := $(LIBS) .Xil *.jou *.log *.pb *.dmp $(PROJECT).cache $(PROJECT).data work $(PROJECT).runs $(PROJECT).hw $(PROJECT).sim $(PROJECT).ip_user_files $(PROJECT).srcs $(PROJECT_FILE)
+
+clean:
+		rm -rf $(CLEAN_TARGETS)
+		rm -rf project synthesize par bitstream
+		rm -rf project.tcl synthesize.tcl par.tcl bitstream.tcl files.tcl
+
+mrproper: clean
+		rm -rf *.bit *.bin
+
+.PHONY: mrproper clean all
--- a/testsuite/106xcix/Manifest.py
+++ b/testsuite/106xcix/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+syn_device = "xc7a200t"
+syn_grade = "-2"
+syn_package = "ffg1156"
+syn_top = "xcix_test"
+syn_project = "xcix_test"
+syn_tool = "vivado"
+
+files = [
+    "adc_memory.xcix",
+    "xcix_test.vhd",
+]
--- a/testsuite/106xcix/adc_memory.xcix
+++ b/testsuite/106xcix/adc_memory.xcix
--- a/testsuite/106xcix/xcix_test.vhd
+++ b/testsuite/106xcix/xcix_test.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity xcix_test is
+  port(
+    clk_i: in std_logic;
+    data_o: out std_logic_vector(63 downto 0)
+    );
+end xcix_test;
+
+architecture xcix_test_arch of xcix_test is
+begin
+  --  Incomplete...
+  cmp_adc_memory : entity work.adc_memory
+  port map (
+    clk_a      => clk_i,
+    clk_b      => clk_i
+    );
+end xcix_test_arch;
--- a/testsuite/test_all.py
+++ b/testsuite/test_all.py
@@ -274,6 +274,12 @@ def test_xci023():
 def test_xci104():
    run_compare(path="104xci")

+def test_xci_json105():
+    run_compare(path="105xci_json")
+
+def test_xcix106():
+    run_compare(path="106xcix")
+
 def test_vlog_parser024():
    run_compare(path="024vlog_parser")