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Commit 5495d573 authored by Tristan Gingold's avatar Tristan Gingold
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makefilevsim: rework stamp files. 

This avoid mkdir errors on windows.
parent 5e6d6130
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Showing with 198 additions and 185 deletions
hdlmake/tools/makefilevsim.py
View file @ 5495d573
...@@ -90,13 +90,32 @@ class MakefileVsim(MakefileSim): ...@@ -90,13 +90,32 @@ class MakefileVsim(MakefileSim):
else: else:
return None return None
def get_stamp_library_dir(self, lib):
"""Return the directory that contains the stamp files"""
return os.path.join(lib, "hdlmake")
def get_stamp_library(self, lib):
"""Return the stamp file for :param lib: It must be a proper file
and not a directory (whose mtime is updated when a new file is created)"""
return os.path.join(self.get_stamp_library_dir(lib), lib + "-stamp")
def get_stamp_file(self, dep_file):
"""Stamp file for source file :param file:"""
return os.path.join(self.get_stamp_library_dir(dep_file.library),
"{}_{}".format(dep_file.purename, dep_file.extension()))
def _makefile_touch_stamp_file(self):
self.write("\t\t@" + shell.touch_command() + " $@\n")
def _makefile_sim_libraries(self, libs): def _makefile_sim_libraries(self, libs):
for lib in libs: for lib in libs:
libfile = self.get_stamp_library(lib) stampdir = self.get_stamp_library_dir(lib)
self.writeln("{}:".format(libfile)) stamplib = self.get_stamp_library(lib)
self.writeln("{}:".format(stamplib))
self.writeln("\t(vlib {lib} && vmap $(VMAP_FLAGS) {lib} " self.writeln("\t(vlib {lib} && vmap $(VMAP_FLAGS) {lib} "
"&& {touch} {libfile}) || {rm} {lib}".format( "&& {mkdir} {stampdir} && {touch} {stamplib}) || {rm} {lib}".format(
lib=lib, touch=shell.touch_command(), libfile=libfile, lib=lib, mkdir=shell.mkdir_command(), stampdir=stampdir,
touch=shell.touch_command(), stamplib=stamplib,
rm=shell.del_command())) rm=shell.del_command()))
self.writeln() self.writeln()
...@@ -121,5 +140,6 @@ class MakefileVsim(MakefileSim): ...@@ -121,5 +140,6 @@ class MakefileVsim(MakefileSim):
for filename, filesource in six.iteritems(self.copy_rules): for filename, filesource in six.iteritems(self.copy_rules):
self.writeln("{}: {}".format(filename, filesource)) self.writeln("{}: {}".format(filename, filesource))
self.writeln("\t\t{} $< . 2>&1".format(shell.copy_command())) self.writeln("\t\t{} $< . 2>&1".format(shell.copy_command()))
self.writeln()
self._makefile_sim_libraries(libs) self._makefile_sim_libraries(libs)
self._makefile_sim_dep_files() self._makefile_sim_dep_files()
testsuite/002msim/Makefile.ref
View file @ 5495d573
...@@ -18,11 +18,11 @@ VERILOG_SRC := ...@@ -18,11 +18,11 @@ VERILOG_SRC :=
VERILOG_OBJ := VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \ VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \ VHDL_OBJ := work/hdlmake/gate_vhdl \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl work/hdlmake/work-stamp:
vcom $(VCOM_FLAGS) -work work $< (vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
@mkdir -p $(dir $@) && touch $@
work/hdlmake/gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/003msim/Makefile.ref
View file @ 5495d573
...@@ -18,11 +18,11 @@ VERILOG_SRC := ...@@ -18,11 +18,11 @@ VERILOG_SRC :=
VERILOG_OBJ := VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \ VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \ VHDL_OBJ := work/hdlmake/gate_vhdl \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl work/hdlmake/work-stamp:
vcom $(VCOM_FLAGS) -work work $< (vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
@mkdir -p $(dir $@) && touch $@
work/hdlmake/gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/004msim/Makefile.ref
View file @ 5495d573
...@@ -18,11 +18,11 @@ VERILOG_SRC := ...@@ -18,11 +18,11 @@ VERILOG_SRC :=
VERILOG_OBJ := VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \ VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \ VHDL_OBJ := work/hdlmake/gate_vhdl \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl work/hdlmake/work-stamp:
vcom $(VCOM_FLAGS) -work work $< (vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
@mkdir -p $(dir $@) && touch $@
work/hdlmake/gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/017riviera/Makefile.ref
View file @ 5495d573
...@@ -17,23 +17,22 @@ VERILOG_SRC := ...@@ -17,23 +17,22 @@ VERILOG_SRC :=
VERILOG_OBJ := VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \ VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \ VHDL_OBJ := work/hdlmake/gate_vhdl \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): $(VERILOG_OBJ):
$(VHDL_OBJ): $(LIB_IND) $(VHDL_OBJ): $(LIB_IND)
work/.work: work/hdlmake/work-stamp:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work (vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl work/hdlmake/gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $< vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@ @touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/024vlog_parser/Makefile.ref
View file @ 5495d573
...@@ -16,13 +16,13 @@ local: sim_pre_cmd simulation sim_post_cmd ...@@ -16,13 +16,13 @@ local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := vlog.v \ VERILOG_SRC := vlog.v \
VERILOG_OBJ := work/vlog/.vlog_v \ VERILOG_OBJ := work/hdlmake/vlog_v \
VHDL_SRC := VHDL_SRC :=
VHDL_OBJ := VHDL_OBJ :=
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -30,14 +30,14 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -30,14 +30,14 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/vlog/.vlog_v: vlog.v \ work/hdlmake/work-stamp:
(vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
work/hdlmake/vlog_v: vlog.v \
macros.v macros.v
vlog -work work $(VLOG_FLAGS) $(INCLUDE_DIRS) $< vlog -work work $(VLOG_FLAGS) $(INCLUDE_DIRS) $<
@mkdir -p $(dir $@) && touch $@ @touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/025vlog_parser/Makefile.ref
View file @ 5495d573
...@@ -16,13 +16,13 @@ local: sim_pre_cmd simulation sim_post_cmd ...@@ -16,13 +16,13 @@ local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := vlog.v \ VERILOG_SRC := vlog.v \
VERILOG_OBJ := work/vlog/.vlog_v \ VERILOG_OBJ := work/hdlmake/vlog_v \
VHDL_SRC := VHDL_SRC :=
VHDL_OBJ := VHDL_OBJ :=
INCLUDE_DIRS := +incdir+inc INCLUDE_DIRS := +incdir+inc
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -30,14 +30,14 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -30,14 +30,14 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/vlog/.vlog_v: vlog.v \ work/hdlmake/work-stamp:
(vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
work/hdlmake/vlog_v: vlog.v \
inc/macros.v inc/macros.v
vlog -work work $(VLOG_FLAGS) $(INCLUDE_DIRS) $< vlog -work work $(VLOG_FLAGS) $(INCLUDE_DIRS) $<
@mkdir -p $(dir $@) && touch $@ @touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/027vhdl_parser/Makefile.ref
View file @ 5495d573
...@@ -19,12 +19,12 @@ VERILOG_OBJ := ...@@ -19,12 +19,12 @@ VERILOG_OBJ :=
VHDL_SRC := gate.vhdl \ VHDL_SRC := gate.vhdl \
pkg.vhdl \ pkg.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \ VHDL_OBJ := work/hdlmake/gate_vhdl \
work/pkg/.pkg_vhdl \ work/hdlmake/pkg_vhdl \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -32,19 +32,18 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -32,19 +32,18 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/gate/.gate_vhdl: gate.vhdl \
work/pkg/.pkg_vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/hdlmake/work-stamp:
(vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
work/pkg/.pkg_vhdl: pkg.vhdl work/hdlmake/gate_vhdl: gate.vhdl \
work/hdlmake/pkg_vhdl
vcom $(VCOM_FLAGS) -work work $< vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@ @touch $@
work/hdlmake/pkg_vhdl: pkg.vhdl
vcom $(VCOM_FLAGS) -work work $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/032manifest_vars/Makefile
View file @ 5495d573
...@@ -18,11 +18,11 @@ VERILOG_SRC := ...@@ -18,11 +18,11 @@ VERILOG_SRC :=
VERILOG_OBJ := VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \ VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \ VHDL_OBJ := work/hdlmake/gate_vhdl \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl work/hdlmake/work-stamp:
vcom $(VCOM_FLAGS) -work work $< (vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
@mkdir -p $(dir $@) && touch $@
work/hdlmake/gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/043local_fetch/Makefile.ref
View file @ 5495d573
...@@ -18,11 +18,11 @@ VERILOG_SRC := ...@@ -18,11 +18,11 @@ VERILOG_SRC :=
VERILOG_OBJ := VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \ VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \ VHDL_OBJ := work/hdlmake/gate_vhdl \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl work/hdlmake/work-stamp:
vcom $(VCOM_FLAGS) -work work $< (vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
@mkdir -p $(dir $@) && touch $@
work/hdlmake/gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/044files_dir/Makefile.ref
View file @ 5495d573
...@@ -18,11 +18,11 @@ VERILOG_SRC := ...@@ -18,11 +18,11 @@ VERILOG_SRC :=
VERILOG_OBJ := VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \ VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \ VHDL_OBJ := work/hdlmake/gate_vhdl \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl work/hdlmake/work-stamp:
vcom $(VCOM_FLAGS) -work work $< (vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
@mkdir -p $(dir $@) && touch $@
work/hdlmake/gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/045incl_makefile/Makefile.ref
View file @ 5495d573
...@@ -20,11 +20,11 @@ VERILOG_SRC := ...@@ -20,11 +20,11 @@ VERILOG_SRC :=
VERILOG_OBJ := VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \ VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \ VHDL_OBJ := work/hdlmake/gate_vhdl \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -32,13 +32,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -32,13 +32,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl work/hdlmake/work-stamp:
vcom $(VCOM_FLAGS) -work work $< (vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
@mkdir -p $(dir $@) && touch $@
work/hdlmake/gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/046incl_makefiles/Makefile.ref
View file @ 5495d573
...@@ -21,11 +21,11 @@ VERILOG_SRC := ...@@ -21,11 +21,11 @@ VERILOG_SRC :=
VERILOG_OBJ := VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \ VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \ VHDL_OBJ := work/hdlmake/gate_vhdl \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -33,13 +33,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -33,13 +33,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl work/hdlmake/work-stamp:
vcom $(VCOM_FLAGS) -work work $< (vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
@mkdir -p $(dir $@) && touch $@
work/hdlmake/gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/052svlog_parser/Makefile.ref
View file @ 5495d573
...@@ -17,14 +17,14 @@ local: sim_pre_cmd simulation sim_post_cmd ...@@ -17,14 +17,14 @@ local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := pkg.sv \ VERILOG_SRC := pkg.sv \
vlog.sv \ vlog.sv \
VERILOG_OBJ := work/pkg/.pkg_sv \ VERILOG_OBJ := work/hdlmake/pkg_sv \
work/vlog/.vlog_sv \ work/hdlmake/vlog_sv \
VHDL_SRC := VHDL_SRC :=
VHDL_OBJ := VHDL_OBJ :=
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -32,19 +32,18 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -32,19 +32,18 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/pkg/.pkg_sv: pkg.sv
vlog -work work $(VLOG_FLAGS) -sv $(INCLUDE_DIRS) $<
@mkdir -p $(dir $@) && touch $@
work/hdlmake/work-stamp:
(vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
work/vlog/.vlog_sv: vlog.sv \ work/hdlmake/pkg_sv: pkg.sv
work/pkg/.pkg_sv
vlog -work work $(VLOG_FLAGS) -sv $(INCLUDE_DIRS) $< vlog -work work $(VLOG_FLAGS) -sv $(INCLUDE_DIRS) $<
@mkdir -p $(dir $@) && touch $@ @touch $@
work/hdlmake/vlog_sv: vlog.sv \
work/hdlmake/pkg_sv
vlog -work work $(VLOG_FLAGS) -sv $(INCLUDE_DIRS) $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/057msim_windows/Makefile.ref
View file @ 5495d573
...@@ -18,11 +18,11 @@ VERILOG_SRC := ...@@ -18,11 +18,11 @@ VERILOG_SRC :=
VERILOG_OBJ := VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \ VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \ VHDL_OBJ := work/hdlmake/gate_vhdl \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work\.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
copy $< . 2>&1 copy $< . 2>&1
work\.work:
(vlib work && vmap $(VMAP_FLAGS) work && type nul >> work\.work) || del /s /q /f work
work/gate/.gate_vhdl: ../files/gate.vhdl work/hdlmake/work-stamp:
vcom $(VCOM_FLAGS) -work work $< (vlib work && vmap $(VMAP_FLAGS) work && mkdir work/hdlmake && type nul >> work/hdlmake/work-stamp) || del /s /q /f work
@mkdir $(dir $@) && type nul >> $@
work/hdlmake/gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@type nul >> $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/076extra_modules/Makefile.ref
View file @ 5495d573
...@@ -16,13 +16,13 @@ local: sim_pre_cmd simulation sim_post_cmd ...@@ -16,13 +16,13 @@ local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := ../files/gate_tb.v \ VERILOG_SRC := ../files/gate_tb.v \
VERILOG_OBJ := work/gate_tb/.gate_tb_v \ VERILOG_OBJ := work/hdlmake/gate_tb_v \
VHDL_SRC := VHDL_SRC :=
VHDL_OBJ := VHDL_OBJ :=
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/gate_tb/.gate_tb_v: ../files/gate_tb.v work/hdlmake/work-stamp:
vlog -work work $(VLOG_FLAGS) $(INCLUDE_DIRS) $< (vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
@mkdir -p $(dir $@) && touch $@
work/hdlmake/gate_tb_v: ../files/gate_tb.v
vlog -work work $(VLOG_FLAGS) $(INCLUDE_DIRS) $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/079err_vlg_macro/Makefile.ref
View file @ 5495d573
...@@ -16,13 +16,13 @@ local: sim_pre_cmd simulation sim_post_cmd ...@@ -16,13 +16,13 @@ local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := vlog.v \ VERILOG_SRC := vlog.v \
VERILOG_OBJ := work/vlog/.vlog_v \ VERILOG_OBJ := work/hdlmake/vlog_v \
VHDL_SRC := VHDL_SRC :=
VHDL_OBJ := VHDL_OBJ :=
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/vlog/.vlog_v: vlog.v work/hdlmake/work-stamp:
vlog -work work $(VLOG_FLAGS) $(INCLUDE_DIRS) $< (vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
@mkdir -p $(dir $@) && touch $@
work/hdlmake/vlog_v: vlog.v
vlog -work work $(VLOG_FLAGS) $(INCLUDE_DIRS) $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/081vlog_ifdef_elsif_else/Makefile.ref
View file @ 5495d573
...@@ -17,14 +17,14 @@ local: sim_pre_cmd simulation sim_post_cmd ...@@ -17,14 +17,14 @@ local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := mod_a.v \ VERILOG_SRC := mod_a.v \
vlog.v \ vlog.v \
VERILOG_OBJ := work/mod_a/.mod_a_v \ VERILOG_OBJ := work/hdlmake/mod_a_v \
work/vlog/.vlog_v \ work/hdlmake/vlog_v \
VHDL_SRC := VHDL_SRC :=
VHDL_OBJ := VHDL_OBJ :=
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -32,19 +32,18 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -32,19 +32,18 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/mod_a/.mod_a_v: mod_a.v
vlog -work work $(VLOG_FLAGS) $(INCLUDE_DIRS) $<
@mkdir -p $(dir $@) && touch $@
work/hdlmake/work-stamp:
(vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
work/vlog/.vlog_v: vlog.v \ work/hdlmake/mod_a_v: mod_a.v
work/mod_a/.mod_a_v
vlog -work work $(VLOG_FLAGS) $(INCLUDE_DIRS) $< vlog -work work $(VLOG_FLAGS) $(INCLUDE_DIRS) $<
@mkdir -p $(dir $@) && touch $@ @touch $@
work/hdlmake/vlog_v: vlog.v \
work/hdlmake/mod_a_v
vlog -work work $(VLOG_FLAGS) $(INCLUDE_DIRS) $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/087many_modules/Makefile.ref
View file @ 5495d573
...@@ -18,11 +18,11 @@ VERILOG_SRC := ...@@ -18,11 +18,11 @@ VERILOG_SRC :=
VERILOG_OBJ := VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \ VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \ VHDL_OBJ := work/hdlmake/gate_vhdl \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl work/hdlmake/work-stamp:
vcom $(VCOM_FLAGS) -work work $< (vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
@mkdir -p $(dir $@) && touch $@
work/hdlmake/gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/088bad_file_abs/Makefile.ref
View file @ 5495d573
...@@ -18,11 +18,11 @@ VERILOG_SRC := ...@@ -18,11 +18,11 @@ VERILOG_SRC :=
VERILOG_OBJ := VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \ VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \ VHDL_OBJ := work/hdlmake/gate_vhdl \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -30,13 +30,13 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl work/hdlmake/work-stamp:
vcom $(VCOM_FLAGS) -work work $< (vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
@mkdir -p $(dir $@) && touch $@
work/hdlmake/gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/091library/Makefile.ref
View file @ 5495d573
...@@ -19,12 +19,12 @@ VERILOG_OBJ := ...@@ -19,12 +19,12 @@ VERILOG_OBJ :=
VHDL_SRC := gate3.vhd \ VHDL_SRC := gate3.vhd \
../files/gate.vhdl \ ../files/gate.vhdl \
VHDL_OBJ := work/gate3/.gate3_vhd \ VHDL_OBJ := work/hdlmake/gate3_vhd \
sublib/gate/.gate_vhdl \ sublib/hdlmake/gate_vhdl \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := sublib work LIBS := sublib work
LIB_IND := sublib/.sublib work/.work LIB_IND := sublib/hdlmake/sublib-stamp work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -32,22 +32,21 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -32,22 +32,21 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
sublib/.sublib:
(vlib sublib && vmap $(VMAP_FLAGS) sublib && touch sublib/.sublib) || rm -rf sublib
work/.work: sublib/hdlmake/sublib-stamp:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work (vlib sublib && vmap $(VMAP_FLAGS) sublib && mkdir -p sublib/hdlmake && touch sublib/hdlmake/sublib-stamp) || rm -rf sublib
work/gate3/.gate3_vhd: gate3.vhd \ work/hdlmake/work-stamp:
sublib/gate/.gate_vhdl (vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/hdlmake/gate3_vhd: gate3.vhd \
sublib/hdlmake/gate_vhdl
vcom $(VCOM_FLAGS) -work work $<
@touch $@
sublib/gate/.gate_vhdl: ../files/gate.vhdl sublib/hdlmake/gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work sublib $< vcom $(VCOM_FLAGS) -work sublib $<
@mkdir -p $(dir $@) && touch $@ @touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/093multi_sat/Makefile.ref
View file @ 5495d573
...@@ -20,13 +20,13 @@ VHDL_SRC := lgate.vhdl \ ...@@ -20,13 +20,13 @@ VHDL_SRC := lgate.vhdl \
../files/gate.vhdl \ ../files/gate.vhdl \
../files/gate3.vhd \ ../files/gate3.vhd \
VHDL_OBJ := work/lgate/.lgate_vhdl \ VHDL_OBJ := work/hdlmake/lgate_vhdl \
work/gate/.gate_vhdl \ work/hdlmake/gate_vhdl \
work/gate3/.gate3_vhd \ work/hdlmake/gate3_vhd \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
LIB_IND := work/.work LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini $(VERILOG_OBJ): modelsim.ini
...@@ -34,27 +34,25 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini ...@@ -34,27 +34,25 @@ $(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1 cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work) || rm -rf work
work/lgate/.lgate_vhdl: lgate.vhdl \
work/gate/.gate_vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/hdlmake/work-stamp:
(vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
work/gate/.gate_vhdl: ../files/gate.vhdl \ work/hdlmake/lgate_vhdl: lgate.vhdl \
work/lgate/.lgate_vhdl work/hdlmake/gate_vhdl
vcom $(VCOM_FLAGS) -work work $< vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@ @touch $@
work/hdlmake/gate_vhdl: ../files/gate.vhdl \
work/gate3/.gate3_vhd: ../files/gate3.vhd \ work/hdlmake/lgate_vhdl
work/lgate/.lgate_vhdl \
work/gate/.gate_vhdl
vcom $(VCOM_FLAGS) -work work $< vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@ @touch $@
work/hdlmake/gate3_vhd: ../files/gate3.vhd \
work/hdlmake/lgate_vhdl \
work/hdlmake/gate_vhdl
vcom $(VCOM_FLAGS) -work work $<
@touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
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