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Hdlmake
Commit 583bd9e0 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Handle hdl files as a dictionay in Modelsim and Riviera

parent d9fb59f2
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hdlmake/tools/sim_makefile_support.py
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......@@ -42,7 +42,7 @@ class VsimMakefileWriter(ToolSim):
- Riviera
"""
HDL_FILES = [VerilogFile, VHDLFile, SVFile]
HDL_FILES = {VerilogFile: '', VHDLFile: '', SVFile: ''}
def __init__(self):
super(VsimMakefileWriter, self).__init__()
......@@ -59,7 +59,7 @@ class VsimMakefileWriter(ToolSim):
# These are files copied into your working directory by a make rule
# The key is the filename, the value is the file source path
self.copy_rules = {}
self._hdl_files.extend(VsimMakefileWriter.HDL_FILES)
self._hdl_files.update(VsimMakefileWriter.HDL_FILES)
def makefile_sim_options(self):
"""Print the vsim options to the Makefile"""
......
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