As test 125 except archictecture file is after entity (x after e)

Fails due to architecture is compiled before entity Further make -n shows a circular dependency (similar as in testcase 125): make: Circular work/hdlmake/gate4_x_a_vhdl <- work/hdlmake/gate4_e_vhdl dependency dropped.

As test 125 except archictecture file is after entity (x after e)
Fails due to architecture is compiled before entity Further make -n shows a circular dependency (similar as in testcase 125): make: Circular work/hdlmake/gate4_x_a_vhdl <- work/hdlmake/gate4_e_vhdl dependency dropped.
5987bf03 · Benny Simonsen · 2d1e038e · 5987bf03 · 5987bf03 · 5987bf03
Commit 5987bf03 authored Sep 12, 2023 by Benny Simonsen
4 changed files
--- a/testsuite/127arch_in_separate_file/Makefile.ref
+++ b/testsuite/127arch_in_separate_file/Makefile.ref
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+TOP_MODULE := gate4
+
+MODELSIM_INI_PATH := ../linux_fakebin/..
+
+VCOM_FLAGS := -quiet -modelsimini modelsim.ini 
+VSIM_FLAGS := 
+VLOG_FLAGS := -quiet -modelsimini modelsim.ini 
+VMAP_FLAGS := -modelsimini modelsim.ini 
+#target for performing local simulation
+local: sim_pre_cmd simulation sim_post_cmd
+
+VERILOG_SRC := 
+VERILOG_OBJ := 
+VHDL_SRC := ../files/gate.vhdl \
+../files/gate4_x_a.vhdl \
+../files/gate4_e.vhdl \
+
+VHDL_OBJ := work/hdlmake/gate_vhdl \
+work/hdlmake/gate4_x_a_vhdl \
+work/hdlmake/gate4_e_vhdl \
+
+INCLUDE_DIRS :=
+LIBS := work
+LIB_IND := work/hdlmake/work-stamp
+
+simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
+$(VERILOG_OBJ): modelsim.ini
+$(VHDL_OBJ): $(LIB_IND) modelsim.ini
+
+modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
+		cp $< . 2>&1
+
+work/hdlmake/work-stamp:
+	(vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
+
+work/hdlmake/gate_vhdl: ../files/gate.vhdl
+		vcom $(VCOM_FLAGS) -work work $< 
+		@touch $@
+
+work/hdlmake/gate4_x_a_vhdl: ../files/gate4_x_a.vhdl \
+work/hdlmake/gate_vhdl \
+work/hdlmake/gate4_e_vhdl
+		vcom $(VCOM_FLAGS) -work work $< 
+		@touch $@
+
+work/hdlmake/gate4_e_vhdl: ../files/gate4_e.vhdl \
+work/hdlmake/gate4_x_a_vhdl
+		vcom $(VCOM_FLAGS) -work work $< 
+		@touch $@
+
+# USER SIM COMMANDS
+sim_pre_cmd:
+		
+sim_post_cmd:
+		
+
+CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
+
+clean:
+		rm -rf $(CLEAN_TARGETS)
+mrproper: clean
+		rm -rf *.vcd *.wlf
+
+.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
--- a/testsuite/127arch_in_separate_file/Manifest.py
+++ b/testsuite/127arch_in_separate_file/Manifest.py
+action = "simulation"
+
+sim_tool="modelsim"
+
+top_module = "gate4"
+
+files = [ "../files/gate4_e.vhdl",  "../files/gate4_x_a.vhdl", "../files/gate.vhdl" ]
--- a/testsuite/127arch_in_separate_file/modelsim.ini
+++ b/testsuite/127arch_in_separate_file/modelsim.ini
--- a/testsuite/files/gate4_x_a.vhdl
+++ b/testsuite/files/gate4_x_a.vhdl
+architecture behav of gate4 is
+begin
+  inst: entity work.gate
+    port map (i, o);
+end behav;