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Hdlmake
Commit 59ab2d16 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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altera support in master branch (probably a bit broken)

parent bb81d5cf
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Showing with 247 additions and 6 deletions
src/Makefile
View file @ 59ab2d16
......@@ -18,8 +18,8 @@
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
#
SRC := configparser.py connection.py dep_solver.py fetch.py\
flow.py global_mod.py hdlmake_kernel.py help_printer.py helper_classes.py\
__main__.py makefile_writer.py module.py msg.py path.py\
flow.py flow_altera.py global_mod.py hdlmake_kernel.py help_printer.py helper_classes.py\
__main__.py makefile_writer.py module.py msg.py path.py \
srcfile.py
PREFIX := ./
......
src/flow_altera.py 0 → 100644
View file @ 59ab2d16
class QuartusProject:
class QuartusProjectProperty:
SET_GLOBAL_INSTANCE, SET_INSTANCE_ASSIGNMENT, SET_LOCATION_ASSIGNMENT, SET_GLOBAL_ASSIGNMENT = range(4)
t = {"set_global_instance" : SET_GLOBAL_INSTANCE,
"set_instance_assignment" : SET_INSTANCE_ASSIGNMENT,
"set_location_assignment": SET_LOCATION_ASSIGNMENT,
"set_global_assignment": SET_GLOBAL_ASSIGNMENT}
def __init__(self, command, what=None, name=None, name_type=None, from_=None, to=None, section_id=None):
self.command = command
self.what = what
self.name = name
self.name_type = name_type
self.from_ = from_
self.to = to
self.section_id = section_id
def emit(self):
words = []
words.append(dict([(b,a) for a,b in self.t.items()])[self.command])
if self.what != None:
words.append(self.what)
if self.name != None:
words.append("-name")
words.append(self.name_type)
words.append(self.name)
if self.from_ != None:
words.append("-from")
words.append(self.from_)
if self.to != None:
words.append("-to")
words.append(self.to)
if self.section_id != None:
words.append("-section_id")
words.append(self.section_id)
return ' '.join(words)
def __init__(self, filename):
self.properties = []
self.files = []
self.filename = filename
self.preflow = None
self.postflow = None
def emit(self):
f = open(self.filename+'.qsf', "w")
for p in self.properties:
f.write(p.emit()+'\n')
f.write(self.__emit_files())
f.write(self.__emit_scripts())
f.close()
f = open(self.filename+'.qpf', "w");
f.write("PROJECT_REVISION = \"" + self.filename + "\"\n")
f.close()
def __emit_scripts(self):
tmp = 'set_global_assignment -name {0} "quartus_sh:{1}"'
pre = post = ""
if self.preflow:
pre = tmp.format("PRE_FLOW_SCRIPT_FILE", self.preflow.rel_path())
if self.postflow:
post = tmp.format("POST_FLOW_SCTIPT_FILE", self.postflow.rel_path())
return pre+'\n'+post+'\n'
def __emit_files(self):
from srcfile import VHDLFile, VerilogFile, SignalTapFile, DPFFile
tmp = "set_global_assignment -name {0} {1}"
ret = []
for f in self.files:
if isinstance(f, VHDLFile):
line = tmp.format("VHDL_FILE", f.rel_path())
elif isinstance(f, VerilogFile):
line = tmp.format("VERILOG_FILE", f.rel_path())
elif isinstance(f, SignalTapFile):
line = tmp.format("SIGNALTAP_FILE", f.rel_path())
elif isinstance(f, DPFFile):
line = tmp.format("MISC_FILE", f.rel_path())
else:
continue
ret.append(line)
return ('\n'.join(ret))+'\n'
def add_property(self, val):
#don't save files (they are unneeded)
if val.name_type != None and "_FILE" in val.name_type:
return
self.properties.append(val)
def add_files(self, fileset):
for f in fileset:
self.files.append(f)
def read(self):
def __gather_string(words, first_index):
i = first_index
ret = []
if words[i][0] != '"':
return (words[i],1)
else:
while True:
ret.append(words[i])
if words[i][len(words[i])-1] == '"':
return (' '.join(ret), len(ret))
i=i+1
f = open(self.filename+'.qsf', "r")
lines = [l.strip() for l in f.readlines()]
lines = [l for l in lines if l != "" and l[0] != '#']
qpp = QuartusProject.QuartusProjectProperty
for line in lines:
words = line.split()
command = qpp.t[words[0]]
what = name = name_type = from_ = to = section_id = None
i = 1
while True:
if i >= len(words):
break
if words[i] == "-name":
name_type = words[i+1]
name, add = __gather_string(words, i+2)
# print name
i = i+2+add
continue
elif words[i] == "-section_id":
section_id, add = __gather_string(words, i+1)
i = i+1+add
continue
elif words[i] == "-to":
to, add = __gather_string(words, i+1)
i = i+1+add
continue
elif words[i] == "-from":
from_, add = __gather_string(words, i+1)
i = i+2
continue
else:
what = words[i]
i = i+1
continue
prop = self.QuartusProjectProperty(command=command, what=what, name=name, name_type=name_type, from_=from_,
to=to, section_id=section_id)
self.add_property(prop)
f.close()
def add_initial_properties(self, syn_device, syn_grade, syn_package, syn_top):
import re
family_names = {
"^EP2AGX.*$" : "Arria II GX",
"^EP3C.*$" : "Cyclone III"
}
for key in family_names:
if re.match(key, syn_device.upper()):
family = family_names[key];
devstring = (syn_device +syn_package+syn_grade).upper()
QPP=self.QuartusProjectProperty
self.add_property(QPP(QPP.SET_GLOBAL_ASSIGNMENT, name_type='FAMILY', name='"family"'))
self.add_property(QPP(QPP.SET_GLOBAL_ASSIGNMENT, name_type='DEVICE', name=devstring))
self.add_property(QPP(QPP.SET_GLOBAL_ASSIGNMENT, name_type='TOP_LEVEL_ENTITY', name=syn_top))
src/hdlmake_kernel.py
View file @ 59ab2d16
......@@ -24,6 +24,8 @@ import os
import msg as p
from help_printer import HelpPrinter as hp
from makefile_writer import MakefileWriter
from flow import ISEProject
from flow_altera import QuartusProject
class HdlmakeKernel(object):
def __init__(self, modules_pool, connection, options):
......@@ -47,10 +49,19 @@ class HdlmakeKernel(object):
if tm.action == "simulation":
self.generate_modelsim_makefile()
elif tm.action == "synthesis":
self.generate_ise_project()
self.generate_ise_makefile()
self.generate_remote_synthesis_makefile()
self.generate_fetch_makefile()
if tm.syn_project == None:
p.rawprint("syn_project variable must be defined in the manfiest")
p.quit()
if tm.target.lower() == "xilinx":
self.generate_ise_project()
self.generate_ise_makefile()
self.generate_remote_synthesis_makefile()
elif tm.target.lower() == "altera":
self.generate_quartus_project()
# self.generate_quartus_makefile()
# self.generate_quartus_remote_synthesis_makefile()
else:
raise RuntimeError("Unrecognized target: "+tm.target)
else:
hp.print_action_help() and quit()
......@@ -138,6 +149,21 @@ class HdlmakeKernel(object):
else:
self.__create_new_ise_project(ise=ise)
def generate_quartus_project(self):
p.rawprint("Generating/updating Quartus project...")
if not self.modules_pool.is_everything_fetched():
p.echo("A module remains unfetched. Fetching must be done prior to makefile generation")
p.echo(str([str(m) for m in self.modules_pool.modules if not m.isfetched]))
quit()
if os.path.exists(self.top_module.syn_project + ".qsf"):
self.__update_existing_quartus_project()
else:
self.__create_new_quartus_project()
def __figure_out_ise_path(self):
import path
if self.options.force_ise != None:
......@@ -225,6 +251,45 @@ class HdlmakeKernel(object):
prj.emit_xml(top_mod.syn_project)
def __create_new_quartus_project(self):
from dep_solver import DependencySolver
from srcfile import IDependable
from flow import ISEProject, ISEProjectProperty
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_global_file_list()
solver = DependencySolver()
non_dependable = fileset.inversed_filter(IDependable)
fileset = solver.solve(fileset)
fileset.add(non_dependable)
prj = QuartusProject(top_mod.syn_project)
prj.add_files(fileset)
prj.add_initial_properties( top_mod.syn_device,
top_mod.syn_grade,
top_mod.syn_package,
top_mod.syn_top);
prj.preflow = None
prj.postflow = None
prj.emit()
def __update_existing_quartus_project(self):
from dep_solver import DependencySolver
from srcfile import IDependable
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_global_file_list()
solver = DependencySolver()
non_dependable = fileset.inversed_filter(IDependable)
fileset = solver.solve(fileset)
fileset.add(non_dependable)
prj = QuartusProject(top_mod.syn_project)
prj.read()
prj.preflow = None
prj.postflow = None
prj.add_files(fileset)
prj.emit()
def run_local_synthesis(self):
tm = self.modules_pool.get_top_module()
if tm.target == "xilinx":
......
src/srcfile.py
View file @ 59ab2d16
......@@ -245,6 +245,14 @@ class CDCFile(File):
def __init__(self, path):
File.__init__(self, path)
class SignalTapFile(File):
def __init__(self, path):
File.__init__(self, path)
class DPFFile(File):
def __init__(self, path):
File.__init__(self, path)
class NGCFile(SourceFile):
def __init__(self, path):
SourceFile.__init__(self, path);
......@@ -327,4 +335,8 @@ class SourceFileFactory:
nf = TCLFile(path)
elif extension == 'xise' or extension == 'ise':
nf = XISEFile(path)
elif extension == 'stp':
nf = SignalTapFile(path)
elif extension == 'dpf':
nf = DPFFile(path)
return nf
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