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Hdlmake
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5d115c76
Commit
5d115c76
authored
Jun 11, 2019
by
Tristan Gingold
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isim: stabilize output, adjust test.
parent
9e5c4c98
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3 changed files
with
19 additions
and
8 deletions
+19
-8
isim.py
hdlmake/tools/isim.py
+2
-2
Makefile.ref
testsuite/010isim/Makefile.ref
+15
-4
Manifest.py
testsuite/010isim/Manifest.py
+2
-2
No files found.
hdlmake/tools/isim.py
View file @
5d115c76
...
...
@@ -176,7 +176,7 @@ fuse:
# rules for all _primary.dat files for sv
# incdir = ""
objs
=
[]
for
vl_file
in
fileset
.
filter
(
VerilogFile
):
for
vl_file
in
fileset
.
filter
(
VerilogFile
)
.
sort
()
:
comp_obj
=
os
.
path
.
join
(
vl_file
.
library
,
vl_file
.
purename
)
objs
.
append
(
comp_obj
)
# self.write(os.path.join(vl_file.library, vl_file.purename,
...
...
@@ -211,7 +211,7 @@ fuse:
self
.
writeln
(
" && "
+
shell
.
touch_command
()
+
" $@
\n\n
"
)
self
.
write
(
"
\n
"
)
# list rules for all _primary.dat files for vhdl
for
vhdl_file
in
fileset
.
filter
(
VHDLFile
):
for
vhdl_file
in
fileset
.
filter
(
VHDLFile
)
.
sort
()
:
lib
=
vhdl_file
.
library
purename
=
vhdl_file
.
purename
comp_obj
=
os
.
path
.
join
(
lib
,
purename
)
...
...
testsuite/010isim/Makefile.ref
View file @
5d115c76
...
...
@@ -5,7 +5,7 @@
## variables #############################
PWD
:=
$(
shell
pwd
)
TOP_MODULE
:=
gate_tb
TOP_MODULE
:=
gate
3
_tb
FUSE_OUTPUT
?=
isim_proj
...
...
@@ -14,13 +14,15 @@ VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
#target for performing local simulation
local
:
sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC
:=
../files/gate_tb.v
\
VERILOG_SRC
:=
../files/gate
3
_tb.v
\
VERILOG_OBJ
:=
work/gate
_tb/.gate
_tb_v
\
VERILOG_OBJ
:=
work/gate
3_tb/.gate3
_tb_v
\
VHDL_SRC
:=
../files/gate.vhdl
\
../files/gate3.vhd
\
VHDL_OBJ
:=
work/gate/.gate_vhdl
\
work/gate3/.gate3_vhd
\
LIBS
:=
work
LIB_IND
:=
work/.work
...
...
@@ -38,7 +40,7 @@ fuse:
work/.work
:
(
mkdir
-p
work
&&
touch
work/.work
&&
echo
work
=
work
>>
xilinxsim.ini
)
||
rm
-rf
work
work/gate
_tb/.gate_tb_v
:
../files/gate_tb.v ../files/gate.vhdl
work/gate
3_tb/.gate3_tb_v
:
../files/gate3_tb.v ../files/gate3.vhd
vlogcomp
-work
work
=
./work
$(VLOGCOMP_FLAGS)
-i
../files
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
...
...
@@ -52,6 +54,15 @@ work/gate/.gate_vhdl: ../files/gate.vhdl work/gate/.gate
work/gate/.gate
:
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gate3/.gate3_vhd
:
../files/gate3.vhd work/gate3/.gate3
vhpcomp
$(VHPCOMP_FLAGS)
-work
work
=
./work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gate3/.gate3
:
\
work/gate/.gate_vhdl
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
# USER SIM COMMANDS
sim_pre_cmd
:
...
...
testsuite/010isim/Manifest.py
View file @
5d115c76
...
...
@@ -2,6 +2,6 @@ action = "simulation"
sim_tool
=
"isim"
top_module
=
"gate_tb"
top_module
=
"gate
3
_tb"
files
=
[
"../files/gate
.vhdl"
,
"../files/gate
_tb.v"
]
files
=
[
"../files/gate
3.vhd"
,
"../files/gate.vhdl"
,
"../files/gate3
_tb.v"
]
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