Commit 5d71c1e7 authored by David Belohrad's avatar David Belohrad Committed by Tristan Gingold

QIP files are now defining top-level definition

so hdlmake can satisfy dependencies declared by qips
parent 63867ddf
......@@ -59,7 +59,7 @@ class DepRelation(object):
def satisfies(self, rel_b):
"""Check if the current dependency relation matches the provided one"""
return (rel_b.rel_type == self.rel_type
return (rel_b.rel_type == self.rel_type
and rel_b.obj_name == self.obj_name
and (self.lib_name is None or rel_b.lib_name == self.lib_name))
......@@ -208,7 +208,7 @@ class DepFile(File):
class ManualFile(DepFile):
"""Class that serves as base to binary HDL files with
"""Class that serves as base to binary HDL files with
dependencies and provided units manually added by the user"""
def __init__(self, path, module, provide=None, depends=[]):
......@@ -221,6 +221,3 @@ class ManualFile(DepFile):
graph.add_provide(self, DepRelation(unit, self.library, DepRelation.ENTITY))
for unit in self.depends_units:
graph.add_require(self, DepRelation(unit, self.library, DepRelation.ENTITY))
......@@ -61,7 +61,7 @@ class VHDLFile(SourceFile):
def __init__(self, path, module):
SourceFile.__init__(self, path=path, module=module)
def parse(self, graph):
from .vhdl_parser import VHDLParser
self.parser = VHDLParser()
......@@ -311,8 +311,11 @@ class WBGenFile(File):
# INTEL/ALTERA FILES
class QIPFile(File):
"""This is the class providing the Altera Quartus IP file"""
class QIPFile(ManualFile):
"""This is the class providing the Altera Quartus IP file. It is
expected that the declaration of QIP file is of type tuple, where
user specifies in the manifest the provided top-level module of
qip file."""
pass
......@@ -402,7 +405,7 @@ def create_source_file(path, module, include_dirs=None):
extension = extension[1:]
logging.debug("add file " + path)
if extension in ("ngc", ):
if extension in ("ngc", "qip"):
logging.warning("file %s in %s has no explicit provided units, rewrite as '(filename, unit)'",
path, module)
new_file = File(path=path, module=module)
......@@ -450,7 +453,8 @@ def create_source_file_with_deps(path, module, provide, depends):
extension = extension[1:]
logging.debug("add file with deps) " + path)
if extension == 'ngc':
if extension in ['ngc', ]:
return NGCFile(path, module, provide, depends)
elif extension in ['qip', ]:
return QIPFile(path, module, provide, depends)
raise Exception("Unknown extension '{}' for file {} (with deps)".format(extension, path))
......@@ -71,7 +71,8 @@ class ToolQuartus(MakefileSyn):
HDL_FILES = {
VHDLFile: _QUARTUS_SOURCE.format('VHDL_FILE') + _QUARTUS_LIBRARY,
VerilogFile: _QUARTUS_SOURCE.format('VERILOG_FILE') + _QUARTUS_LIBRARY,
SVFile: _QUARTUS_SOURCE.format('SYSTEMVERILOG_FILE') + _QUARTUS_LIBRARY}
SVFile: _QUARTUS_SOURCE.format('SYSTEMVERILOG_FILE') + _QUARTUS_LIBRARY,
QIPFile: _QUARTUS_SOURCE.format("QIP_FILE") + _QUARTUS_LIBRARY}
CLEAN_TARGETS = {'clean': ["*.rpt", "*.smsg", "*.summary",
"*.done", "*.jdi", "*.pin", "*.qws",
......
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