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Hdlmake
Commit 64eb10da authored by Paweł Szostek's avatar Paweł Szostek
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add --generate-project-vhd swtich

parent 74d58e92
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Showing with 17 additions and 9 deletions
hdlmake/__main__.py
View file @ 64eb10da
......@@ -76,6 +76,8 @@ def main():
merge_cores = subparsers.add_parser("merge-cores", help="Merges entire synthesizable content of an project into a pair of VHDL/Verilog files")
merge_cores.add_argument("--dest", help="name for output merged file", dest="dest", default=None)
ise_proj = subparsers.add_parser("ise-project", help="create/update an ise project including list of project")
ise_proj.add_argument("--generate-project-vhd", help="generate project.vhd file with a meta package describing the project",
dest="generate_project_vhd", default=False, action="store_true")
quartus_proj = subparsers.add_parser("quartus-project", help="create/update a quartus project including list of project")
condition_check = argparse.ArgumentParser()
......
hdlmake/action/ise_project.py
View file @ 64eb10da
......@@ -69,17 +69,23 @@ class GenerateISEProject(Action):
prj = ISEProject(ise=self.env["ise_version"],
top_mod=self.modules_pool.get_top_module())
self._write_project_vhd()
prj.add_files(flist)
sff = SourceFileFactory()
logging.debug(top_mod.vlog_opt)
# prj.add_files([sff.new(top_mod.vlog_opt)])
prj.add_files([sff.new(path=path.rel2abs("project.vhd"),
module=self.modules_pool.get_module_by_path("."))])
if self.options.generate_project_vhd:
self._write_project_vhd()
prj.add_files([sff.new(path=path.rel2abs("project.vhd"),
module=self.modules_pool.get_module_by_path("."))])\
prj.add_libs(fileset.get_libs())
if update is True:
prj.load_xml(top_mod.syn_project)
try:
prj.load_xml(top_mod.syn_project)
except:
logging.error("Error while reading the project file.\n"
"Are you sure that syn_project indicates a correct ISE project file?")
raise
else:
prj.add_initial_properties()
logging.info("Writing down .xise project file")
......@@ -93,7 +99,7 @@ class GenerateISEProject(Action):
today = date.today()
date_string = today.strftime("%Y%m%d")
template = Template("""library ieee;
use work.wishbone_pkg.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......
hdlmake/makefile_writer.py
View file @ 64eb10da
......@@ -212,7 +212,7 @@ run.tcl
local: syn_pre_cmd check_tool
\t\techo "project open $$(PROJECT)" > run.tcl
\t\techo "process run {Generate Programming File} -force rerun_all" >> run.tcl
\t\t${ise_path}/xtclsh run.tcl
\t\t${xtclsh_path} run.tcl
check_tool:
\t\t${check_tool}
......@@ -260,7 +260,8 @@ mrproper:
ise_path=ise_path,
check_tool=check_tool,
syn_pre_cmd=syn_pre_cmd,
syn_post_cmd=syn_post_cmd)
syn_post_cmd=syn_post_cmd,
xtclsh_path=os.path.join(ise_path, "xtclsh"))
self.write(makefile_text)
for f in top_mod.incl_makefiles:
if os.path.exists(f):
......@@ -305,7 +306,6 @@ mrproper:
def generate_iverilog_makefile(self, fileset, top_module, modules_pool):
from srcfile import VerilogFile
import global_mod
#open the file and write the above preambule (part 1)
# for m in global_mod.mod_pool:
for f in global_mod.top_module.incl_makefiles:
......
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