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Hdlmake
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64f3ef14
Commit
64f3ef14
authored
Mar 30, 2016
by
jozsef imrek
Committed by
Javier D. Garcia-Lasheras
Mar 30, 2016
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This commit closes #1275
parent
55ca10ae
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quartus.py
hdlmake/tools/quartus/quartus.py
+2
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hdlmake/tools/quartus/quartus.py
View file @
64f3ef14
...
...
@@ -180,10 +180,11 @@ mrproper:
def
__emit_files
(
self
):
from
hdlmake.srcfile
import
VHDLFile
,
VerilogFile
,
SignalTapFile
,
SDCFile
,
QIPFile
,
DPFFile
tmp
=
"set_global_assignment -name {0} {1}"
tmplib
=
tmp
+
" -library {2}"
ret
=
[]
for
f
in
self
.
files
:
if
isinstance
(
f
,
VHDLFile
):
line
=
tmp
.
format
(
"VHDL_FILE"
,
f
.
rel_path
()
)
line
=
tmp
lib
.
format
(
"VHDL_FILE"
,
f
.
rel_path
(),
f
.
library
)
elif
isinstance
(
f
,
VerilogFile
):
line
=
tmp
.
format
(
"VERILOG_FILE"
,
f
.
rel_path
())
elif
isinstance
(
f
,
SignalTapFile
):
...
...
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