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Hdlmake
Commit 6d763a1d authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Fix minor style issues

parent 918438b5
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Showing with 19 additions and 14 deletions
hdlmake/fetch/git.py
View file @ 6d763a1d
......@@ -49,9 +49,9 @@ class Git(Fetcher):
shell=True)
tree_root_line = tree_root_cmd.stdout.readlines()[0].strip()
return tree_root_line
except CalledProcessError as e:
print e.output
logging.error("Cannot get the top level!")
except CalledProcessError as process_error:
logging.error("Cannot get the top level!: %s",
process_error.output)
quit()
@staticmethod
......@@ -74,9 +74,9 @@ class Git(Fetcher):
return None
else:
return None
except CalledProcessError as e:
print e.output
logging.error("Cannot get the submodule status!")
except CalledProcessError as process_error:
logging.error("Cannot get the submodule status!: %s",
process_error.output)
quit()
def fetch(self, module):
......
hdlmake/module/content.py
View file @ 6d763a1d
......@@ -110,8 +110,10 @@ class ModuleContent(ModuleCore):
# Included Makefiles
included_makefiles_aux = []
if "incl_makefiles" in self.manifest_dict:
if isinstance(self.manifest_dict["incl_makefiles"], six.string_types):
included_makefiles_aux.append(self.manifest_dict["incl_makefiles"])
if isinstance(self.manifest_dict["incl_makefiles"],
six.string_types):
included_makefiles_aux.append(
self.manifest_dict["incl_makefiles"])
else: # list
included_makefiles_aux = self.manifest_dict["incl_makefiles"][:]
makefiles_paths = self._make_list_of_paths(included_makefiles_aux)
......
hdlmake/tools/quartus.py
View file @ 6d763a1d
......@@ -66,9 +66,12 @@ class ToolQuartus(ToolSyn):
_QUARTUS_LIBRARY = " -library {0}".format('work')
HDL_FILES = {
VHDLFile: _QUARTUS_SOURCE.format('VHDL_FILE') + _QUARTUS_LIBRARY,
VerilogFile: _QUARTUS_SOURCE.format('SYSTEMVERILOG_FILE') + _QUARTUS_LIBRARY,
SVFile: _QUARTUS_SOURCE.format('VERILOG_FILE') + _QUARTUS_LIBRARY}
VHDLFile: _QUARTUS_SOURCE.format('VHDL_FILE') +
_QUARTUS_LIBRARY,
VerilogFile: _QUARTUS_SOURCE.format('SYSTEMVERILOG_FILE') +
_QUARTUS_LIBRARY,
SVFile: _QUARTUS_SOURCE.format('VERILOG_FILE') +
_QUARTUS_LIBRARY}
CLEAN_TARGETS = {'clean': ["*.rpt", "*.smsg", "run.tcl", "*.summary",
"*.done", "*.jdi", "*.pin", "*.qws",
......
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