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Hdlmake
Commits
6e6eb8ca
Commit
6e6eb8ca
authored
Jun 24, 2022
by
Tristan Gingold
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testsuite: add a test for order
parent
7cb2b5bb
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6 changed files
with
191 additions
and
0 deletions
+191
-0
Makefile.ref
testsuite/119order/Makefile.ref
+169
-0
Manifest.py
testsuite/119order/Manifest.py
+16
-0
Manifest.py
testsuite/119order/sub/Manifest.py
+1
-0
sub.ucf
testsuite/119order/sub/sub.ucf
+1
-0
top.ucf
testsuite/119order/top.ucf
+1
-0
test_all.py
testsuite/test_all.py
+3
-0
No files found.
testsuite/119order/Makefile.ref
0 → 100644
View file @
6e6eb8ca
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE
:=
gate
PROJECT
:=
gate
PROJECT_FILE
:=
$(PROJECT)
.xise
TOOL_PATH
:=
TCL_INTERPRETER
:=
xtclsh
ifneq
($(strip
$(TOOL_PATH)),)
TCL_INTERPRETER
:=
$(TOOL_PATH)
/
$(TCL_INTERPRETER)
endif
SYN_FAMILY
:=
Spartan6
SYN_DEVICE
:=
xc6slx45t
SYN_PACKAGE
:=
fgg484
SYN_GRADE
:=
-3
TCL_CREATE
:=
project new
$(PROJECT_FILE)
TCL_OPEN
:=
project open
$(PROJECT_FILE)
TCL_SAVE
:=
project save
TCL_CLOSE
:=
project close
#target for performing local synthesis
all
:
bitstream
files.tcl
:
echo
'xfile add sub/sub.ucf'
>>
$@
echo
'xfile add top.ucf'
>>
$@
echo
'xfile add ../files/gate.vhdl'
>>
$@
SYN_PRE_PROJECT_CMD
:=
SYN_POST_PROJECT_CMD
:=
SYN_PRE_SYNTHESIZE_CMD
:=
SYN_POST_SYNTHESIZE_CMD
:=
SYN_PRE_TRANSLATE_CMD
:=
SYN_POST_TRANSLATE_CMD
:=
SYN_PRE_MAP_CMD
:=
SYN_POST_MAP_CMD
:=
SYN_PRE_PAR_CMD
:=
SYN_POST_PAR_CMD
:=
SYN_PRE_BITSTREAM_CMD
:=
SYN_POST_BITSTREAM_CMD
:=
project.tcl
:
echo
file delete
$(PROJECT_FILE)
>>
$@
echo
$(TCL_CREATE)
>>
$@
echo
xfile remove
[
search
\*
-type
file]
>>
$@
echo source
files.tcl
>>
$@
echo
project
set
'"family"'
\"
$(SYN_FAMILY)
\"
>>
$@
echo
project
set
'"device"'
\"
$(SYN_DEVICE)
\"
>>
$@
echo
project
set
'"package"'
\"
$(SYN_PACKAGE)
\"
>>
$@
echo
project
set
'"speed"'
\"
$(SYN_GRADE)
\"
>>
$@
echo
project
set
'"Manual Implementation Compile Order"'
\"
false
\"
>>
$@
echo
project
set
'"Auto Implementation Top"'
\"
false
\"
>>
$@
echo
project
set
'"Create Binary Configuration File"'
\"
true
\"
>>
$@
echo
project
set
'"prop1"'
\"
0
\"
>>
$@
echo set
compile_directory
.
>>
$@
echo
project
set
top
$(TOP_MODULE)
>>
$@
echo
$(TCL_SAVE)
>>
$@
echo
$(TCL_CLOSE)
>>
$@
project
:
files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_PROJECT_CMD)
touch
$@
synthesize.tcl
:
echo
$(TCL_OPEN)
>>
$@
echo set
process
{
Synthesize - XST
}
>>
$@
echo
process run
'$$'
process
>>
$@
echo set
result
[
process get
'$$'
process status]
>>
$@
echo
if
{
'$$'
result
==
\"
errors
\"
}
{
>>
$@
echo exit
1
>>
$@
echo
}
>>
$@
echo
$(TCL_SAVE)
>>
$@
echo
$(TCL_CLOSE)
>>
$@
synthesize
:
project synthesize.tcl sub/sub.ucf top.ucf ../files/gate.vhdl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch
$@
translate.tcl
:
echo
$(TCL_OPEN)
>>
$@
echo set
process
{
Translate
}
>>
$@
echo
process run
'$$'
process
>>
$@
echo set
result
[
process get
'$$'
process status]
>>
$@
echo
if
{
'$$'
result
==
\"
errors
\"
}
{
>>
$@
echo exit
1
>>
$@
echo
}
>>
$@
echo
$(TCL_SAVE)
>>
$@
echo
$(TCL_CLOSE)
>>
$@
translate
:
synthesize translate.tcl
$(SYN_PRE_TRANSLATE_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_TRANSLATE_CMD)
touch
$@
map.tcl
:
echo
$(TCL_OPEN)
>>
$@
echo set
process
{
Map
}
>>
$@
echo
process run
'$$'
process
>>
$@
echo set
result
[
process get
'$$'
process status]
>>
$@
echo
if
{
'$$'
result
==
\"
errors
\"
}
{
>>
$@
echo exit
1
>>
$@
echo
}
>>
$@
echo
$(TCL_SAVE)
>>
$@
echo
$(TCL_CLOSE)
>>
$@
map
:
translate map.tcl
$(SYN_PRE_MAP_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_MAP_CMD)
touch
$@
par.tcl
:
echo
$(TCL_OPEN)
>>
$@
echo set
process
{
Place
'&'
Route
}
>>
$@
echo
process run
'$$'
process
>>
$@
echo set
result
[
process get
'$$'
process status]
>>
$@
echo
if
{
'$$'
result
==
\"
errors
\"
}
{
>>
$@
echo exit
1
>>
$@
echo
}
>>
$@
echo
$(TCL_SAVE)
>>
$@
echo
$(TCL_CLOSE)
>>
$@
par
:
map par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_PAR_CMD)
touch
$@
bitstream.tcl
:
echo
$(TCL_OPEN)
>>
$@
echo set
process
{
Generate Programming File
}
>>
$@
echo
process run
'$$'
process
>>
$@
echo set
result
[
process get
'$$'
process status]
>>
$@
echo
if
{
'$$'
result
==
\"
errors
\"
}
{
>>
$@
echo exit
1
>>
$@
echo
}
>>
$@
echo
$(TCL_SAVE)
>>
$@
echo
$(TCL_CLOSE)
>>
$@
bitstream
:
par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER)
$@
.tcl
$(SYN_POST_BITSTREAM_CMD)
touch
$@
CLEAN_TARGETS
:=
$(LIBS)
xst xlnx_auto_0_xdb iseconfig _xmsgs _ngo
*
.b
*
_summary.html
*
.bld
*
.cmd_log
*
.drc
*
.lso
*
.ncd
*
.ngc
*
.ngd
*
.ngr
*
.pad
*
.par
*
.pcf
*
.prj
*
.ptwx
*
.stx
*
.syr
*
.twr
*
.twx
*
.gise
*
.gise
*
.bgn
*
.unroutes
*
.ut
*
.xpi
*
.xst
*
.xise
*
.xwbt
*
_envsettings.html
*
_guide.ncd
*
_map.map
*
_map.mrp
*
_map.ncd
*
_map.ngm
*
_map.xrpt
*
_ngdbuild.xrpt
*
_pad.csv
*
_pad.txt
*
_par.xrpt
*
_summary.xml
*
_usage.xml
*
_xst.xrpt usage_statistics_webtalk.html webtalk.log par_usage_statistics.html webtalk_pn.xml
clean
:
rm
-rf
$(CLEAN_TARGETS)
rm
-rf
project synthesize translate map par bitstream
rm
-rf
project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper
:
clean
rm
-rf
*
.bit
*
.bin
*
.mcs
.PHONY
:
mrproper clean all
testsuite/119order/Manifest.py
0 → 100644
View file @
6e6eb8ca
action
=
"synthesis"
language
=
"vhdl"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
syn_top
=
"gate"
syn_project
=
"gate.xise"
syn_tool
=
"ise"
syn_properties
=
[[
'prop1'
,
0
]]
files
=
[
"../files/gate.vhdl"
,
"top.ucf"
]
modules
=
{
"local"
:
[
"sub"
]
}
testsuite/119order/sub/Manifest.py
0 → 100644
View file @
6e6eb8ca
files
=
[
"sub.ucf"
]
testsuite/119order/sub/sub.ucf
0 → 100644
View file @
6e6eb8ca
# this is sub
testsuite/119order/top.ucf
0 → 100644
View file @
6e6eb8ca
# this is top
testsuite/test_all.py
View file @
6e6eb8ca
...
...
@@ -562,6 +562,9 @@ def test_linerosoc_project_opt_117():
def
test_wildcards_118
():
run_compare
(
path
=
"118wildcards"
)
def
test_order_119
():
run_compare
(
path
=
"119order"
)
@
pytest
.
mark
.
xfail
def
test_xfail
():
"""This is a self-consistency test: the test is known to fail"""
...
...
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