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Commit 72cec82e authored by Tristan Gingold's avatar Tristan Gingold
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Add a test for vivado properties

parent 6c0e17fc
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testsuite/054vivado_props/Makefile.ref 0 → 100644
View file @ 72cec82e
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
PROJECT := gate
PROJECT_FILE := $(PROJECT).xpr
TOOL_PATH :=
TCL_INTERPRETER := vivado -mode tcl -source
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY :=
SYN_DEVICE := xc6slx45t
SYN_PACKAGE := fgg484
SYN_GRADE := -3
TCL_CREATE := create_project $(PROJECT) ./
TCL_OPEN := open_project $(PROJECT_FILE)
TCL_CLOSE := exit
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "add_files -norecurse $(sourcefile); set_property IS_GLOBAL_INCLUDE 1 [get_files $(sourcefile)]" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_SYNTHESIZE_CMD :=
SYN_POST_SYNTHESIZE_CMD :=
SYN_PRE_PAR_CMD :=
SYN_POST_PAR_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo $(TCL_CREATE) >> $@
echo # project properties >> $@
echo set_property "part" "$(SYN_DEVICE)$(SYN_PACKAGE)$(SYN_GRADE)" [current_project] >> $@
echo set_property "target_language" "vhdl" [current_project] >> $@
echo set_property "top" "$(TOP_MODULE)" [get_property srcset [current_run]] >> $@
echo set_property "ip_repo_paths" "." [current_fileset] >> $@
echo set_property "prop1" "val1obj" [current_project] >> $@
echo set_property -name {prop3 options} -value {obj} -objects [current_project] >> $@
echo set_property "prop4 err" "obj" [current_project] >> $@
echo source files.tcl >> $@
echo update_compile_order -fileset sources_1 >> $@
echo update_compile_order -fileset sim_1 >> $@
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
synthesize.tcl:
echo $(TCL_OPEN) >> $@
echo # synthesize properties >> $@
echo set_property "steps.synth_design" "2" [get_runs synth_1] >> $@
echo reset_run synth_1 >> $@
echo launch_runs synth_1 >> $@
echo wait_on_run synth_1 >> $@
echo set result [get_property STATUS [get_runs synth_1]] >> $@
echo set keyword [lindex [split '$$'result " "] end] >> $@
echo if { '$$'keyword != \"Complete!\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_CLOSE) >> $@
synthesize: project synthesize.tcl
$(SYN_PRE_SYNTHESIZE_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_SYNTHESIZE_CMD)
touch $@
par.tcl:
echo $(TCL_OPEN) >> $@
echo # par properties >> $@
echo set_property "steps.impl" "3" [get_runs impl_1] >> $@
echo reset_run impl_1 >> $@
echo launch_runs impl_1 >> $@
echo wait_on_run impl_1 >> $@
echo set result [get_property STATUS [get_runs impl_1]] >> $@
echo set keyword [lindex [split '$$'result " "] end] >> $@
echo if { '$$'keyword != \"Complete!\" } { >> $@
echo exit 1 >> $@
echo } >> $@
echo $(TCL_CLOSE) >> $@
par: synthesize par.tcl
$(SYN_PRE_PAR_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PAR_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
echo launch_runs impl_1 -to_step write_bitstream >> $@
echo wait_on_run impl_1 >> $@
echo $(TCL_CLOSE) >> $@
bitstream: par bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) .Xil *.jou *.log *.pb *.dmp $(PROJECT).cache $(PROJECT).data work $(PROJECT).runs $(PROJECT).hw $(PROJECT).ip_user_files $(PROJECT_FILE)
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.bit *.bin
.PHONY: mrproper clean all
testsuite/054vivado_props/Manifest.py 0 → 100644
View file @ 72cec82e
action = "synthesis"
fetchto = '.'
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "gate"
syn_project = "gate.xise"
syn_tool = "vivado"
syn_properties = [['prop1', 'val1' 'obj'],
["prop2", "is", "too", "long"],
["prop3 options", "obj"],
["prop4 err", "obj"],
["steps.synth_design", "2"],
["steps.impl", "3"]]
files = [ "../files/gate.vhdl" ]
testsuite/test_all.py
View file @ 72cec82e
......@@ -149,6 +149,9 @@ def test_riviera():
def test_vivado():
run_compare(path="018vivado")
def test_vivado_props():
run_compare(path="054vivado_props")
def test_vivado_sim():
run_compare(path="019vsim")
......
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