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Hdlmake
Commit 75aafc94 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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merge-cores option: puts together all files of a project into a single… 

merge-cores option: puts together all files of a project into a single 'archive'. For convenience of Windows users :)
parent a9445efc
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Showing with 68 additions and 13 deletions
src/__main__.py
View file @ 75aafc94
......@@ -60,6 +60,9 @@ def main():
parser.add_option("--list-files", action="store_true", dest="list_files",
default=None, help="List all files in a from of a space-separated string")
parser.add_option("--merge-cores=name", default=None, dest="merge_cores",
help="Merges entire synthesizable content of an project into a pair of VHDL/Verilog files")
parser.add_option("--ise-proj", action="store_true", dest="ise_proj",
default=None, help="create/update an ise project including list of project files")
......@@ -127,7 +130,8 @@ use 0 for current version""", metavar="ISE")
"make_ise" : "generate_ise_makefile",
"make_remote" : "generate_remote_synthesis_makefile",
"list" : "list_modules",
"clean" : "clean_modules"
"clean" : "clean_modules",
"merge_cores" : "merge_cores"
}
sth_chosen = False
......
src/configparser.py
View file @ 75aafc94
......@@ -273,6 +273,7 @@ class ConfigParser(object):
if type(val) not in opt.types:
raise RuntimeError("Given option: "+str(type(val))+" doesn't match specified types:"+str(opt.types))
ret[opt_name] = val
# print("Opt_name ", opt_name)
if type(val) == type(dict()):
try:
for key in val:
......
src/global_mod.py
View file @ 75aafc94
......@@ -24,5 +24,5 @@ top_module = None
global_target = "''"
#######
#this var is modified by the build makefile - DON'T TOUCH IT!
BUILD_ID = "2012Feb29:dc2276"
BUILD_ID = "2012Mar5:a9445e"
######
src/hdlmake_kernel.py
View file @ 75aafc94
......@@ -385,3 +385,38 @@ class HdlmakeKernel(object):
p.echo("A module remains unfetched. Fetching must be done prior to makefile generation")
quit()
self.make_writer.generate_fetch_makefile(pool)
def merge_cores(self):
from dep_solver import DependencySolver
from srcfile import VerilogFile, VHDLFile, SVFile
from vlog_parser import VerilogPreprocessor
solver = DependencySolver()
pool = self.modules_pool
if not pool.is_everything_fetched():
p.echo("A module remains unfetched. Fetching must be done prior to makefile generation")
p.echo(str([str(m) for m in self.modules_pool.modules if not m.isfetched]))
quit()
flist = pool.build_global_file_list();
flist_sorted = solver.solve(flist);
f_out = open(self.options.merge_cores+".vhd", "w")
for vhdl in flist_sorted.filter(VHDLFile):
f_out.write("\n\n--- File: %s ----\n\n" % vhdl.rel_path())
f_out.write(open(vhdl.rel_path(),"r").read()+"\n\n")
#print("VHDL: %s" % vhdl.rel_path())
f_out.close()
f_out = open(self.options.merge_cores+".v", "w")
for vlog in flist_sorted.filter(VerilogFile):
f_out.write("\n\n// File: %s \n\n" % vlog.rel_path())
vpp = VerilogPreprocessor()
vpp.add_path(vlog.dirname)
f_out.write(vpp.preprocess(vlog.rel_path()))
# print("VD: %s" % vlog.dirname)
# print("VL: %s" % vlog.rel_path())
# VerilogPreprocessor:
f_out.close()
\ No newline at end of file
src/srcfile.py
View file @ 75aafc94
......@@ -96,6 +96,12 @@ class SourceFile(IDependable, File):
class VHDLFile(SourceFile):
std_libs = [ 'std', 'ieee', 'vital2000',
'mtiavm', 'mtiovm', 'mtiuvm', 'mtiupf', 'mtipa', 'simprim',
'simprims_ver', 'xilinxcorelib', 'unimacro', 'unisim', 'secureip',
'altera', 'altera_mf', 'altera_primitives', 'lpm', 'sgate', 'cycloneiii'
];
def __init__(self, path, library = None, vcom_opt = None):
SourceFile.__init__(self, path, library);
self.__create_deps();
......@@ -129,16 +135,18 @@ class VHDLFile(SourceFile):
non-standard library a tuple (lib, file) is returned in a list.
"""
if global_mod.top_module.action == "simulation":
try:
std_libs = flow.ModelsiminiReader().get_libraries()
except RuntimeError:
std_libs = flow.MODELSIM_STANDARD_LIBS
elif global_mod.top_module.action == "synthesis":
if global_mod.top_module.target == "xilinx":
std_libs = flow.ISE_STANDARD_LIBS
elif global_mod.top_module.target == "altera":
std_libs = flow.MODELSIM_STANDARD_LIBS
# print("ACT" ,global_mod.top_module.action)
# if global_mod.top_module.action == "simulation":
# try:
# std_libs = flow.ModelsiminiReader().get_libraries()
# print("STD: ", std_libs);
# except RuntimeError:
# std_libs = flow.MODELSIM_STANDARD_LIBS
# elif global_mod.top_module.action == "synthesis":
# if global_mod.top_module.target == "xilinx":
# std_libs = flow.ISE_STANDARD_LIBS
# elif global_mod.top_module.target == "altera":
# std_libs = flow.MODELSIM_STANDARD_LIBS
import re
f = open(self.path, "r")
......@@ -163,7 +171,7 @@ class VHDLFile(SourceFile):
m = re.match(lib_pattern, line)
if m != None:
#omit standard libraries
if (m.group(1)).lower() in std_libs:
if (m.group(1)).lower() in self.std_libs:
continue
if self.library != "work":
#if a file is put in a library, `work' points this library
......@@ -272,6 +280,10 @@ class WBGenFile(File):
def __init__(self, path):
File.__init__(self, path);
class RAMFile(File):
def __init__(self, path):
File.__init__(self, path);
class SourceFileSet(list):
def __init__(self):
pass
......@@ -349,4 +361,7 @@ class SourceFileFactory:
nf = SignalTapFile(path)
elif extension == 'dpf':
nf = DPFFile(path)
elif extension == 'ram':
nf = RAMFile(path)
return nf
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