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Commit 7dc0a9c2 authored by Benny Simonsen's avatar Benny Simonsen
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xilinx: Rm default_library = None & set_property LIBRARY work 

Skip default_library = None for ToolXilinx (syn) (now work is derived
from ToolMakefile.

Prior "set_property LIBRARY {library} [get_files {srcfile}]" was set
unless library = None. Now it is set unless library is None or work.
This causes one Xilinx vivado_sim testcase to fail/change since
set_property LIBRARY work was set - removed.
parent 96a1adb9
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Showing with 2 additions and 3 deletions
hdlmake/tools/xilinx.py
View file @ 7dc0a9c2
......@@ -71,7 +71,6 @@ $(TCL_CLOSE)'''
def __init__(self):
super(ToolXilinx, self).__init__()
self._tcl_controls.update(ToolXilinx.TCL_CONTROLS)
self.default_library = None
def _get_properties(self):
"""Create the property list"""
......
hdlmake/tools/xilinx_prj.py
View file @ 7dc0a9c2
......@@ -35,8 +35,9 @@ class ToolXilinxProject:
# Commands to be executed to complete the addition of a source file
# in the project (like setting the library)
# Note: Ok to set_property LIBRARY work, previously done in vivado_sim. vivado(synth it was None, now work).
_XILINX_VHDL_PROPERTY = (
lambda srcfile: "set_property LIBRARY {library} [get_files {srcfile}]" if srcfile.library is not None else "")
lambda srcfile: "set_property LIBRARY {library} [get_files {srcfile}]" if srcfile.library not in [None, "work"] else "")
_XILINX_VERILOG_PROPERTY = ""
......
testsuite/019vsim/Makefile.ref
View file @ 7dc0a9c2
......@@ -30,7 +30,6 @@ project.tcl: Makefile
@echo add_files -norecurse '{' >> $@
@echo '../files/gate.vhdl' >> $@
@echo '}' >> $@
@echo 'set_property LIBRARY work [get_files ../files/gate.vhdl]' >> $@
@echo "exit" >> $@
project: project.tcl
......
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