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Hdlmake
Commit 9cf5b959 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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The makefile functions for writing simulation and synthesis stages are now private

parent 8d5b4529
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Showing with 68 additions and 68 deletions
hdlmake/tools/active_hdl.py
View file @ 9cf5b959
...@@ -52,7 +52,7 @@ class ToolActiveHDL(ToolSim): ...@@ -52,7 +52,7 @@ class ToolActiveHDL(ToolSim):
self._standard_libs.extend(ToolActiveHDL.STANDARD_LIBS) self._standard_libs.extend(ToolActiveHDL.STANDARD_LIBS)
self._clean_targets.update(ToolActiveHDL.CLEAN_TARGETS) self._clean_targets.update(ToolActiveHDL.CLEAN_TARGETS)
def makefile_sim_compilation(self): def _makefile_sim_compilation(self):
"""Print Makefile compilation target for Aldec Active-HDL simulator""" """Print Makefile compilation target for Aldec Active-HDL simulator"""
fileset = self.fileset fileset = self.fileset
self.writeln("simulation:") self.writeln("simulation:")
......
hdlmake/tools/diamond.py
View file @ 9cf5b959
...@@ -86,7 +86,7 @@ class ToolDiamond(ToolSyn): ...@@ -86,7 +86,7 @@ class ToolDiamond(ToolSyn):
self._clean_targets.update(ToolDiamond.CLEAN_TARGETS) self._clean_targets.update(ToolDiamond.CLEAN_TARGETS)
self._tcl_controls.update(ToolDiamond.TCL_CONTROLS) self._tcl_controls.update(ToolDiamond.TCL_CONTROLS)
def makefile_syn_tcl(self): def _makefile_syn_tcl(self):
"""Create a Diamond synthesis project by TCL""" """Create a Diamond synthesis project by TCL"""
syn_device = self.manifest_dict["syn_device"] syn_device = self.manifest_dict["syn_device"]
syn_grade = self.manifest_dict["syn_grade"] syn_grade = self.manifest_dict["syn_grade"]
...@@ -94,4 +94,4 @@ class ToolDiamond(ToolSyn): ...@@ -94,4 +94,4 @@ class ToolDiamond(ToolSyn):
create_tmp = self._tcl_controls["create"] create_tmp = self._tcl_controls["create"]
target = syn_device + syn_grade + syn_package target = syn_device + syn_grade + syn_package
self._tcl_controls["create"] = create_tmp.format(target.upper()) self._tcl_controls["create"] = create_tmp.format(target.upper())
super(ToolDiamond, self).makefile_syn_tcl() super(ToolDiamond, self)._makefile_syn_tcl()
hdlmake/tools/ghdl.py
View file @ 9cf5b959
...@@ -59,7 +59,7 @@ class ToolGHDL(ToolSim): ...@@ -59,7 +59,7 @@ class ToolGHDL(ToolSim):
self._clean_targets.update(ToolGHDL.CLEAN_TARGETS) self._clean_targets.update(ToolGHDL.CLEAN_TARGETS)
self._simulator_controls.update(ToolGHDL.SIMULATOR_CONTROLS) self._simulator_controls.update(ToolGHDL.SIMULATOR_CONTROLS)
def makefile_sim_options(self): def _makefile_sim_options(self):
"""Print the GHDL options to the Makefile""" """Print the GHDL options to the Makefile"""
ghdl_opt = self.manifest_dict.get("ghdl_opt", '') ghdl_opt = self.manifest_dict.get("ghdl_opt", '')
ghdl_string = string.Template( ghdl_string = string.Template(
...@@ -67,9 +67,9 @@ class ToolGHDL(ToolSim): ...@@ -67,9 +67,9 @@ class ToolGHDL(ToolSim):
self.writeln(ghdl_string.substitute( self.writeln(ghdl_string.substitute(
ghdl_opt=ghdl_opt)) ghdl_opt=ghdl_opt))
def makefile_sim_compilation(self): def _makefile_sim_compilation(self):
"""Print the GDHL simulation compilation target""" """Print the GDHL simulation compilation target"""
self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)") self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("\t\t" + self._simulator_controls['compiler']) self.writeln("\t\t" + self._simulator_controls['compiler'])
self.writeln('\n') self.writeln('\n')
self.makefile_sim_dep_files() self._makefile_sim_dep_files()
hdlmake/tools/icestorm.py
View file @ 9cf5b959
...@@ -71,7 +71,7 @@ class ToolIcestorm(ToolSyn): ...@@ -71,7 +71,7 @@ class ToolIcestorm(ToolSyn):
self._clean_targets.update(ToolIcestorm.CLEAN_TARGETS) self._clean_targets.update(ToolIcestorm.CLEAN_TARGETS)
self._tcl_controls.update(ToolIcestorm.TCL_CONTROLS) self._tcl_controls.update(ToolIcestorm.TCL_CONTROLS)
def makefile_syn_top(self): def _makefile_syn_top(self):
self.manifest_dict["syn_family"] = 'iCE40' self.manifest_dict["syn_family"] = 'iCE40'
super(ToolIcestorm, self).makefile_syn_top() super(ToolIcestorm, self)._makefile_syn_top()
hdlmake/tools/ise.py
View file @ 9cf5b959
...@@ -129,7 +129,7 @@ $(TCL_CLOSE)''' ...@@ -129,7 +129,7 @@ $(TCL_CLOSE)'''
self._clean_targets.update(ToolISE.CLEAN_TARGETS) self._clean_targets.update(ToolISE.CLEAN_TARGETS)
self._tcl_controls.update(ToolISE.TCL_CONTROLS) self._tcl_controls.update(ToolISE.TCL_CONTROLS)
def makefile_syn_top(self): def _makefile_syn_top(self):
"""Create the top part of the synthesis Makefile for ISE""" """Create the top part of the synthesis Makefile for ISE"""
syn_family = self.manifest_dict.get("syn_family", None) syn_family = self.manifest_dict.get("syn_family", None)
if syn_family is None: if syn_family is None:
...@@ -141,10 +141,10 @@ $(TCL_CLOSE)''' ...@@ -141,10 +141,10 @@ $(TCL_CLOSE)'''
" and can not be guessed!") " and can not be guessed!")
quit(-1) quit(-1)
self.manifest_dict["syn_family"] = syn_family self.manifest_dict["syn_family"] = syn_family
super(ToolISE, self).makefile_syn_top() super(ToolISE, self)._makefile_syn_top()
def makefile_syn_tcl(self): def _makefile_syn_tcl(self):
"""Create a Xilinx synthesis project by TCL""" """Create a Xilinx synthesis project by TCL"""
syn_properties = self.manifest_dict.get("syn_properties") syn_properties = self.manifest_dict.get("syn_properties")
project_new = [] project_new = []
...@@ -168,4 +168,4 @@ $(TCL_CLOSE)''' ...@@ -168,4 +168,4 @@ $(TCL_CLOSE)'''
project_new.append('set compile_directory .') project_new.append('set compile_directory .')
self._tcl_controls["project"] = project_tcl.format( self._tcl_controls["project"] = project_tcl.format(
"\n".join(project_new)) "\n".join(project_new))
super(ToolISE, self).makefile_syn_tcl() super(ToolISE, self)._makefile_syn_tcl()
hdlmake/tools/isim.py
View file @ 9cf5b959
...@@ -66,7 +66,7 @@ class ToolISim(ToolSim): ...@@ -66,7 +66,7 @@ class ToolISim(ToolSim):
self._standard_libs.extend(ToolISim.STANDARD_LIBS) self._standard_libs.extend(ToolISim.STANDARD_LIBS)
self._clean_targets.update(ToolISim.CLEAN_TARGETS) self._clean_targets.update(ToolISim.CLEAN_TARGETS)
def makefile_sim_top(self): def _makefile_sim_top(self):
"""Print the top section of the Makefile for Xilinx ISim""" """Print the top section of the Makefile for Xilinx ISim"""
def __get_xilinxsim_ini_dir(): def __get_xilinxsim_ini_dir():
...@@ -101,7 +101,7 @@ XILINX_INI_PATH := """ + __get_xilinxsim_ini_dir() + ...@@ -101,7 +101,7 @@ XILINX_INI_PATH := """ + __get_xilinxsim_ini_dir() +
""" """
""") """)
def makefile_sim_options(self): def _makefile_sim_options(self):
"""Print the Xilinx ISim simulation options in the Makefile""" """Print the Xilinx ISim simulation options in the Makefile"""
def __get_rid_of_isim_incdirs(vlog_opt): def __get_rid_of_isim_incdirs(vlog_opt):
"""Clean the vlog options from include dirs""" """Clean the vlog options from include dirs"""
...@@ -127,7 +127,7 @@ VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ + ...@@ -127,7 +127,7 @@ VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ +
self.manifest_dict.get("vlog_opt", '')) + """ self.manifest_dict.get("vlog_opt", '')) + """
""") """)
def makefile_sim_compilation(self): def _makefile_sim_compilation(self):
"""Print the compile simulation target for Xilinx ISim""" """Print the compile simulation target for Xilinx ISim"""
fileset = self.fileset fileset = self.fileset
libs = set(f.library for f in fileset) libs = set(f.library for f in fileset)
......
hdlmake/tools/iverilog.py
View file @ 9cf5b959
...@@ -62,7 +62,7 @@ class ToolIVerilog(ToolSim): ...@@ -62,7 +62,7 @@ class ToolIVerilog(ToolSim):
self._clean_targets.update(ToolIVerilog.CLEAN_TARGETS) self._clean_targets.update(ToolIVerilog.CLEAN_TARGETS)
self._simulator_controls.update(ToolIVerilog.SIMULATOR_CONTROLS) self._simulator_controls.update(ToolIVerilog.SIMULATOR_CONTROLS)
def makefile_sim_compilation(self): def _makefile_sim_compilation(self):
"""Generate compile simulation Makefile target for IVerilog""" """Generate compile simulation Makefile target for IVerilog"""
self.writeln("simulation: include_dirs $(VERILOG_OBJ) $(VHDL_OBJ)") self.writeln("simulation: include_dirs $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("\t\t" + self._simulator_controls['compiler']) self.writeln("\t\t" + self._simulator_controls['compiler'])
...@@ -74,9 +74,9 @@ class ToolIVerilog(ToolSim): ...@@ -74,9 +74,9 @@ class ToolIVerilog(ToolSim):
for inc in self.manifest_dict.get("include_dirs", []): for inc in self.manifest_dict.get("include_dirs", []):
self.writeln("\t\techo \"+incdir+" + inc + "\" >> run.command") self.writeln("\t\techo \"+incdir+" + inc + "\" >> run.command")
self.writeln('\n') self.writeln('\n')
self.makefile_sim_dep_files() self._makefile_sim_dep_files()
def makefile_sim_options(self): def _makefile_sim_options(self):
"""Print the IVerilog options to the Makefile""" """Print the IVerilog options to the Makefile"""
iverilog_opt = self.manifest_dict.get("iverilog_opt", '') iverilog_opt = self.manifest_dict.get("iverilog_opt", '')
iverilog_string = string.Template( iverilog_string = string.Template(
......
hdlmake/tools/libero.py
View file @ 9cf5b959
...@@ -83,7 +83,7 @@ class ToolLibero(ToolSyn): ...@@ -83,7 +83,7 @@ class ToolLibero(ToolSyn):
self._clean_targets.update(ToolLibero.CLEAN_TARGETS) self._clean_targets.update(ToolLibero.CLEAN_TARGETS)
self._tcl_controls.update(ToolLibero.TCL_CONTROLS) self._tcl_controls.update(ToolLibero.TCL_CONTROLS)
def makefile_syn_tcl(self): def _makefile_syn_tcl(self):
"""Create a Libero synthesis project by TCL""" """Create a Libero synthesis project by TCL"""
syn_project = self.manifest_dict["syn_project"] syn_project = self.manifest_dict["syn_project"]
syn_device = self.manifest_dict["syn_device"] syn_device = self.manifest_dict["syn_device"]
...@@ -129,4 +129,4 @@ class ToolLibero(ToolSyn): ...@@ -129,4 +129,4 @@ class ToolLibero(ToolSyn):
line = 'set_root -module {$(TOP_MODULE)::work}' line = 'set_root -module {$(TOP_MODULE)::work}'
ret.append(line) ret.append(line)
self._tcl_controls['project'] = project_tmp.format('\n'.join(ret)) self._tcl_controls['project'] = project_tmp.format('\n'.join(ret))
super(ToolLibero, self).makefile_syn_tcl() super(ToolLibero, self)._makefile_syn_tcl()
hdlmake/tools/make_sim.py
View file @ 9cf5b959
...@@ -34,16 +34,16 @@ class ToolSim(ToolMakefile): ...@@ -34,16 +34,16 @@ class ToolSim(ToolMakefile):
_check_simulation_manifest(config) _check_simulation_manifest(config)
self.makefile_setup(config, fileset, filename=filename) self.makefile_setup(config, fileset, filename=filename)
self.makefile_check_tool('sim_path') self.makefile_check_tool('sim_path')
self.makefile_sim_top() self._makefile_sim_top()
self.makefile_sim_options() self._makefile_sim_options()
self.makefile_sim_local() self._makefile_sim_local()
self.makefile_sim_sources() self._makefile_sim_sources()
self.makefile_sim_compilation() self._makefile_sim_compilation()
self.makefile_sim_command() self._makefile_sim_command()
self.makefile_sim_clean() self._makefile_sim_clean()
self.makefile_sim_phony() self._makefile_sim_phony()
def makefile_sim_top(self): def _makefile_sim_top(self):
"""Generic method to write the simulation Makefile top section""" """Generic method to write the simulation Makefile top section"""
top_parameter = string.Template("""\ top_parameter = string.Template("""\
TOP_MODULE := ${top_module} TOP_MODULE := ${top_module}
...@@ -52,21 +52,21 @@ PWD := $$(shell pwd) ...@@ -52,21 +52,21 @@ PWD := $$(shell pwd)
self.writeln(top_parameter.substitute( self.writeln(top_parameter.substitute(
top_module=self.manifest_dict["sim_top"])) top_module=self.manifest_dict["sim_top"]))
def makefile_sim_options(self): def _makefile_sim_options(self):
"""End stub method to write the simulation Makefile options section""" """End stub method to write the simulation Makefile options section"""
pass pass
def makefile_sim_compilation(self): def _makefile_sim_compilation(self):
"""End stub method to write the simulation Makefile compilation """End stub method to write the simulation Makefile compilation
section""" section"""
pass pass
def makefile_sim_local(self): def _makefile_sim_local(self):
"""Generic method to write the simulation Makefile local target""" """Generic method to write the simulation Makefile local target"""
self.writeln("#target for performing local simulation\n" self.writeln("#target for performing local simulation\n"
"local: sim_pre_cmd simulation sim_post_cmd\n") "local: sim_pre_cmd simulation sim_post_cmd\n")
def makefile_sim_sources(self): def _makefile_sim_sources(self):
"""Generic method to write the simulation Makefile HDL sources""" """Generic method to write the simulation Makefile HDL sources"""
fileset = self.fileset fileset = self.fileset
self.write("VERILOG_SRC := ") self.write("VERILOG_SRC := ")
...@@ -110,7 +110,7 @@ PWD := $$(shell pwd) ...@@ -110,7 +110,7 @@ PWD := $$(shell pwd)
" \\") " \\")
self.writeln() self.writeln()
def makefile_sim_dep_files(self): def _makefile_sim_dep_files(self):
"""Print dummy targets to handle file dependencies""" """Print dummy targets to handle file dependencies"""
fileset = self.fileset fileset = self.fileset
for file_aux in fileset: for file_aux in fileset:
...@@ -143,7 +143,7 @@ PWD := $$(shell pwd) ...@@ -143,7 +143,7 @@ PWD := $$(shell pwd)
self.writeln(" && " + shell.touch_command() + " $@ \n") self.writeln(" && " + shell.touch_command() + " $@ \n")
self.writeln() self.writeln()
def makefile_sim_command(self): def _makefile_sim_command(self):
"""Generic method to write the simulation Makefile user commands""" """Generic method to write the simulation Makefile user commands"""
sim_pre_cmd = self.manifest_dict.get("sim_pre_cmd", '') sim_pre_cmd = self.manifest_dict.get("sim_pre_cmd", '')
sim_post_cmd = self.manifest_dict.get("sim_post_cmd", '') sim_post_cmd = self.manifest_dict.get("sim_post_cmd", '')
...@@ -156,12 +156,12 @@ sim_post_cmd: ...@@ -156,12 +156,12 @@ sim_post_cmd:
self.writeln(sim_command.substitute(sim_pre_cmd=sim_pre_cmd, self.writeln(sim_command.substitute(sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd)) sim_post_cmd=sim_post_cmd))
def makefile_sim_clean(self): def _makefile_sim_clean(self):
"""Generic method to write the simulation Makefile user clean target""" """Generic method to write the simulation Makefile user clean target"""
self.makefile_clean() self.makefile_clean()
self.makefile_mrproper() self.makefile_mrproper()
def makefile_sim_phony(self): def _makefile_sim_phony(self):
"""Print simulation PHONY target list to the Makefile""" """Print simulation PHONY target list to the Makefile"""
self.writeln( self.writeln(
".PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation") ".PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation")
hdlmake/tools/make_syn.py
View file @ 9cf5b959
...@@ -46,17 +46,17 @@ class ToolSyn(ToolMakefile): ...@@ -46,17 +46,17 @@ class ToolSyn(ToolMakefile):
filename=filename) filename=filename)
self.makefile_check_tool('syn_path') self.makefile_check_tool('syn_path')
self.makefile_includes() self.makefile_includes()
self.makefile_syn_top() self._makefile_syn_top()
self.makefile_syn_tcl() self._makefile_syn_tcl()
self.makefile_syn_local() self._makefile_syn_local()
self.makefile_syn_files() self._makefile_syn_files()
self.makefile_syn_command() self._makefile_syn_command()
self.makefile_syn_build() self._makefile_syn_build()
self.makefile_syn_clean() self._makefile_syn_clean()
self.makefile_syn_phony() self._makefile_syn_phony()
logging.info(self._tool_info['name'] + " synthesis makefile generated.") logging.info(self._tool_info['name'] + " synthesis makefile generated.")
def makefile_syn_top(self): def _makefile_syn_top(self):
"""Create the top part of the synthesis Makefile""" """Create the top part of the synthesis Makefile"""
if shell.check_windows(): if shell.check_windows():
tcl_interpreter = self._tool_info["windows_bin"] tcl_interpreter = self._tool_info["windows_bin"]
...@@ -90,7 +90,7 @@ SYN_GRADE := ${syn_grade} ...@@ -90,7 +90,7 @@ SYN_GRADE := ${syn_grade}
tool_path=self.manifest_dict["syn_path"], tool_path=self.manifest_dict["syn_path"],
top_module=self.manifest_dict["syn_top"])) top_module=self.manifest_dict["syn_top"]))
def makefile_syn_tcl(self): def _makefile_syn_tcl(self):
"""Create the Makefile TCL dictionary for the selected tool""" """Create the Makefile TCL dictionary for the selected tool"""
command_list = ["create", "open", "save", "close"] command_list = ["create", "open", "save", "close"]
for command in command_list: for command in command_list:
...@@ -103,7 +103,7 @@ TCL_CREATE := $(TCL_OPEN) ...@@ -103,7 +103,7 @@ TCL_CREATE := $(TCL_OPEN)
endif""") endif""")
self.writeln() self.writeln()
def makefile_syn_files(self): def _makefile_syn_files(self):
"""Write the files TCL section of the Makefile""" """Write the files TCL section of the Makefile"""
ret = [] ret = []
fileset_dict = {} fileset_dict = {}
...@@ -143,12 +143,12 @@ endif""") ...@@ -143,12 +143,12 @@ endif""")
self.writeln(filetype_string) self.writeln(filetype_string)
self.writeln() self.writeln()
def makefile_syn_local(self): def _makefile_syn_local(self):
"""Generic method to write the synthesis Makefile local target""" """Generic method to write the synthesis Makefile local target"""
self.writeln("#target for performing local synthesis\n" self.writeln("#target for performing local synthesis\n"
"all: bitstream\n") "all: bitstream\n")
def makefile_syn_build(self): def _makefile_syn_build(self):
"""Generate the synthesis Makefile targets for handling design build""" """Generate the synthesis Makefile targets for handling design build"""
stage_previous = "files.tcl" stage_previous = "files.tcl"
stage_list = ["project", "synthesize", "translate", stage_list = ["project", "synthesize", "translate",
...@@ -176,7 +176,7 @@ endif""") ...@@ -176,7 +176,7 @@ endif""")
command_string, shell.touch_command())) command_string, shell.touch_command()))
stage_previous = stage stage_previous = stage
def makefile_syn_command(self): def _makefile_syn_command(self):
"""Create the Makefile targets for user defined commands""" """Create the Makefile targets for user defined commands"""
stage_list = ["project", "synthesize", "translate", stage_list = ["project", "synthesize", "translate",
"map", "par", "bitstream"] "map", "par", "bitstream"]
...@@ -189,7 +189,7 @@ SYN_POST_{0}_CMD := {2} ...@@ -189,7 +189,7 @@ SYN_POST_{0}_CMD := {2}
self.manifest_dict.get("syn_pre_" + stage + "_cmd", ''), self.manifest_dict.get("syn_pre_" + stage + "_cmd", ''),
self.manifest_dict.get("syn_post_" + stage + "_cmd", ''))) self.manifest_dict.get("syn_post_" + stage + "_cmd", '')))
def makefile_syn_clean(self): def _makefile_syn_clean(self):
"""Print the Makefile clean target for synthesis""" """Print the Makefile clean target for synthesis"""
self.makefile_clean() self.makefile_clean()
self.writeln("\t\t" + shell.del_command() + self.writeln("\t\t" + shell.del_command() +
...@@ -197,7 +197,7 @@ SYN_POST_{0}_CMD := {2} ...@@ -197,7 +197,7 @@ SYN_POST_{0}_CMD := {2}
self.writeln() self.writeln()
self.makefile_mrproper() self.makefile_mrproper()
def makefile_syn_phony(self): def _makefile_syn_phony(self):
"""Print synthesis PHONY target list to the Makefile""" """Print synthesis PHONY target list to the Makefile"""
self.writeln( self.writeln(
".PHONY: mrproper clean all") ".PHONY: mrproper clean all")
hdlmake/tools/modelsim.py
View file @ 9cf5b959
...@@ -56,7 +56,7 @@ class ToolModelsim(VsimMakefileWriter): ...@@ -56,7 +56,7 @@ class ToolModelsim(VsimMakefileWriter):
self._clean_targets.update(ToolModelsim.CLEAN_TARGETS) self._clean_targets.update(ToolModelsim.CLEAN_TARGETS)
self._standard_libs.extend(ToolModelsim.STANDARD_LIBS) self._standard_libs.extend(ToolModelsim.STANDARD_LIBS)
def makefile_sim_options(self): def _makefile_sim_options(self):
"""Print the Modelsim options to the Makefile""" """Print the Modelsim options to the Makefile"""
if "sim_path" in self.manifest_dict: if "sim_path" in self.manifest_dict:
modelsim_ini_path = os.path.join( modelsim_ini_path = os.path.join(
...@@ -65,4 +65,4 @@ class ToolModelsim(VsimMakefileWriter): ...@@ -65,4 +65,4 @@ class ToolModelsim(VsimMakefileWriter):
else: else:
modelsim_ini_path = os.path.join("$(HDLMAKE_MODELSIM_PATH)", "..") modelsim_ini_path = os.path.join("$(HDLMAKE_MODELSIM_PATH)", "..")
self.custom_variables["MODELSIM_INI_PATH"] = modelsim_ini_path self.custom_variables["MODELSIM_INI_PATH"] = modelsim_ini_path
super(ToolModelsim, self).makefile_sim_options() super(ToolModelsim, self)._makefile_sim_options()
hdlmake/tools/quartus.py
View file @ 9cf5b959
...@@ -109,7 +109,7 @@ class ToolQuartus(ToolSyn): ...@@ -109,7 +109,7 @@ class ToolQuartus(ToolSyn):
self._clean_targets.update(ToolQuartus.CLEAN_TARGETS) self._clean_targets.update(ToolQuartus.CLEAN_TARGETS)
self._tcl_controls.update(ToolQuartus.TCL_CONTROLS) self._tcl_controls.update(ToolQuartus.TCL_CONTROLS)
def makefile_syn_top(self): def _makefile_syn_top(self):
"""Update project synthesis variables for Quartus""" """Update project synthesis variables for Quartus"""
import re import re
...@@ -144,7 +144,7 @@ class ToolQuartus(ToolSyn): ...@@ -144,7 +144,7 @@ class ToolQuartus(ToolSyn):
self.manifest_dict["syn_grade"]) self.manifest_dict["syn_grade"])
self.manifest_dict["syn_family"] = family_string self.manifest_dict["syn_family"] = family_string
self.manifest_dict["syn_device"] = device_string self.manifest_dict["syn_device"] = device_string
super(ToolQuartus, self).makefile_syn_top() super(ToolQuartus, self)._makefile_syn_top()
def _emit_property(self, command, new_property): def _emit_property(self, command, new_property):
"""Emit a formated property for Altera Quartus TCL""" """Emit a formated property for Altera Quartus TCL"""
...@@ -180,7 +180,7 @@ class ToolQuartus(ToolSyn): ...@@ -180,7 +180,7 @@ class ToolQuartus(ToolSyn):
words.append(property_dict['section_id']) words.append(property_dict['section_id'])
return ' '.join(words) return ' '.join(words)
def makefile_syn_tcl(self): def _makefile_syn_tcl(self):
"""Add initial properties to the Altera Quartus project""" """Add initial properties to the Altera Quartus project"""
command_list = [] command_list = []
command_list.append(self._tcl_controls["project"]) command_list.append(self._tcl_controls["project"])
...@@ -197,9 +197,9 @@ class ToolQuartus(ToolSyn): ...@@ -197,9 +197,9 @@ class ToolQuartus(ToolSyn):
{'name_type': 'TOP_LEVEL_ENTITY', {'name_type': 'TOP_LEVEL_ENTITY',
'name': '\\"$(TOP_MODULE)\\"'})) 'name': '\\"$(TOP_MODULE)\\"'}))
self._tcl_controls["project"] = '\n'.join(command_list) self._tcl_controls["project"] = '\n'.join(command_list)
super(ToolQuartus, self).makefile_syn_tcl() super(ToolQuartus, self)._makefile_syn_tcl()
def makefile_syn_files(self): def _makefile_syn_files(self):
# Insert the Quartus standard control TCL files # Insert the Quartus standard control TCL files
command_list = [] command_list = []
if "quartus_preflow" in self.manifest_dict: if "quartus_preflow" in self.manifest_dict:
...@@ -240,4 +240,4 @@ class ToolQuartus(ToolSyn): ...@@ -240,4 +240,4 @@ class ToolQuartus(ToolSyn):
{'name_type': 'POST_FLOW_SCRIPT_FILE', {'name_type': 'POST_FLOW_SCRIPT_FILE',
'name': postflow})) 'name': postflow}))
self._tcl_controls["files"] = '\n'.join(command_list) self._tcl_controls["files"] = '\n'.join(command_list)
super(ToolQuartus, self).makefile_syn_files() super(ToolQuartus, self)._makefile_syn_files()
hdlmake/tools/sim_makefile_support.py
View file @ 9cf5b959
...@@ -61,7 +61,7 @@ class VsimMakefileWriter(ToolSim): ...@@ -61,7 +61,7 @@ class VsimMakefileWriter(ToolSim):
self.copy_rules = {} self.copy_rules = {}
self._hdl_files.update(VsimMakefileWriter.HDL_FILES) self._hdl_files.update(VsimMakefileWriter.HDL_FILES)
def makefile_sim_options(self): def _makefile_sim_options(self):
"""Print the vsim options to the Makefile""" """Print the vsim options to the Makefile"""
def __get_rid_of_vsim_incdirs(vlog_opt=""): def __get_rid_of_vsim_incdirs(vlog_opt=""):
"""Parse the VLOG options and purge the included dirs""" """Parse the VLOG options and purge the included dirs"""
...@@ -86,7 +86,7 @@ class VsimMakefileWriter(ToolSim): ...@@ -86,7 +86,7 @@ class VsimMakefileWriter(ToolSim):
self.writeln("VLOG_FLAGS := %s" % (' '.join(self.vlog_flags))) self.writeln("VLOG_FLAGS := %s" % (' '.join(self.vlog_flags)))
self.writeln("VMAP_FLAGS := %s" % (' '.join(self.vmap_flags))) self.writeln("VMAP_FLAGS := %s" % (' '.join(self.vmap_flags)))
def makefile_sim_compilation(self): def _makefile_sim_compilation(self):
"""Write a properly formatted Makefile for the simulator. """Write a properly formatted Makefile for the simulator.
The Makefile format is shared, but flags, dependencies, clean rules, The Makefile format is shared, but flags, dependencies, clean rules,
etc are defined by the specific tool. etc are defined by the specific tool.
......
hdlmake/tools/vivado.py
View file @ 9cf5b959
...@@ -86,9 +86,9 @@ class ToolVivado(ToolXilinx, ToolSim): ...@@ -86,9 +86,9 @@ class ToolVivado(ToolXilinx, ToolSim):
self._tcl_controls.update(ToolVivado.TCL_CONTROLS) self._tcl_controls.update(ToolVivado.TCL_CONTROLS)
self._simulator_controls.update(ToolVivado.SIMULATOR_CONTROLS) self._simulator_controls.update(ToolVivado.SIMULATOR_CONTROLS)
def makefile_sim_compilation(self): def _makefile_sim_compilation(self):
"""Generate compile simulation Makefile target for Vivado Simulator""" """Generate compile simulation Makefile target for Vivado Simulator"""
self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)") self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("\t\t" + ToolVivado.SIMULATOR_CONTROLS['compiler']) self.writeln("\t\t" + ToolVivado.SIMULATOR_CONTROLS['compiler'])
self.writeln() self.writeln()
self.makefile_sim_dep_files() self._makefile_sim_dep_files()
hdlmake/tools/xilinx.py
View file @ 9cf5b959
...@@ -96,7 +96,7 @@ $(TCL_CLOSE)''' ...@@ -96,7 +96,7 @@ $(TCL_CLOSE)'''
properties.extend(syn_properties) properties.extend(syn_properties)
return properties return properties
def makefile_syn_tcl(self): def _makefile_syn_tcl(self):
"""Create a Xilinx synthesis project by TCL""" """Create a Xilinx synthesis project by TCL"""
prop_val = 'set_property "{0}" "{1}" [{2}]' prop_val = 'set_property "{0}" "{1}" [{2}]'
prop_opt = 'set_property -name {{{0}}} -value {{{1}}} -objects [{2}]' prop_opt = 'set_property -name {{{0}}} -value {{{1}}} -objects [{2}]'
...@@ -141,4 +141,4 @@ $(TCL_CLOSE)''' ...@@ -141,4 +141,4 @@ $(TCL_CLOSE)'''
self._tcl_controls["par"] = tmp_dict["par"].format( self._tcl_controls["par"] = tmp_dict["par"].format(
"impl_1", "impl_1",
"\n".join(par_new)) "\n".join(par_new))
super(ToolXilinx, self).makefile_syn_tcl() super(ToolXilinx, self)._makefile_syn_tcl()
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