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Hdlmake
Commit a76999c2 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Simulation tools are now a set of classes inherited by simulation action

parent 092e2524
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Showing with 54 additions and 18 deletions
hdlmake/action/simulation.py
View file @ a76999c2
......@@ -31,8 +31,13 @@ from hdlmake.dep_file import DepFile
#import hdlmake.new_dep_solver as dep_solver
from .action import Action
from hdlmake.tools import (
ToolIVerilog, ToolISim, ToolModelsim,
ToolActiveHDL, ToolRiviera, ToolGHDL)
class GenerateSimulationMakefile(Action):
class GenerateSimulationMakefile(Action,
ToolIVerilog, ToolISim, ToolModelsim,
ToolActiveHDL, ToolRiviera, ToolGHDL):
"""This class contains the simulation specific methods"""
def _check_simulation_makefile(self):
......@@ -50,8 +55,20 @@ class GenerateSimulationMakefile(Action):
self._check_all_fetched_or_quit()
self._check_simulation_makefile()
tool_name = self.get_top_module().manifest_dict["sim_tool"]
tool_module = importlib.import_module("hdlmake.tools.%s.%s" % (tool_name, tool_name))
tool_object = tool_module.ToolControls()
if tool_name is "iverilog":
tool_object = ToolIVerilog()
elif tool_name is "isim":
tool_object = ToolISim()
elif tool_name is "modelsim":
tool_object = ToolModelsim()
elif tool_name is "active-hdl":
tool_object = ToolActiveHDL()
elif tool_name is "riviera":
tool_object = ToolRiviera()
elif tool_name is "ghdl":
tool_object = ToolGHDL()
tool_info = tool_object.get_keys()
if sys.platform == 'cygwin':
bin_name = tool_info['windows_bin']
......
hdlmake/makefile_writer.py
View file @ a76999c2
......@@ -41,6 +41,7 @@ class MakefileWriter(object):
self._filename = filename
else:
self._filename = "Makefile"
super(MakefileWriter, self).__init__()
def __del__(self):
if self._file:
......
hdlmake/tools/__init__.py
View file @ a76999c2
from .iverilog import ToolIVerilog
from .isim import ToolISim
from .modelsim import ToolModelsim
from .active_hdl import ToolActiveHDL
from .riviera import ToolRiviera
from .ghdl import ToolGHDL
from .sim_makefile_support import VsimMakefileWriter
hdlmake/tools/aldec/aldec.py → hdlmake/tools/active_hdl.py
View file @ a76999c2
......@@ -26,7 +26,10 @@ import string
from hdlmake.makefile_writer import MakefileWriter
class ToolControls(MakefileWriter):
class ToolActiveHDL(MakefileWriter):
def __init__(self):
super(ToolActiveHDL, self).__init__()
def detect_version(self, path):
pass
......
hdlmake/tools/common/__init__.py deleted 100644 → 0
View file @ 092e2524
"""Common functionality shared by multiple tools."""
hdlmake/tools/ghdl/ghdl.py → hdlmake/tools/ghdl.py
View file @ a76999c2
......@@ -25,7 +25,10 @@ import string
from hdlmake.makefile_writer import MakefileWriter
class ToolControls(MakefileWriter):
class ToolGHDL(MakefileWriter):
def __init__(self):
super(ToolGHDL, self).__init__()
def detect_version(self, path):
pass
......
hdlmake/tools/isim/isim.py → hdlmake/tools/isim.py
View file @ a76999c2
......@@ -40,7 +40,10 @@ ISIM_STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
'simprims_ver', 'unisims_ver', 'uni9000_ver',
'unimacro_ver', 'xilinxcorelib_ver', 'secureip']
class ToolControls(MakefileWriter):
class ToolISim(MakefileWriter):
def __init__(self):
super(ToolISim, self).__init__()
def get_keys(self):
tool_info = {
......@@ -196,8 +199,9 @@ isim.wdb isim_proj isim_proj.*
#incdir = "-i "
#incdir += " -i ".join(vl.include_dirs)
#incdir += " "
self.write(' -i ')
self.write(' '.join(vl.include_dirs) + ' ')
if vl.include_dirs:
self.write(' -i ')
self.write(' '.join(vl.include_dirs) + ' ')
self.writeln(vl.vlog_opt+" $<")
self.write("\t\t@mkdir -p $(dir $@)")
self.writeln(" && touch $@ \n\n")
......
hdlmake/tools/iverilog/iverilog.py → hdlmake/tools/iverilog.py
View file @ a76999c2
......@@ -36,8 +36,10 @@ IVERILOG_STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
'simprims_ver', 'unisims_ver', 'uni9000_ver',
'unimacro_ver', 'xilinxcorelib_ver', 'secureip']
class ToolControls(MakefileWriter):
class ToolIVerilog(MakefileWriter):
def __init__(self):
super(ToolIVerilog, self).__init__()
def get_keys(self):
tool_info = {
......
hdlmake/tools/modelsim/modelsim.py → hdlmake/tools/modelsim.py
View file @ a76999c2
......@@ -25,16 +25,16 @@ from __future__ import print_function
import xml.dom.minidom
import os
from ..common.sim_makefile_support import VsimMakefileWriter
from .sim_makefile_support import VsimMakefileWriter
XmlImpl = xml.dom.minidom.getDOMImplementation()
MODELSIM_STANDARD_LIBS = ['ieee', 'std', 'altera_mf']
class ToolControls(VsimMakefileWriter):
class ToolModelsim(VsimMakefileWriter):
def __init__(self):
super(ToolControls, self).__init__()
super(ToolModelsim, self).__init__()
def detect_version(self, path):
pass
......@@ -69,5 +69,5 @@ class ToolControls(VsimMakefileWriter):
self.additional_clean.extend(["./modelsim.ini", "transcript", "*.vcd", "*.wlf"])
self.copy_rules["modelsim.ini"] = os.path.join("$(MODELSIM_INI_PATH)", "modelsim.ini")
super(ToolControls, self).generate_simulation_makefile(fileset, top_module)
super(ToolModelsim, self).generate_simulation_makefile(fileset, top_module)
hdlmake/tools/riviera/riviera.py → hdlmake/tools/riviera.py
View file @ a76999c2
......@@ -23,7 +23,7 @@
#
from __future__ import print_function
from ..common.sim_makefile_support import VsimMakefileWriter
from .sim_makefile_support import VsimMakefileWriter
# as of 2014.06, these are the standard libraries
# included in an installation
......@@ -60,9 +60,9 @@ RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VHDL_LIBRARIES)
RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VLOG_LIBRARIES)
class ToolControls(VsimMakefileWriter):
class ToolRiviera(VsimMakefileWriter):
def __init__(self):
super(ToolControls, self).__init__()
super(ToolRiviera, self).__init__()
self.vcom_flags.append("-2008")
self.additional_clean.extend(["*.asdb", "*.vcd", ])
......
hdlmake/tools/common/sim_makefile_support.py → hdlmake/tools/sim_makefile_support.py
View file @ a76999c2
......@@ -94,7 +94,7 @@ PWD := $(shell pwd)
self.writeln("VSIM_FLAGS := %s" % (' '.join(self.vsim_flags)))
self.writeln("VLOG_FLAGS := %s" % (' '.join(self.vlog_flags)))
self.writeln("VMAP_FLAGS := %s" % (' '.join(self.vmap_flags)))
self.writeln("INCLUDE_DIRS := +incdir+%s" % ('+'.join(top_module.include_dirs)))
#self.writeln("INCLUDE_DIRS := +incdir+%s" % ('+'.join(top_module.include_dirs)))
self.write("VERILOG_SRC := ")
for vl in fileset.filter(VerilogFile):
......
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