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Commit a90100a1 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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First tests for integrating Vivado Simulator

parent b89ecb22
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Showing with 30 additions and 4 deletions
hdlmake/action/simulation.py
View file @ a90100a1
...@@ -60,7 +60,8 @@ class ActionSimulation(Action): ...@@ -60,7 +60,8 @@ class ActionSimulation(Action):
"modelsim": self.sim_writer.modelsim, "modelsim": self.sim_writer.modelsim,
"active-hdl": self.sim_writer.active_hdl, "active-hdl": self.sim_writer.active_hdl,
"riviera": self.sim_writer.riviera, "riviera": self.sim_writer.riviera,
"ghdl": self.sim_writer.ghdl} "ghdl": self.sim_writer.ghdl,
"vivado": self.sim_writer.vivado}
if not tool_name in tool_dict: if not tool_name in tool_dict:
logging.error("Unknown sim_tool: %s", tool_name) logging.error("Unknown sim_tool: %s", tool_name)
sys.exit("Exiting") sys.exit("Exiting")
......
hdlmake/tools/vivado.py
View file @ a90100a1
...@@ -25,11 +25,12 @@ ...@@ -25,11 +25,12 @@
from .xilinx import ToolXilinx from .xilinx import ToolXilinx
from .make_sim import ToolSim
from hdlmake.srcfile import (UCFFile, NGCFile, XMPFile, from hdlmake.srcfile import (UCFFile, NGCFile, XMPFile,
XCOFile, BDFile, TCLFile) XCOFile, BDFile, TCLFile)
class ToolVivado(ToolXilinx): class ToolVivado(ToolXilinx, ToolSim):
"""Class providing the interface for Xilinx Vivado synthesis""" """Class providing the interface for Xilinx Vivado synthesis"""
...@@ -46,17 +47,31 @@ class ToolVivado(ToolXilinx): ...@@ -46,17 +47,31 @@ class ToolVivado(ToolXilinx):
SUPPORTED_FILES = [UCFFile, NGCFile, XMPFile, SUPPORTED_FILES = [UCFFile, NGCFile, XMPFile,
XCOFile, BDFile, TCLFile] XCOFile, BDFile, TCLFile]
CLEAN_TARGETS = {'clean': ["run.tcl", ".Xil", "*.jou", "*.log", CLEAN_TARGETS = {'clean': ["run.tcl", ".Xil", "*.jou", "*.log", "*.pb",
"$(PROJECT).cache", "$(PROJECT).data", "$(PROJECT).cache", "$(PROJECT).data", "work",
"$(PROJECT).runs", "$(PROJECT_FILE)"]} "$(PROJECT).runs", "$(PROJECT_FILE)"]}
TCL_CONTROLS = {'bitstream': 'launch_runs impl_1 -to_step write_bitstream' TCL_CONTROLS = {'bitstream': 'launch_runs impl_1 -to_step write_bitstream'
'\n' '\n'
'wait_on_run impl_1'} 'wait_on_run impl_1'}
SIMULATOR_CONTROLS = {'vlog': 'xvlog $<',
'vhdl': 'xvhdl $<',
'compiler': 'xelab $(TOP_MODULE) -s $(TOP_MODULE)'}
def __init__(self): def __init__(self):
super(ToolVivado, self).__init__() super(ToolVivado, self).__init__()
self._tool_info.update(ToolVivado.TOOL_INFO) self._tool_info.update(ToolVivado.TOOL_INFO)
self._supported_files.extend(ToolVivado.SUPPORTED_FILES) self._supported_files.extend(ToolVivado.SUPPORTED_FILES)
self._clean_targets.update(ToolVivado.CLEAN_TARGETS) self._clean_targets.update(ToolVivado.CLEAN_TARGETS)
self._tcl_controls.update(ToolVivado.TCL_CONTROLS) self._tcl_controls.update(ToolVivado.TCL_CONTROLS)
def makefile_sim_compilation(self):
"""Generate compile simulation Makefile target for Vivado Simulator"""
self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("\t\t" + ToolVivado.SIMULATOR_CONTROLS['compiler'])
self.writeln()
self.makefile_sim_dep_files(ToolVivado.SIMULATOR_CONTROLS['vhdl'])
hdlmake/tools/writer.py
View file @ a90100a1
...@@ -20,6 +20,7 @@ class WriterSim(object): ...@@ -20,6 +20,7 @@ class WriterSim(object):
self.active_hdl = ToolActiveHDL() self.active_hdl = ToolActiveHDL()
self.riviera = ToolRiviera() self.riviera = ToolRiviera()
self.ghdl = ToolGHDL() self.ghdl = ToolGHDL()
self.vivado = ToolVivado()
class WriterSyn(object): class WriterSyn(object):
......
tests/counter/sim/vivado/vhdl/Manifest.py 0 → 100644
View file @ a90100a1
action = "simulation"
sim_tool = "vivado"
sim_top = "counter_tb"
sim_post_cmd = "xsim %s -gui" % sim_top
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
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